JP2002158289A5 - - Google Patents
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- Publication number
- JP2002158289A5 JP2002158289A5 JP2001241483A JP2001241483A JP2002158289A5 JP 2002158289 A5 JP2002158289 A5 JP 2002158289A5 JP 2001241483 A JP2001241483 A JP 2001241483A JP 2001241483 A JP2001241483 A JP 2001241483A JP 2002158289 A5 JP2002158289 A5 JP 2002158289A5
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- fuse link
- logic level
- latch
- link
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001960 triggered effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Images
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/634790 | 2000-08-09 | ||
| US09/634,790 US6400208B1 (en) | 2000-08-09 | 2000-08-09 | On-chip trim link sensing and latching circuit for fuse links |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002158289A JP2002158289A (ja) | 2002-05-31 |
| JP2002158289A5 true JP2002158289A5 (cg-RX-API-DMAC7.html) | 2004-10-07 |
Family
ID=24545194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001241483A Pending JP2002158289A (ja) | 2000-08-09 | 2001-08-09 | ヒューズリンクのためのオンチップトリムリンク感知ラッチ回路 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6400208B1 (cg-RX-API-DMAC7.html) |
| EP (1) | EP1184874B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2002158289A (cg-RX-API-DMAC7.html) |
| KR (1) | KR100794479B1 (cg-RX-API-DMAC7.html) |
| DE (1) | DE60107633T2 (cg-RX-API-DMAC7.html) |
| TW (1) | TW522407B (cg-RX-API-DMAC7.html) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100470168B1 (ko) * | 2002-05-27 | 2005-02-07 | 주식회사 하이닉스반도체 | 안티퓨즈 회로 |
| US6670843B1 (en) * | 2002-07-31 | 2003-12-30 | Advanced Micro Devices, Inc. | Method and apparatus for sensing a programming state of fuses |
| KR100481179B1 (ko) * | 2002-09-10 | 2005-04-07 | 삼성전자주식회사 | 퓨즈를 구비한 회로 및 이를 이용한 반도체 장치 |
| KR100660899B1 (ko) * | 2005-12-15 | 2006-12-26 | 삼성전자주식회사 | 누설 전류 패스를 제거할 수 있는 퓨즈 회로 |
| US20080211513A1 (en) * | 2007-02-15 | 2008-09-04 | Stmicroelectronics, Inc. | Initiation of fuse sensing circuitry and storage of sensed fuse status information |
| KR100930411B1 (ko) * | 2008-04-10 | 2009-12-08 | 주식회사 하이닉스반도체 | 퓨즈 정보 제어 장치, 이를 이용한 반도체 집적회로 및그의 퓨즈 정보 제어 방법 |
| KR101050110B1 (ko) * | 2009-12-28 | 2011-07-19 | 전자부품연구원 | 공정변화를 보정하기 위한 퓨징장치 |
| CN112986796A (zh) * | 2021-02-07 | 2021-06-18 | 昂宝电子(上海)有限公司 | 用于芯片的参数修调装置和方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01184796A (ja) * | 1988-01-19 | 1989-07-24 | Nec Corp | 半導体メモリ装置 |
| KR900008554B1 (ko) * | 1988-04-23 | 1990-11-24 | 삼성전자 주식회사 | 메모리 동작모드 선택회로 |
| US5345110A (en) * | 1993-04-13 | 1994-09-06 | Micron Semiconductor, Inc. | Low-power fuse detect and latch circuit |
| JP3080520B2 (ja) * | 1993-09-21 | 2000-08-28 | 富士通株式会社 | シンクロナスdram |
| KR0144711B1 (ko) * | 1994-12-13 | 1998-08-17 | 김광호 | 반도체 메모리장치의 테스트 제어회로 및 방법 |
| JPH08274266A (ja) * | 1995-03-29 | 1996-10-18 | Hitachi Ltd | ヒューズトリミング回路及びそれを備えた半導体集積回路 |
| KR0164378B1 (ko) * | 1995-04-13 | 1999-02-18 | 김광호 | 반도체 메모리장치의 퓨즈 상태 감지회로 |
| KR0147194B1 (ko) * | 1995-05-26 | 1998-11-02 | 문정환 | 반도체 메모리 소자 |
| KR100204340B1 (ko) * | 1996-06-19 | 1999-06-15 | 윤종용 | 메모리 장치의 모드 셋팅 회로 |
| US5933376A (en) | 1997-02-28 | 1999-08-03 | Lucent Technologies Inc. | Semiconductor memory device with electrically programmable redundancy |
| US5991220A (en) | 1998-03-09 | 1999-11-23 | Lucent Technologies, Inc. | Software programmable write-once fuse memory |
| US6028756A (en) | 1998-03-11 | 2000-02-22 | Lucent Technologies, Inc. | Using topological features to lower the blowing current needed for fuses |
| JP2000132990A (ja) * | 1998-10-27 | 2000-05-12 | Fujitsu Ltd | 冗長判定回路、半導体記憶装置及び冗長判定方法 |
| JP2000200497A (ja) * | 1998-11-05 | 2000-07-18 | Nec Corp | ヒュ―ズ判定回路およびメモリの冗長設定回路 |
-
2000
- 2000-08-09 US US09/634,790 patent/US6400208B1/en not_active Expired - Lifetime
-
2001
- 2001-08-08 TW TW090119338A patent/TW522407B/zh not_active IP Right Cessation
- 2001-08-09 JP JP2001241483A patent/JP2002158289A/ja active Pending
- 2001-08-09 KR KR1020010048001A patent/KR100794479B1/ko not_active Expired - Fee Related
- 2001-08-09 DE DE60107633T patent/DE60107633T2/de not_active Expired - Lifetime
- 2001-08-09 EP EP01306816A patent/EP1184874B1/en not_active Expired - Lifetime
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