JP2002093168A5 - - Google Patents

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Publication number
JP2002093168A5
JP2002093168A5 JP2000277108A JP2000277108A JP2002093168A5 JP 2002093168 A5 JP2002093168 A5 JP 2002093168A5 JP 2000277108 A JP2000277108 A JP 2000277108A JP 2000277108 A JP2000277108 A JP 2000277108A JP 2002093168 A5 JP2002093168 A5 JP 2002093168A5
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JP
Japan
Prior art keywords
signal
mask
circuit
generation circuit
mask method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000277108A
Other languages
English (en)
Japanese (ja)
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JP2002093168A (ja
JP4025002B2 (ja
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Publication date
Application filed filed Critical
Priority to JP2000277108A priority Critical patent/JP4025002B2/ja
Priority claimed from JP2000277108A external-priority patent/JP4025002B2/ja
Priority to US09/951,230 priority patent/US6483772B2/en
Publication of JP2002093168A publication Critical patent/JP2002093168A/ja
Publication of JP2002093168A5 publication Critical patent/JP2002093168A5/ja
Application granted granted Critical
Publication of JP4025002B2 publication Critical patent/JP4025002B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000277108A 2000-09-12 2000-09-12 半導体記憶装置 Expired - Fee Related JP4025002B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000277108A JP4025002B2 (ja) 2000-09-12 2000-09-12 半導体記憶装置
US09/951,230 US6483772B2 (en) 2000-09-12 2001-09-12 Semiconductor memory device capable of masking data to be written

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000277108A JP4025002B2 (ja) 2000-09-12 2000-09-12 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2002093168A JP2002093168A (ja) 2002-03-29
JP2002093168A5 true JP2002093168A5 (enExample) 2005-06-02
JP4025002B2 JP4025002B2 (ja) 2007-12-19

Family

ID=18762487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000277108A Expired - Fee Related JP4025002B2 (ja) 2000-09-12 2000-09-12 半導体記憶装置

Country Status (2)

Country Link
US (1) US6483772B2 (enExample)
JP (1) JP4025002B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6671212B2 (en) 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
US6957308B1 (en) 2002-07-11 2005-10-18 Advanced Micro Devices, Inc. DRAM supporting different burst-length accesses without changing the burst length setting in the mode register
JP2004213337A (ja) * 2002-12-27 2004-07-29 Nec Computertechno Ltd 半導体記憶装置及び実装型半導体装置
JP4505195B2 (ja) * 2003-04-01 2010-07-21 エイティアイ テクノロジーズ インコーポレイテッド メモリデバイスにおいてデータを反転させるための方法および装置
WO2007099447A2 (en) * 2006-03-02 2007-09-07 Nokia Corporation Method and system for flexible burst length control
US20080059748A1 (en) * 2006-08-31 2008-03-06 Nokia Corporation Method, mobile device, system and software for a write method with burst stop and data masks
JP2008198280A (ja) * 2007-02-13 2008-08-28 Elpida Memory Inc 半導体記憶装置及びその動作方法
KR20100101449A (ko) * 2009-03-09 2010-09-17 삼성전자주식회사 메모리 장치, 그것의 마스크 데이터 전송 방법 및 입력 데이터 정렬 방법
JP5726425B2 (ja) * 2010-03-04 2015-06-03 エイティアイ テクノロジーズ インコーポレイテッド メモリデバイスにおいてデータを反転させるための方法および装置
KR101133686B1 (ko) * 2010-05-28 2012-04-12 에스케이하이닉스 주식회사 반도체 장치와 그의 동작 방법
US10846253B2 (en) 2017-12-21 2020-11-24 Advanced Micro Devices, Inc. Dynamic page state aware scheduling of read/write burst transactions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3756231B2 (ja) 1995-12-19 2006-03-15 株式会社ルネサステクノロジ 同期型半導体記憶装置
KR100364127B1 (ko) * 1997-12-29 2003-04-11 주식회사 하이닉스반도체 칩-세트
US6219747B1 (en) * 1999-01-06 2001-04-17 Dvdo Inc Methods and apparatus for variable length SDRAM transfers

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