JP2006145527A5 - - Google Patents

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Publication number
JP2006145527A5
JP2006145527A5 JP2005326186A JP2005326186A JP2006145527A5 JP 2006145527 A5 JP2006145527 A5 JP 2006145527A5 JP 2005326186 A JP2005326186 A JP 2005326186A JP 2005326186 A JP2005326186 A JP 2005326186A JP 2006145527 A5 JP2006145527 A5 JP 2006145527A5
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JP
Japan
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register
data capture
pads
data
output
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Pending
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JP2005326186A
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English (en)
Japanese (ja)
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JP2006145527A (ja
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Priority claimed from US10/996,113 external-priority patent/US7640468B2/en
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Publication of JP2006145527A publication Critical patent/JP2006145527A/ja
Publication of JP2006145527A5 publication Critical patent/JP2006145527A5/ja
Pending legal-status Critical Current

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JP2005326186A 2004-11-23 2005-11-10 埋め込み型時間領域反射率試験の方法及び装置 Pending JP2006145527A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/996,113 US7640468B2 (en) 2004-11-23 2004-11-23 Method and apparatus for an embedded time domain reflectometry test

Publications (2)

Publication Number Publication Date
JP2006145527A JP2006145527A (ja) 2006-06-08
JP2006145527A5 true JP2006145527A5 (enExample) 2008-03-27

Family

ID=34654497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005326186A Pending JP2006145527A (ja) 2004-11-23 2005-11-10 埋め込み型時間領域反射率試験の方法及び装置

Country Status (3)

Country Link
US (1) US7640468B2 (enExample)
JP (1) JP2006145527A (enExample)
GB (1) GB2420421A (enExample)

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US7250784B2 (en) 2005-06-29 2007-07-31 Marvell International Ltd. Integrated systems testing
KR100692529B1 (ko) * 2005-07-01 2007-03-09 삼성전자주식회사 최적화된 딜레이 타임 결정 방법, 장치 및 최적화된 딜레이타임 결정 프로그램이 기록된 컴퓨터로 판독 가능한기록매체
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US8024631B1 (en) * 2006-11-07 2011-09-20 Marvell International Ltd. Scan testing system and method
US8117460B2 (en) * 2007-02-14 2012-02-14 Intel Corporation Time-domain reflectometry used to provide biometric authentication
DE102007037377B4 (de) 2007-08-08 2018-08-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Detektion von durch Unterbrechungen charakterisierbare Fehlstellen in Leitbahnnetzwerken
US8829940B2 (en) * 2008-09-26 2014-09-09 Nxp, B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
US9043662B2 (en) * 2009-03-30 2015-05-26 Cadence Design Systems, Inc. Double data rate memory physical interface high speed testing using self checking loopback
US20120081129A1 (en) * 2009-06-03 2012-04-05 Advantest Corporation Test apparatus
US8489947B2 (en) * 2010-02-15 2013-07-16 Mentor Graphics Corporation Circuit and method for simultaneously measuring multiple changes in delay
JP2012189396A (ja) * 2011-03-09 2012-10-04 Mitsubishi Electric Corp Ｉｃチップ、半導体部品、検査用プローブ、ハンディマルチテスター、及び通信装置
US9640280B1 (en) * 2015-11-02 2017-05-02 Cadence Design Systems, Inc. Power domain aware insertion methods and designs for testing and repairing memory
US10666540B2 (en) 2017-07-17 2020-05-26 International Business Machines Corporation Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
US10564219B2 (en) 2017-07-27 2020-02-18 Teradyne, Inc. Time-aligning communication channels
JP7404646B2 (ja) * 2019-04-23 2023-12-26 ブラザー工業株式会社 入出力基板及び工作機械
US10890623B1 (en) 2019-09-04 2021-01-12 International Business Machines Corporation Power saving scannable latch output driver
US10897239B1 (en) 2019-09-06 2021-01-19 International Business Machines Corporation Granular variable impedance tuning

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254942A (en) * 1991-04-25 1993-10-19 Daniel D'Souza Single chip IC tester architecture
DE4221435C2 (de) 1992-06-30 1994-05-05 Siemens Ag Elektronischer Baustein mit einer taktgesteuerten Schieberegisterprüfarchitektur (Boundary-Scan)
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US6020757A (en) * 1998-03-24 2000-02-01 Xilinx, Inc. Slew rate selection circuit for a programmable device
US6266793B1 (en) * 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
US6397361B1 (en) * 1999-04-02 2002-05-28 International Business Machines Corporation Reduced-pin integrated circuit I/O test
DE19938060B4 (de) 1999-08-12 2008-06-19 Nokia Siemens Networks Gmbh & Co.Kg Integrierte Schaltung mit einer Testeinrichtung und Verfahren zum Testen der Güte elektrischer Verbindungen der ingegrierten Schaltung
US6477674B1 (en) * 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements
US20020095633A1 (en) 2000-10-05 2002-07-18 Ulf Pillkahn Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board
US6714021B2 (en) 2001-01-11 2004-03-30 Sun Microsystems, Inc. Integrated time domain reflectometry (TDR) tester
US6724210B2 (en) 2001-08-22 2004-04-20 International Business Machines Corporation Method and apparatus for reduced pin count package connection verification
US6862546B2 (en) 2002-02-22 2005-03-01 Intel Corporation Integrated adjustable short-haul/long-haul time domain reflectometry
JP3798713B2 (ja) * 2002-03-11 2006-07-19 株式会社東芝 半導体集積回路装置及びそのテスト方法
US6802046B2 (en) 2002-05-01 2004-10-05 Agilent Technologies, Inc. Time domain measurement systems and methods
US6986087B2 (en) 2002-09-09 2006-01-10 Hewlett-Packard Development Company, L.P. Method and apparatus for improving testability of I/O driver/receivers

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