TWI295425B - High access speed flash controller - Google Patents

Description

1295425 IX. Description of the Invention: [Technical Field] The present invention relates to a flash memory controller component, and more particularly to a flash memory chip capable of high speed access; Flash memory controller. , "Heart [Prior Art] The design of the $step circuit has been widely used in the design of Ic circuits. This way of constructing on the clock makes the action eda

Tool can help circuit design engineers to easily and accurately divide the circuit. 0 Because the flash memory of the flash memory controller is a 2-step ίί interface (Interface), and the different manufacturers make = flash The reaction coffee may be different, even the side manufacturers produce different types of (four) record dragons and their reverse may not be side, so the general device in response to different manufacturers of flash memory or take m ̄ w = class The flash memory of the large-capacity flash memory disk is taken when the stock is on the 眺 _ spicy will occur on the L surface. *DriVlngCapability is weaker in the flash memory data bus. On the large-capacity two-two if disk, 111 is necessary to match multiple flash memories to make the load become heavier. At this time, because of the large g system of the flash memory. The speed of accessing the flash memory disk is caused by the drive capability of the flash memory, which causes the flash memory disk to be on the -1295425 to maintain the volume on the disk. The purpose of the present invention is to overcome the above problems. SUMMARY OF THE INVENTION Synchronization and ίίίί In the flash memory controller, the same speed can be achieved when using the same type of clock memory. The high-speed circuit is achieved without lowering the work ==) parameter setting; the bidirectional feedback input-input delay chain has been output to the flash memory crystal feedback delay chain circuit, and the data bus is sampled and received; —=== ίί iii take d the lean bus sampler' to provide the data sink [embodiment] In view of the prior art, the flash memory controller with a different number of 1295425, will depend on (four) amount Causing trouble or stretching the two delay chains (Delay Chain) with a feedback external

Feedback) improves the read/write speed of the fast memory control. One of the delays is 2, and the second is in the 4 in/i flash memory controller. The writing of the external memory is performed in the design of the control 11 of the outer = to achieve the flash memory. Flash memory controller 5 hardware 2 for different applications 2 write signals and flash memory ======= similar ^ 2 ^ ί 体 body controller 5 can be matched with several phases at the same time

The SiiiS fast chip 7 can still correctly control the output contact pad _2, the sampling point m, the ΐ枓Ξ1 〇1, and the second input/output contact pad (10) 2) 35. Standing

The signal of the S=_)20 feedback can be two;; S 1295425 must satisfy the correct or incorrect writing when the line is taken. The present invention uses the above two external ίτ<^ϊίΓ two-way feedback input and output contact pads (10) 1) 20 feedback. fHw Tiger's way to improve access speed. L^ and π in the flash memory control 11 to make the timing of the synchronization of the reading of the writing Aead / Write Pulse) after the delay chain adjustment makes fast ^ = Μ Μ money can eliminate flash flash control and flash Timing Latency between memories.

Trea

Twh

Twp

Trc

Tdh

Tds 18 ns 10 15 30 5 15 ns ns ns ns ns In Table 1, the minimum value of the read/write R/W pulse period Trc specification is 30 ns, and when the R/W pulse is in the low state (read), the data appears from The data bus, (data bus) and the maximum read and write access time (RE access time) to the end of the transit time (trans access time) is 18ns, while the minimum maintenance of the R/W pulse is high.

• 1295425 State time (write) write enable continues trick r time) Twh is l〇ns. Tdh is the alias ^ A \ (AWnte enable hold is still the smallest in the data bus; ' (4) minimum data maintenance time, such as the table _ dry 3 Bechui muscles into the enable pulse width (see the table! Don't say = for flash flash control 11 pairs of flash memory read and write points when performing write data in flash memory · flash memory 'for Twh, Twp, Tdh and Tds ϊϋ ίίί. The flash memory controller puts the valid data for generating the write signal on the data bus, so Tdh and Tds are very easy and fast flashing, so the bottleneck of high-speed writing and reading flash memory is in accordance with Twh. And Twp time specification. When a control chip is set up, flashing, at any time, the read and write signals generated by the synchronization circuit are difficult to meet the requirements of various types of flash memory under the dazzling access speed. The present invention utilizes a delay chain design to produce an optimized write operation. Referring to Figure 4, the read and write pulse delay chain circuit 15 for the write signal is shown. The delayed cells ΐβ in the figure represent a delay circuit, respectively. And Figure 5 shows the right The signal response after the delay signal of the write signal and the different delay lengths. The signal response in Figure 5 responds to b, c, d, e and the original input signal a. It corresponds to the fixed pulse width generated by the synchronization circuit (Pulse) Wid also) signal, the original input signal a and the delay chain circuit of the unequal delay length and the gate (MD gate) 17 operation, generate low-level read and write signals of different widths, and flash with 11 -1295425 f ί ΐΐ ϋ Memory chip requirements for Twh and twp. Re:it. T with, memory chip, the purchase of the program will be related to the multiplexer 读写 体 晶片 晶片 晶片 ί ί ί ί ί ί ί ί ί The tiger meets the time of the various flashovers and flashes. The ϋ 体 日 7 7 7 7 7 ^ 闪 闪 闪 闪 闪 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 在 在 都能 都能 都能 都能 都能 都能 都能When the maximum speed is written, when the data is read from the flash memory, the flash memory controller 5 performs the reading time of the flash memory chip, and = 2: B. Data bus. The invention utilizes a kind of returning body to the most?: read in;: make ~^ Mmllliming will be significantly affected by the use of (four) the number of carcasses and the fast Ιϊ ί ί ί ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ At the beginning of the point (Fig.: The correctness of the access of the material 8 12 1295425] flashes quickly - it will fall at point C. ° But when the controller internal data sampler is sampling the flash memory, because Fast ^ flash memory array on the array appears to appear in the material g miscellaneous 42, ^ ^ body's 'turning ability is weak, so the signal before the effective data D point because the fast ^ ^ will fall after the D point . In an untrustworthy transient signal. , ^ force is weak, so the sampling point is still fixed at the c point flash memory controller synchronization circuit body 'Tiyi block sound map, turn ^ map - no flash memory controller 5 circuit side sampling point For the detailed circuit of the delay chain circuit 25, please refer to the circuit diagram® in Figure 7. The basic electrical pulse delay chain circuit 15 of the sample point extension circuit 25 is similar in that it includes a delay cell 26 and a large but omitted AND gate design. Please refer to Figure 8. After the delay of the cell, the signal only produces displacement, and does not change the R/w pulse width. The competition changes the sampling point of the data in the data bus. In the case of multiple flashes, the firmware can also be used to control the output of the delay chain circuit: so that the sample point of the data sampler falls after the D point, the data can be correctly sampled by the sampler. take. Figure 9 is a diagram showing an equivalent circuit of a bidirectional return wheel access contact 塾 (PAD1) in accordance with an embodiment of the present invention. In general, 'PAD is to transmit the signal inside the integrated circuit to an external circuit (here, the flash memory 'body chip

13 1295425 2备而Λ7 „The intersection of the (four) current so the plane area will be larger, and you ~ 凡 凡 凡 凡 占 占 占 占 占

Γ Γ T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T It is the hall, * Μ \ αΓ Γ) that receives the literacy signal, so the valid data appears in the data; =: ϊϊ ί appears after the time of Trea+Td, this iii, t over-time PAD ( PAD2) time delay will enter / (4) Sampling $ on the time of obtaining valid data, the point may occur (Figure 3). Therefore, if the flash memory controller 5 is internally sent via PAD (4) u to flash The memory chip 7 and the (four) memory chip 7 receive the information received by the master and then provide the data to the data bus and then transmitted back through the PAD 钤f 夬 丨 丨 丨 丨 控制器 控制器 控制器 controller 5, obviously there will be two Sub-pad delay. Therefore, the present invention replaces the input/output contact pad PAD with the bidirectional feedback input/output contact (塾) (PAD1) 20 and combines the sample point delay chain circuit 25 to eliminate the pad delay twice. Still referring to the bidirectional feedback input and output contact pad (PAD1) 2〇 of Figure 9, the control signal of the secondary material read out the bidirectional feedback input and output contact pad (PAD1) 2〇2 output buffer 20a and feed back again The input buffer 20b of the input/output port (PAD1) 20 is fed back, and the control of the data reading can be offset by the PAD1 20 and the data is delayed by the PAD2 35 twice. $ is selected by the point delay chain circuit 25 to select the most appropriate sampling point, which can be used; ^Bao Zi 1 14 1295425 Advantages of the invention: ▲ (1) The same hardware can be applied without lowering the access speed. The optimal access speed is also achieved by the different day-to-day specifications of flash memory chips of different numbers or different manufacturers. (2) The flash memory controller can be applied to the flash memory of different capacities, and the fastest access speed can be obtained on the 1st disc. Because the frequency reduction type is not needed, the external power supply design should also be targeted. Make any changes to the flash memory disk in the different valleys. The preferred embodiment of the invention has been modified and modified, and should be included in the following patent application.

1295425 [Brief Description of the Drawings] Figure 1 shows a schematic diagram of a flash memory controller in accordance with an embodiment of the present invention, with a plurality of flash memory chips of the same type or different types. "W-FIG. - shows a block diagram of a circuit in which the flash memory is controlled internally according to an embodiment of the present invention. Figure 2 shows a schematic diagram of the read and write pulses of the flash memory must conform to the time specification. Figure 4 shows a schematic diagram in accordance with the present invention. A schematic diagram of a read/write pulse delay chain circuit in an embodiment. A circuit ϊ ί ί 实 实 实 实 实 f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f f Chain electric power 0 (4) - Example (4) Sampler delay delay reading and writing material miscellaneous chain circuit Figure 9 shows the most suitable touch pad (10) υ material effect circuit ^ Figure ^ example two-way feedback output _ ^ Τψ % ΑΝϋ gate))j road 15 16 8 1295425

Output buffer 20a Input buffer 20b Sample point delay chain circuit 25 Delay cell 16, 26 multiplexer 18, 28 Data bus sampler 30 Second input and output contact pad (PAD2) 35 Single chip when data bus status 41 Chip time data bus status 42 17 8

Claims (1)

1295425 X. Patent application scope · · System 1 (4) Memory chip control _ memory control u Wang Xiba 兮 · 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The read/write control signal of the wafer conforms to the fast data bus sampler; #雷1=the output contact pad (10) receives the read/write control signal delayed by the read/write pulse to the flash memory chip, Ϊ = read and write g poor material bus sampler that has been output to the flash memory chips; and H to the second output contact 塾 (PAD2) for feeding into the flash: ^ The material bus sampler is provided to provide the flash memory controller of the data range of the patent, and the circuit comprises a plurality of delayed cells, a complex read and write control signal. Material greenness pulse visibility 3. As in the patent application scope item 2, flash flashing, etc.; 1:3⁄4: write === later logic _ after the result is done separately; 18 1295425 upper middle body wafer In the time specification, Twp f=h疋 is dedicated to the flash memory. 5·1,±1? The flash memory controller of the second item, wherein the control system is provided via the firmware. The flash memory controller of the fifth item of the month f; the upper edge of the JL system refers to the temporary storage of the multiple memory into the flash memory controller by the application program. ^Working area control feed -7 take 2 please / refer to the first item of flash memory controller, but also include feedback input and output contact 塾 (10) 1) back s, Shiyan # patent range 2nd item flash In the memory controller, the upper and lower sample delay chain circuits are composed of a plurality of delayed cells and a plurality of read-and-receive readings; the "delay of taking the interval" and the control signal of the multiplexer Select the flash memory controller in the first item of the patent scope, and the upper Sit back contact pad (10) is - the control with ^ is included to contain the feedback signal to the input buffer. The flash memory controller of the first item, the flash memory chip of the above, comprising a strobe flash memory chip having the same time specification or a different type of flash memory of different time specifications ^ 8 19 1295425 body wafer One. 1i· on the fast flash clock chip '_ memory control read and write pulse Generator; read and write pulse delay chain circuit, because the j time specification should be used to delay the sampling point generated by the read/write gland generator; chain power = write control ί 汇 r sampler pure sample delay _ read Writing a second input/output contact pad (PAD2) for feeding the quick-feeding material bus sampler to provide the data bus bar to 12, for example, please call the flash memory control of the scope of the patent item u, „ The late circuit includes a plurality of delayed cells, ": a multi-turn pulse width 13 as in the patent range 12th flash memory controller, and a plurality of different degrees of pulse width read/write control signals are described. The read/write pulse generated by the read/write pulse generates the read/write (4) money and the result thereof is divided into the ^20 1295425, and the result of the logical mND is respectively performed as the flash memory controller described above, wherein the memory crystal (10) is read by Dedicated to these flashes: see Twp in the dry, and Twh. The above-mentioned multiplexed i month of the 12th flash memory controller, in which the control signal of the second is provided via the firmware. Item 15 of the fast _ memory controller, which is the town The valve number is controlled by the flash memory controller of the 11th patent range, and the 1st crying point delay chain circuit is made up of a plurality of delayed cells and a multi-worker to make a double-short feedback output contact.塾(10)1) Delay in reading time of feedback] Then select the flash memory controller of the 11th patent range of the multiplexer from the control signal of the multiplexer, wherein the output output contact pad (padi) is a control terminal The input contains the feedback signal to the input buffer. The upper ii, _= patent scope 11 (4) memory controller, 1 in the same type 3; ^ flash memory chip 'contains the same day view Fan 21