JP2006145527A - 埋め込み型時間領域反射率試験の方法及び装置 - Google Patents

埋め込み型時間領域反射率試験の方法及び装置 Download PDF

Info

Publication number
JP2006145527A
JP2006145527A JP2005326186A JP2005326186A JP2006145527A JP 2006145527 A JP2006145527 A JP 2006145527A JP 2005326186 A JP2005326186 A JP 2005326186A JP 2005326186 A JP2005326186 A JP 2005326186A JP 2006145527 A JP2006145527 A JP 2006145527A
Authority
JP
Japan
Prior art keywords
signal
data
scan
test
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005326186A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006145527A5 (enExample
Inventor
David L Linam
デイビッド・エル・リナム
Jeffrey R Rearick
ジェフェリー・アール・リーリック
Guy Harlan Humphrey
ガイ・ハーラン・ハンフリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2006145527A publication Critical patent/JP2006145527A/ja
Publication of JP2006145527A5 publication Critical patent/JP2006145527A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/11—Locating faults in cables, transmission lines, or networks using pulse reflection methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2005326186A 2004-11-23 2005-11-10 埋め込み型時間領域反射率試験の方法及び装置 Pending JP2006145527A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/996,113 US7640468B2 (en) 2004-11-23 2004-11-23 Method and apparatus for an embedded time domain reflectometry test

Publications (2)

Publication Number Publication Date
JP2006145527A true JP2006145527A (ja) 2006-06-08
JP2006145527A5 JP2006145527A5 (enExample) 2008-03-27

Family

ID=34654497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005326186A Pending JP2006145527A (ja) 2004-11-23 2005-11-10 埋め込み型時間領域反射率試験の方法及び装置

Country Status (3)

Country Link
US (1) US7640468B2 (enExample)
JP (1) JP2006145527A (enExample)
GB (1) GB2420421A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012189396A (ja) * 2011-03-09 2012-10-04 Mitsubishi Electric Corp Ｉｃチップ、半導体部品、検査用プローブ、ハンディマルチテスター、及び通信装置
JP2020180805A (ja) * 2019-04-23 2020-11-05 ブラザー工業株式会社 入出力基板及び工作機械

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250784B2 (en) 2005-06-29 2007-07-31 Marvell International Ltd. Integrated systems testing
KR100692529B1 (ko) * 2005-07-01 2007-03-09 삼성전자주식회사 최적화된 딜레이 타임 결정 방법, 장치 및 최적화된 딜레이타임 결정 프로그램이 기록된 컴퓨터로 판독 가능한기록매체
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US8024631B1 (en) * 2006-11-07 2011-09-20 Marvell International Ltd. Scan testing system and method
US8117460B2 (en) * 2007-02-14 2012-02-14 Intel Corporation Time-domain reflectometry used to provide biometric authentication
DE102007037377B4 (de) 2007-08-08 2018-08-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Detektion von durch Unterbrechungen charakterisierbare Fehlstellen in Leitbahnnetzwerken
US8829940B2 (en) * 2008-09-26 2014-09-09 Nxp, B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
US9043662B2 (en) * 2009-03-30 2015-05-26 Cadence Design Systems, Inc. Double data rate memory physical interface high speed testing using self checking loopback
US20120081129A1 (en) * 2009-06-03 2012-04-05 Advantest Corporation Test apparatus
US8489947B2 (en) * 2010-02-15 2013-07-16 Mentor Graphics Corporation Circuit and method for simultaneously measuring multiple changes in delay
US9640280B1 (en) * 2015-11-02 2017-05-02 Cadence Design Systems, Inc. Power domain aware insertion methods and designs for testing and repairing memory
US10666540B2 (en) 2017-07-17 2020-05-26 International Business Machines Corporation Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system
US10564219B2 (en) 2017-07-27 2020-02-18 Teradyne, Inc. Time-aligning communication channels
US10890623B1 (en) 2019-09-04 2021-01-12 International Business Machines Corporation Power saving scannable latch output driver
US10897239B1 (en) 2019-09-06 2021-01-19 International Business Machines Corporation Granular variable impedance tuning

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396170A (en) * 1991-04-25 1995-03-07 D'souza; Daniel Single chip IC tester architecture
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US6477674B1 (en) * 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4221435C2 (de) 1992-06-30 1994-05-05 Siemens Ag Elektronischer Baustein mit einer taktgesteuerten Schieberegisterprüfarchitektur (Boundary-Scan)
US6020757A (en) * 1998-03-24 2000-02-01 Xilinx, Inc. Slew rate selection circuit for a programmable device
US6266793B1 (en) * 1999-02-26 2001-07-24 Intel Corporation JTAG boundary scan cell with enhanced testability feature
US6397361B1 (en) * 1999-04-02 2002-05-28 International Business Machines Corporation Reduced-pin integrated circuit I/O test
DE19938060B4 (de) 1999-08-12 2008-06-19 Nokia Siemens Networks Gmbh & Co.Kg Integrierte Schaltung mit einer Testeinrichtung und Verfahren zum Testen der Güte elektrischer Verbindungen der ingegrierten Schaltung
US20020095633A1 (en) 2000-10-05 2002-07-18 Ulf Pillkahn Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board
US6714021B2 (en) 2001-01-11 2004-03-30 Sun Microsystems, Inc. Integrated time domain reflectometry (TDR) tester
US6724210B2 (en) 2001-08-22 2004-04-20 International Business Machines Corporation Method and apparatus for reduced pin count package connection verification
US6862546B2 (en) 2002-02-22 2005-03-01 Intel Corporation Integrated adjustable short-haul/long-haul time domain reflectometry
JP3798713B2 (ja) * 2002-03-11 2006-07-19 株式会社東芝 半導体集積回路装置及びそのテスト方法
US6802046B2 (en) 2002-05-01 2004-10-05 Agilent Technologies, Inc. Time domain measurement systems and methods
US6986087B2 (en) 2002-09-09 2006-01-10 Hewlett-Packard Development Company, L.P. Method and apparatus for improving testability of I/O driver/receivers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396170A (en) * 1991-04-25 1995-03-07 D'souza; Daniel Single chip IC tester architecture
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization
US6477674B1 (en) * 1999-12-29 2002-11-05 Intel Corporation Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012189396A (ja) * 2011-03-09 2012-10-04 Mitsubishi Electric Corp Ｉｃチップ、半導体部品、検査用プローブ、ハンディマルチテスター、及び通信装置
JP2020180805A (ja) * 2019-04-23 2020-11-05 ブラザー工業株式会社 入出力基板及び工作機械
JP7404646B2 (ja) 2019-04-23 2023-12-26 ブラザー工業株式会社 入出力基板及び工作機械

Also Published As

Publication number Publication date
US7640468B2 (en) 2009-12-29
GB0508079D0 (en) 2005-06-01
GB2420421A (en) 2006-05-24
US20060123305A1 (en) 2006-06-08

Similar Documents

Publication Publication Date Title
US7856581B1 (en) Methods and apparatuses for external test methodology and initialization of input-output circuits
US6000051A (en) Method and apparatus for high-speed interconnect testing
CN104321655B (zh) 能够生成用于扫描测试的测试模式控制信号的集成电路
JP2006145527A (ja) 埋め込み型時間領域反射率試験の方法及び装置
US20040267479A1 (en) Automatic self test of an integrated circuit component via AC I/O loopback
JP2004502147A (ja) 高性能回路をテストする方法及び装置
US6880137B1 (en) Dynamically reconfigurable precision signal delay test system for automatic test equipment
US6691269B2 (en) Method for scan controlled sequential sampling of analog signals and circuit for use therewith
US20160349318A1 (en) Dynamic Clock Chain Bypass
CN106680688B (zh) 利用并行扫描测试数据输入和输出测试多核集成电路
JP4701244B2 (ja) マイクロコンピュータ及びそのテスト方法
JP2007178421A (ja) ２相クロック制御によるタイミング競合バウンダリスキャンレジスタを用いないシフトレジスタ
US9021323B1 (en) Test techniques and circuitry
US20090063921A1 (en) Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration
US7080302B2 (en) Semiconductor device and test system therefor
JPH10209376A (ja) 半導体デバイス試験システムおよび方法
US6073261A (en) Circuit for evaluating signal timing
US20030046625A1 (en) Method and apparatus for efficient control of multiple tap controllers
EP1647828A1 (en) Automatic fault-testing of logic blocks using internal at-speed logic-BIST
US20120137187A1 (en) System and method for scan testing integrated circuits
US7689897B2 (en) Method and device for high speed testing of an integrated circuit
US8543876B1 (en) Method and apparatus for serial scan test data delivery
van de Logt et al. An extension to JTAG for at-speed debug on a system
JPH04221781A (ja) 検査方法及び回路
JP2008508541A (ja) 回路相互接続試験の構成とその手法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080212

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101116

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110426