JP2001523369A - 改良されたオペレーティングモード検出機能を備えたフラッシュメモリーカード及びユーザフレンドリなインターフェーシングシステム - Google Patents
改良されたオペレーティングモード検出機能を備えたフラッシュメモリーカード及びユーザフレンドリなインターフェーシングシステムInfo
- Publication number
- JP2001523369A JP2001523369A JP54497199A JP54497199A JP2001523369A JP 2001523369 A JP2001523369 A JP 2001523369A JP 54497199 A JP54497199 A JP 54497199A JP 54497199 A JP54497199 A JP 54497199A JP 2001523369 A JP2001523369 A JP 2001523369A
- Authority
- JP
- Japan
- Prior art keywords
- flash memory
- memory card
- operating mode
- signal
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1. ホストコンピュータシステムに接続され、外部ソースからのコンフィギュ レーション指示を受けることなく複数の選択されたオペレーティングモードでデ ータ保存を行うことができるフラッシュメモリーカードであって、 a. 書込み動作、読出し動作、消去動作を実行するためのフラッシュメモリ モジュールと、 b. フラッシュメモリモジュールに接続され、ホストコンピュータシステム からのアンエンコード信号及びフラッシュメモリーカード内のエンコード信号を 処理し、そのアンエンコード信号とエンコード信号とに応じて、フラッシュメモ リーカードを選択されたオペレーティングモードにコンフィギュレーションする 制御装置と、 c. 限定組の予め決められたコードをホストコンピュータシステムからのプ リエンコードされた信号に適用し、予め決められたコードの各々が唯一のオペレ ーティングモードを識別し、これによりプリエンコードされた信号をエンコード 信号に変換する、前記制御装置に接続されたエンコード手段と、 d. アンエンコード信号とエンコード信号とをモニタする、前記制御装置に 接続された感知手段と、 を備えたフラッシュメモリーカード。 2. 限定組の予め決められたコードが制御装置内にプログラムされている請求 項1記載のフラッシュメモリーカード。 3. エンコード信号は、HA3、HA4、HA5、HA6、HA7、HA8、 HA9、HA10から選択されたATA IDEオペレーティングモード信号ピ ンである請求項1記載のフラッシュメモリーカード。 4. さらに、インターフェース装置に接続するように構成された50ピンコネ クタ端を備えた請求項1記載のフラッシュメモリーカード。 5. さらに、インターフェース装置に接続するように構成された68のピンコ ネクタ端を備えた請求項1記載のフラッシュメモリーカード。 6. 選択されたオペレーティングモードで周辺機器と通信可能なホストコンピ ュータシステムに周辺機器を接続し、該周辺機器が選択されたオペレーティング モードを自動的に検出して該オペレーティングモードを使用できるように該周辺 機器自体をコンフィギュレーションできるようにするインターフェーシングシス テムであって、 a. ホストコンピュータシステムに接続するように構成された第1の端と、 周辺機器に接続するように構成された第2の端とを有し、該第1の端及び第2の 端が選択されたオペレーティングモードでの通信をサポートするインターフェー ス装置と、 b. ホストコンピュータシステムからのアンエンコード信号と周辺機器内の エンコード信号とを処理し、そのアンエンコード信号とエンコード信号に応じて 周辺機器を選択したオペレーティングモードにコンフィギュレーションする、周 辺機器内に組み込まれた制御装置と、 c. 限定組の予め決められたコードをホストコンピュータシステムからのプ リエンコードされた信号に適用し、予め決められたコードの各々が唯一のオペレ ーティングモードを識別し、これによりプリエンコードされた信号をエンコード 信号に変換する、前記制御装置に接続されたエンコード手段と、 d. アンエンコード信号とエンコード信号とをモニタする、前記制御装置に 接続された感知手段と、 を備えたインターフェーシングシステム。 7. 限定組の予め決められたコードが制御装置内にプログラムされている請求 項6記載のインターフェーシングシステム。 8. 周辺機器はフラッシュメモリーカードである請求項6記載のインターフェ ーシングシステム。 9. エンコード信号は、HA3、HA4、HA5、HA6、HA7、HA8、 HA9、HA10から選択されたATA IDEオペレーティングモード信号ピ ンである請求項8記載のインターフェーシングシステム。 10. インターフェース装置の第2の端は50ピン接続が可能な請求項6記載 のインターフェーシングシステム。 11. インターフェース装置の第2の端は68ピン接続が可能な請求項6記載 のインターフェーシングシステム。 12. インターフェース装置はPCMCIAインターフェースとして用いられ る請求項6記載のインターフェーシングシステム。 13. インターフェース装置はATA IDEインターフェースとして用いら れる請求項6記載のインターフェーシングシステム。 14. インターフェース装置はユニバーサルシリアルバスインターフェースと して用いられる請求項6記載のインターフェーシングシステム。 15. a. 周辺機器をホストコンピュータシステムに接続させ、周辺機器と コンピュータシステムの間に通信チャネルを確立するステップと、 b. 周辺機器を起動するステップと、 c. 選択されたオペレーティングモードが識別されるまで、周辺機器内で複 数の信号を逐次分析するステップと、 d. 前記信号に応じて自動的に、周辺機器装置を選択されたオペレーティン グモードにコンフィギュレーションするステップと、 を有する、選択されたオペレーティングモードでホストコンピュータシステム と通信するために周辺機器を自動的にコンフィギュレーションする方法。 16. 信号を逐次分析するステップは、 a. 周辺機器内で、ホストコンピュータからのエンコード信号と、ホストコ ンピュータからのアンエンコード信号とを感知するステップと、 b. ホストコンピュータシステムからのプリエンコードした信号を限定組の 予め決められたコードを用いてエンコードするステップであって、予め決められ たコードは各々唯一のオペレーティングモードを識別し、これにより、プリエン コードされた信号をエンコード信号に変換するステップと、 を有する請求項15記載の方法。 17. さらに、プリエンコードされた信号をエンコードするステップの前に、 周辺機器を予備オペレーティングモードにコンフィギュレーションするステップ を有する請求項16記載の方法。 18. 予備オペレーティングモードはATA IDEモードである請求項17 記載の方法。 19. 周辺機器はフラッシュメモリーカードである請求項15記載の方法。 20. エンコード信号は、HA3、HA4、HA5、HA6、HA7、HA8 、HA9、HA10から選択されたATA IDEオペレーティングモード信号 ピンである請求項19記載の方法。 21. 選択されたオペレーティングモードはPCMCIAモードである請求項 15記載の方法。 22. 選択されたオペレーティングモードはユニバーサルシリアルバスモード である請求項15記載の方法。 23. 選択されたオペレーティングモードはATA IDEモードである請求 項15記載の方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/034,173 US6182162B1 (en) | 1998-03-02 | 1998-03-02 | Externally coupled compact flash memory card that configures itself one of a plurality of appropriate operating protocol modes of a host computer |
US09/034,173 | 1998-03-02 | ||
US09/234,430 | 1999-01-20 | ||
US09/234,430 US6385667B1 (en) | 1998-03-02 | 1999-01-20 | System for configuring a flash memory card with enhanced operating mode detection and user-friendly interfacing system |
PCT/US1999/004633 WO1999045460A2 (en) | 1998-03-02 | 1999-03-02 | Flash memory card with enhanced operating mode detection and user-friendly interfacing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001523369A true JP2001523369A (ja) | 2001-11-20 |
JP3714969B2 JP3714969B2 (ja) | 2005-11-09 |
Family
ID=26710651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54497199A Expired - Lifetime JP3714969B2 (ja) | 1998-03-02 | 1999-03-02 | 改良されたオペレーティングモード検出機能を備えたフラッシュメモリーカード及びユーザフレンドリなインターフェーシングシステム |
Country Status (5)
Country | Link |
---|---|
US (4) | US6721819B2 (ja) |
JP (1) | JP3714969B2 (ja) |
DE (1) | DE19980546B4 (ja) |
GB (1) | GB2339044B (ja) |
WO (1) | WO1999045460A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2009506420A (ja) * | 2005-08-29 | 2009-02-12 | サンディスク アイエル リミテッド | フラッシュメモリコントローラを構成するための装置および方法 |
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Cited By (2)
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JP2009506420A (ja) * | 2005-08-29 | 2009-02-12 | サンディスク アイエル リミテッド | フラッシュメモリコントローラを構成するための装置および方法 |
JP4734413B2 (ja) * | 2005-08-29 | 2011-07-27 | サンディスク アイエル リミテッド | フラッシュメモリコントローラを構成するための装置および方法 |
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DE19980546T1 (de) | 2000-07-06 |
US7111085B2 (en) | 2006-09-19 |
US20040039854A1 (en) | 2004-02-26 |
US7174445B2 (en) | 2007-02-06 |
JP3714969B2 (ja) | 2005-11-09 |
WO1999045460A3 (en) | 1999-10-21 |
DE19980546B4 (de) | 2011-01-27 |
WO1999045460A2 (en) | 1999-09-10 |
US20020040412A1 (en) | 2002-04-04 |
US6721819B2 (en) | 2004-04-13 |
GB9925231D0 (en) | 1999-12-22 |
US20020112101A1 (en) | 2002-08-15 |
GB2339044B (en) | 2003-06-04 |
GB2339044A (en) | 2000-01-12 |
US7421523B2 (en) | 2008-09-02 |
US20060085578A1 (en) | 2006-04-20 |
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