US6041001A - Method of increasing data reliability of a flash memory device without compromising compatibility - Google Patents

Method of increasing data reliability of a flash memory device without compromising compatibility Download PDF

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US6041001A
US6041001A US09/258,163 US25816399A US6041001A US 6041001 A US6041001 A US 6041001A US 25816399 A US25816399 A US 25816399A US 6041001 A US6041001 A US 6041001A
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memory device
data reliability
data
procedure
flash memory
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Petro Estakhri
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Micron Technology Inc
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Lexar Media Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/22Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

A method for increasing the data reliability of a flash memory device without compromising compatibility with existing memory products or an existing memory format makes only minor modifications to the flash memory device. Inside the flash memory device which supports a low power Error Correcting Code known as Hamming Code, the flash memory cells are divided into groups called blocks. Each block is further divided into units called sectors. Each sector is partioned into well defined areas of bits including: SCRATCH DATA, DATA STATUS, and BLOCK STATUS. According to the method, the bits in DATA STATUS and BLOCK STATUS are modified within the specifications of the existing memory format so they can serve as indicators of the increased data reliability capacity of the flash memory device but continue to carry out the function allocated by the existing memory format. Additionally, the SCRATCH DATA is converted into a repository for the data reliability bits for a high power Error Correcting Code (HP ECC). Finally, a newly-designed controller is utilized to perform the Hamming Code or the HP ECC on the data bits being programmed into or read from the flash memory device. The DATA STATUS and the BLOCK STATUS are decoded to determine which ECC to perform on the data bits.

Description

FIELD OF THE INVENTION

The present invention relates to the field of flash memory devices. More particularly, the present invention relates to techniques for improving the data reliability of a flash memory device while retaining compatibility with an existing memory format and existing memory products.

BACKGROUND OF THE INVENTION

A flash memory device is an electrically rewritable nonvolatile digital memory device that does not require a power source to retain its memory contents. A typical flash memory device stores charge on a floating gate to represent a first logic state in the binary state system, while the lack of stored charge represents a second logic state in the binary state system. Additionally, the typical flash memory device is capable of performing a write operation, a read operation, and an erase operation.

Within the flash memory industry, several small form-factor flash memory module standards have evolved to meet the memory demands of portable compact electronic products and to meet the demand for an easily removable compact storage medium. Each of these small form-factor flash memory module standards share the following features: a compact structure and a rugged design. One such standard is the Solid State Floppy Disk Card (SSFDC) standard, a vendor-independent standard crafted by the SSFDC Forum. A flash memory device complying with the SSFDC standard functions with SSFDC products manufactured by any SSFDC vendor. The SSFDC standard has gained wide support and acceptance since its inception because of its simple structure, high portability, and interchangeability. The SSFDC standard has the distinction of being the lightest and thinnest of the currently available flash memory module standards. With a dimension of 45×37×0.76 mm, a SSFDC flash memory device is about half the size and the same thickness as a credit card.

Compared with currently available memory module formats, which use a semiconductor memory assembled on board, the SSFDC standard possesses a much simpler structure. A SSFDC flash memory device has an embedded NAND-type flash memory chip, but does not include a controller or any other substantive support logic circuitry. This simplified design allows the manufacture of a less costly memory device as compared to other types of memory module standards.

The NAND-type structure alludes to the serial arrangement of the memory cells in the SSFDC flash memory. By contrast, the NOR-type structure has the memory cells arranged in parallel. An advantage of the NAND-type structure is faster sequential accessing than the NOR-type structure. In addition, the NAND-type structure supports faster write and erase operations and permits fabrication of higher density memory chips or smaller and less-expensive chips of the same density.

Since the SSFDC flash memory device does not have an integrated controller, the controller can be implemented in numerous embodiments. The controller can be designed directly in a host computer system--as hardware or firmware--, an adapter or as a software-only solution on the host computer system. Resembling a floppy disk drive in which one disk drive functions with numerous floppy disks from a variety of vendors, one SSFDC controller from any SSFDC vendor can be used with any SSFDC flash memory device from a variety of SSFDC vendors.

The SSFDC flash memory device is optimally suited for use in portable devices requiring internal data storage and in low cost consumer products that process data including digital cameras, personal digital assistants, electronic musical instruments, voice recorders faxes, smart cellular phones, pagers, and other portable information-related products. Moreover, the SSFDC flash memory device can be used in equipment requiring removable memory for portability, version upgrades, or memory upgrades for software applications. Besides adding portability to products, the SSFDC flash memory device facilitates the reduction in size of electronic products.

The potential for data corruption in large digital memories poses problems for mission critical computer operations. Since such errors are likely to occur in large digital memories, most modern digital memories incorporate some sort of data reliability procedure to detect and possibly correct errors in the data bits. The SSFDC standard implements a data reliability procedure known as Hamming Code, a type of error correcting code (ECC).

When data bits in a digital memory are moved or stored, there is always a possibility that a mistake can be made, that is, a logic HIGH state interpreted as a logic LOW state or a logic LOW state taken to be a logic HIGH state. This can be caused by media defects, electronic noise, component failures, poor connections, deterioration due to age, environmental perturbations, and other factors. The mistakenly interpreted data bit represents a corrupted data bit--a data bit error. This data bit error could be soft (transient) or hard (permanent). Since this data bit error is a natural consequence of the type of technology employed in digital memory design, the digital memory must compensate for this data bit error by utilizing appropriate logic such as an error correcting code (ECC).

An ECC allows data bits being read or transmitted to be checked for errors and, when necessary, correct the errors "on the fly". It is even possible to detect and restore erased data bits with a particular ECC. The ECC differs from parity-checking in that errors are not only detected but are also corrected--within certain limitations. The power of the ECC is determined by the number and types of errors the ECC is capable of detecting and correcting within the particular data bits being processed by the ECC. A high power ECC can detect and correct many more types of errors and a greater number of errors than a low power ECC. A Hamming Code is an example of a low power ECC, one capable of detecting all single data bit errors and double data bit errors, but correcting only the single data bit errors. A double data bit error indicates two distinct data bits contain errors. The ECC is needed to ensure the accuracy and integrity of data bits as speed and density of digital memories increase--which is usually accompanied by an increase in data bit error rates. In general, the ECC increases the reliability of any computing, telecommunication, and digital memory system without adding much cost. Additionally, the ECC can be integrated within the digital memory device or implemented outside the digital memory device. The fundamental features of the ECC are (1) a module for detecting and correcting errors and (2) extra data bits added by the ECC module to the units of data bits being sent to the digital memory for storage. These extra data bits cannot be utilized by an ECC other than the type of ECC that originally generated the extra data bits.

The ECC can either be implemented in hardware or software. Under most circumstances, errors must be detected and corrected "on the fly", meaning at the same rate as data bits are being read or transmitted. Typically, only a hardware-implemented ECC can provide the performance level for "on the fly" detection and correction at high data transmission rates.

Generally, the ECC performs the error detection and correction on units of data bits. The ECC adds extra data bits to each unit of data bits. These extra data bits are data reliability bits generated by the ECC in response to each unit of data bits. The data reliability bits, when combined with the unit of data bits, form a certain structure. If that structure is altered by errors, the changes can be detected and corrected--within certain limitations.

The basic concept of an ECC can be understood by analogizing with English words. A combination of letters of the English alphabet may or may not form a legitimate English word. The dictionary of the English language provides only the legitimate English words. Errors that occur when transmitting or storing English words can be detected by determining if the received word is in the dictionary. If it is not, errors can be corrected by determining which legitimate English word approximately resembles the received word. The ECC works in a similar fashion.

In practice, when a unit of data bits is stored in the digital memory, data reliability bits that describe the unit of data bits are calculated by the ECC and stored along with the unit of data bits. When the unit of data bits is requested for reading, data reliability bits for the about-to-be read unit of data bits are again calculated by the ECC. She newly generated data reliability bits are compared with the data reliability bits generated when the unit of data bits was stored. If the data reliability bits match, the unit of data bits is considered free of errors and sent to its destination. If the data reliability bits do not match, the missing or erroneous data bits are determined by the ECC and then supplied or corrected.

As mentioned earlier, the SSFDC standard employs an ECC known as Hamming Code. The data reliability bits for the Hamming Code are stored in the SSFDC flash memory device, but the actual Hamming Code module, which performs the error detection and correction, resides outside the SSFDC flash memory device--usually in the SSFDC controller. The Hamming Code cannot be changed to a different ECC by the vendor/manufacturer since the SSFDC standard is a vendor-independent standard for which a variety of SSFDC products have been designed. These SSFDC products are configured to operate only with the data reliability bits for the Hamming Code--not just any ECC--since the data reliability bits are meaningful only to the Hamming Code.

Inside the SSFDC flash memory device, the flash memory cells are divided into groups called blocks. Each block is further divided into units called sectors. The SSFDC standard requires each sector to be defined as denoted in FIG. 1. Each sector 100 must be a length of five hundred twenty-eight bytes. The five hundred twenty-eight bytes are parcelled as follows: five hundred twelve bytes to USER DATA 10, four bytes to SCRATCH DATA 20, one byte to DATA STATUS 30, one byte to BLOCK STATUS 40, two bytes to BLOCK ADDRESS 50, three bytes to ECC1 60, two bytes to BLOCK ADDRESS 70, and three bytes to ECC2 80.

USER DATA 10 is further divided into two hundred fifty-six bytes for USER DATA1 12 and two hundred fifty-six bytes for USER DATA2 14. Data bits sent to the SSFDC flash memory device for storage are stored in USER DATA1 12 and USER DATA2 14.

SCRATCH DATA 20 can be utilized by the vendor/manufacturer tor storing bits of vendor-specific information. Without SCRATCH DATA 20, the SSFDC flash memory device could still function properly as a storage device.

DATA STATUS 30 holds bits of information concerning the operability of USER DATA 10. The SSFDC standard specifies several possible patterns of bits within DATA STATUS 30 that are appropriate for indicating specific conditions of USER DATA 10. Under normal operating conditions, DATA STATUS 30 is set to FFh.

BLOCK STATUS 40 holds bits of information concerning the operability of the block of which the sector 100 is a part. The SSFDC standard specifies several possible patterns of bits within BLOCK STATUS 40 that are appropriate for indicating specific conditions of the block of which the sector 100 is a part. The specific conditions include: defective block and good block. Under normal operating conditions, BLOCK STATUS 40 is set to FFh.

BLOCK ADDRESS 50 holds bits indicating the block address of USER DATA 10.

ECC1 60 stores the data reliability bits which the Hamming Code needs in order to perform error detection and correction on the data bits in USER DATA1 12. These data reliability bits would be useless to an ECC other than the Hamming Code.

BLOCK ADDRESS 70 holds bits indicating the block address of USER DATA 10.

ECC2 80 stores the data reliability bits which the Hamming Code needs in order to perform error detection and correction on the data bits in USER DATA2 14. These data reliability bits would be useless to an ECC other than the Hamming Code.

For an illustration of how the Hamming Code interacts with the SSFDC flash memory device refer to FIG. 2 and FIG. 3. Focusing on FIG. 2, a unit of data bits 210 to be programmed into the SSFDC flash memory device 200 is first processed by the Hamming Code 250. From the Hamming Code 250, the unit of data bits 230 is sent to the SSFDC flash memory device 200 for storing. The data reliability bits 220 generated by the Hamming Code for the unit of data bits 210 is stored with the unit of data bits 230.

Focusing on FIG. 3, a unit of data bits 310 read from the SSFDC flash memory device 300 is first processed by the Hamming Code 350. The data reliability bits 320 previously generated by the Hamming Code 350 are also transmitted to the Hamming Code 350. Within the Hamming Code 350, the unit of data bits 310 is checked for errors and corrected if any errors are detected--refer to the earlier discussion of the ECC for an explanation of how the ECC, such as the Hamming Code, accomplishes the error detection and correction. From the Hamming Code 350, the unit of data bits 360--now checked and corrected--proceeds to its destination.

FIG. 2 and FIG. 3 are merely intended to illustrate a particular implementation of the Hamming Code with the SSFDC flash memory device, but are not intended to limit the scope of the discussion to this particular implementation.

As discussed above, the Hamming Code is a low power ECC. This limits the SSFDC flash memory device to applications not requiring an extreme level of data reliability. In addition, the SSFDC flash memory device is currently unsuited to handled the higher error rates of future flash memory cell technologies such as multi-bit flash memory cells. Even if the ECC on the SSFDC controller was changed to a high power ECC by the vendor, the potential market for such a product would be stymied by the lack of compatibility with the existing SSFDC controllers and products designed with the Hamming Code. The reason for this outcome lies in the interdependence between the ECC and the data reliability bits. Since each type of ECC generates vastly different data reliability bits, one type of ECC could not utilize the data reliability bits from a different type of ECC. Thus, the existing SSFDC controller would be unable to function properly with the modified SSFDC flash memory device, which is configured to operate with a high power ECC, while the modified SSFDC controller, which is configured to operate with a high power ECC, would be unable to function properly with the existing SSFDC flash memory device, thus undermining the objective of having multiple SSFDC vendors designing SSFDC controllers and products that are compatible with the SSFDC controllers and products of other SSFDC vendors.

In sum, there is no SSFDC flash memory device with a high power ECC that is compatible with existing standards.

SUMMARY OF THE INVENTION

The present invention is a method of increasing data reliability of a flash memory device without compromising compatibility with existing memory products or an existing memory format. The flash memory device used in a way that is modified by the present invention adheres to the Solid State Floppy Disk Card (SSFDC) standard while continuing to function properly with existing SSFDC products. Simply stated, the increased data reliability is achieved by incorporating a high power Error Correcting Code (ECC) into a newly-designed SSFDC controller while retaining the conventional Hamming Code. A SCRATCH DATA within each sector of the SSFDC flash memory device is designated as the location for data reliability information for the high power ECC, thus avoiding conflict with the SSFDC standard. Furthermore, bits in a DATA STATUS and in a BLOCK STATUS of each sector are modified such that the SSFDC standard is not abandoned or altered beyond permissible limits. This modification of the bits in the DATA STATUS and in the BLOCK STATUS permits the DATA STATUS and the BLOCK STATUS to continue carrying out the function assigned to them by the SSFDC standard, as well as indicate whether the SCRATCH DATA contains the data reliability information for the high power ECC.

As a result, data reliability is improved because error detection and correction is performed by the high power ECC rather than the Hamming Code, which is a low power ECC. Any type of ECC can be utilized as the high power ECC.

Compatibility is maintained due to retention of the Hamming Code for use with existing SSFDC controllers operating with only the Hamming Code. By decoding bits in the DATA STATUS and the BLOCK STATUS, the newly-designed SSFDC controller, operating with the high power ECC and the low power Hamming Code, determines which ECC to perform on the data bits to be programmed into or read from the SSFDC flash memory device. Most importantly, the newly-designed SSFDC controller both generates data reliability bits for the Hamming Code and stores them in the SSFDC flash memory device whenever the newly-designed SSFDC controller generates and stores data reliability bits for the high power ECC. Similarly, the SSFDC flash memory device, which has been changed by storing the data reliability bits for the high power ECC in the SCRATCH DATA and by altering the bits of the DATA STATUS and the BLOCK STATUS, functions faultlessly when interacting with existing SSFDC controllers and products because the SSFDC flash memory device stores the data reliability bits for both the high power ECC and the Hamming Code.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the data storage format of a sector within the SSFDC flash memory device according to the prior art.

FIG. 2 illustrates the data reliability procedure during the program/write mode of the SSFDC flash memory device according to the prior art.

FIG. 3 illustrates the data reliability procedure during the read mode of the SSFDC flash memory device according to the prior art.

FIG. 4 illustrates the data storage format of a sector within the SSFDC flash memory device according to the present invention.

FIG. 5 illustrates the data reliability procedure during the program/write mode of the SSFDC flash memory device according to the present invention when the SSFDC flash memory device is formatted according to the present invention.

FIG. 6 illustrates the data reliability procedure during the read mode of the SSFDC flash memory device according to the present invention when the SSFDC flash memory device is formatted according to the present invention.

FIG. 7 illustrates the data reliability procedure during the program/write mode of the SSFDC flash memory device according to the present invention when the SSFDC flash memory device is formatted according to the prior art.

FIG. 8 illustrates the data reliability procedure during the read mode of the SSFDC flash memory device according to the present invention when the SSFDC flash memory device is formatted according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The method of the present invention increases the data reliability of a flash memory device without compromising compatibility with existing memory products and an existing memory format. Handling data reliability of a flash memory device requires addressing the errors in data bits caused by the corruption of the data bits through any of the sources of corruption discussed earlier. The use of multi-bit flash memory cells for expanding the capacity of the typical flash memory device degrades the data reliability of the flash memory device considerably. Although the flash memory device can be designed to minimize the sources of corruption, a more efficient and economical approach lies in confronting the errors in the data bits, once the errors have occurred, with a data reliability procedure. Achieving compatibility with existing products and an existing memory format entails incorporating essential features of existing processes into the new processes.

Incorporating high data reliability without the expense and inconvenience of incompatibility stimulates rapid market acceptance of the flash memory device and expands the range of possible applications for the flash memory device. A high power Error Correcting Code (HP ECC) is a data reliability procedure which provides increased data reliability capability. The integration of the high power ECC (HP ECC) into the operation of the flash memory device without losing compatibility is the crucial problem solved by the present invention.

By working within the parameters of a memory standard for the flash memory device, compatibility is not lost, but improved data reliability is achieved in a system configured to take advantage of this invention. Since the memory standard defines relevant operating conditions, data storage format, and data reliability procedure, but allows for variation to a limited extent, the present invention takes advantage of this permissible variation in the parameters of the memory standard. In particular, certain bits within the flash memory device that hold information about the internal operation of the flash memory device are altered--only to an extent not departing from the memory standard--so that the bits can serve multiple purposes. While continuing to hold internal operational information, the newly-altered bits also passively communicate the existence of the increased data reliability capability of the flash memory device. Additionally, specific bits within the flash memory device are designated--without conflicting with the memory standard--as repositories of the increased data reliability capability. Most importantly, data bits being programmed into or read from the flash memory device undergo a data reliability procedure, either a high level or a low level, communicated by the newly-altered bits. Capability to perform the high level and the low level data reliability procedures is required in order to maintain compatibility with the memory standard. Before initiating the data reliability procedure, the newly-altered bits are decoded to determine which particular data reliability procedure to perform on the data bits being programmed into or read from the flash memory device.

Although the preferred embodiment of the present invention will be disclosed with reference to a flash memory device configured to a Solid State Floppy Disk Card (SSFDC) standard, the present invention is applicable to other types of memory devices known to those skilled in the art, as well as to flash memory devices configured according to a variety of other memory standards known to those skilled in the art.

Reference will be made to a high power ECC (HP ECC). The HP ECC can be implemented as any type of ECC known to those skilled in the art. Additionally, a type of data reliability procedure different from an ECC can be substituted for the HP ECC. Preferably, the present invention is implemented to improve the data reliability of the SSFDC flash memory device. Alternatively, the present invention can be implemented to add other features to the data reliability of the SSFDC flash memory device.

As discussed earlier, flash memory cells within a SSFDC flash memory device are divided into groups called blocks. Each block is further divided into units called sectors. The sectors observe a data storage format dictated by the SSFDC standard.

Referring to FIG. 4, the data storage format of a sector 400 within the SSFDC flash memory device is shown after being modified by the method of increasing data reliability without compromising compatibility. USER DATA1 412. USER DATA2 414, BLOCK ADDRESS 450, ECC1 460, BLOCK ADDRESS 470, and ECC2 480 remain unchanged when compared to FIG. 1. The description of each of these areas can be found above. The same function and limits are applicable. However, changes to the sector 400 can be best illustrated by referencing both FIG. 1 and FIG. 4.

The SCRATCH DATA 20 (FIG. 1) has been redesignated as a NEW ECC 420 (FIG. 4). Data bits within the NEW ECC 420 serve as repositories of data reliability bits for the high power Error Correcting Code (HP ECC). This change does not interfere with the SSFDC standard because the SCRATCH DATA 20 was originally utilized for storing only SSFDC vendor-specific information rather than critical operational information. Additionally, the NEW ECC 420 is sufficiently large to hold the data reliability bits for the HP ECC for all data bits in the entire USER DATA 410, unlike the prior art where USER DATA 10 was divided into USER DATA1 12 and USER DATA2 14 and the data reliability bits for the data bits were stored in ECC1 60 and ECC2 80.

The DATA STATUS 30 (FIG. 1) has been reassigned as a DATA STATUS & ECC DESIGNATION 430 (FIG. 4). Besides holding bits of information concerning the operability of the USER DATA 410, the bits in the DATA STATUS & ECC DESIGNATION 430 indicate whether the SCRATCH DATA 20 has been transformed into the NEW ECC 420 for use with the HP ECC. Because the SSFDC standard specifies several possible patterns of bits within the DATA STATUS 30 that are appropriate for indicating specific conditions of the USER DATA 10, the normal operating condition setting of the DATA STATUS & EEC DESIGNATION 430 is different from that of the DATA STATUS 30. Rather than being FFh under normal operating conditions, the DATA STATUS & ECC DESIGNATION 430 is set to any other setting which meets the following guidelines: (1) the setting does not conflict with the SSFDC standard and (2) the setting is not been utilized for any operating purpose by the SSFDC standard. For example, the SSFDC standard mandates that a specific number of bits with logic LOW values would indicate a particular operating condition of the USER DATA 410. Hence, the normal operating condition setting is formulated not to have the specific number of bits with logic LOW values to avoid unexpectedly triggering that particular operating condition.

The BLOCK STATUS 40 (FIG. 1) has been reassigned as a BLOCK STATUS & ECC DESIGNATION 440 (FIG. 4). Besides holding bits of information concerning the operability of the block of which the sector 400 is a part of, the bits in the BLOCK STATUS & ECC DESIGNATION 440 indicate whether the SCRATCH DATA 20 has been transformed into the NEW ECC 420 for use with the HP ECC. Because the SSFDC standard specifies several possible patterns of bits within the BLOCK STATUS 40 that are appropriate for indicating specific conditions of the block of which the sector 400 is a part of, the normal operating condition setting of the BLOCK STATUS & ECC DESIGNATION 440 is different from that of the BLOCK STATUS 40. Rather than being FFh under normal operating conditions, the BLOCK STATUS & ECC DESIGNATION 440 is set to any other setting which meets the following guidelines: (1) the setting does not conflict with the SSFDC standard and (2) the setting is not been utilized for any operating purpose by the SSFDC standard. For example, the SSFDC standard mandates that a specific number of bits with logic LOW values would indicate a particular operating condition of the block of which the sector 400 is a part. Hence, the normal operating condition setting is formulated not to have the specific number of bits with logic LOW values to avoid unexpectedly triggering that particular operating condition.

Preferably, the method of increasing data reliability of the SSFDC flash memory device without compromising compatibility is implemented in conjunction with a newly-designed SSFDC controller. Alternatively, the steps of the method can be implemented using other devices, circuits, or software known to those skilled in the art.

The newly-designed SSFDC controller (SSFDC controller) is capable of performing several data reliability procedures on bits being read from or programmed into the SSFDC flash memory device. The SSFDC controller preferably includes (1) means for decoding data bits in the BLOCK STATUS & ECC DESIGNATION and in the DATA STATUS & ECC DESIGNATION and (2) means for performing the data reliability procedures, such as the high power ECC and the Hamming Code.

The means for decoding can be implemented as a decoding circuitry, decoding software, or any equivalent implementation. As discussed above, under normal operating conditions, the bits in the BLOCK STATUS & ECC DESIGNATION and in the DATA STATUS & ECC DESIGNATION are set to particular settings that also indicate the presence of data reliability bits for the high power ECC in the NEW ECC. Thus, by decoding these particular settings, the means for performing the data reliability procedures can be configured to perform either the high power ECC or the Hamming Code on the data bits being programmed into or read from the SSFDC flash memory device.

The means for performing the data reliability procedures is coupled to the means for decoding. In addition, the means for performing the data reliability procedures can be implemented as logic circuitry, software, or any equivalent implementation. The means for performing the data reliability procedures includes means for generating the data reliability bits for the high power ECC, means for generating the data reliability bits for the Hamming Code, and means for assigning the data reliability bits for the high power ECC to the NEW ECC and the data reliability bits for the Hamming Code to the ECC1 and the ECC2. Each means for generating accomplishes the task of generating data reliability bits which are used as described previously. Both means for generating and the means for assigning can be implemented as logic circuitry, software, or any equivalent implementation.

Before performing the data reliability procedure on the data bits being programmed into or read from the SSFDC flash memory device, the means for performing needs information from the means for decoding concerning the data reliability procedure that should be performed. Depending on the information received from the decoding means, the means for performing performs either the high power ECC or the Hamming Code. More importantly, the means for performing generates the data reliability bits for the Hamming Code and assigns them to either the ECC1 or the ECC2 in the SSFDC flash memory device whenever the means for performing generates and assigns data reliability bits for the high power ECC to the NEW ECC in the flash memory device.

Preferably, the method of increasing data reliability of the SSFDC flash memory device without compromising compatibility modifies the bits of the DATA STATUS and the BLOCK STATUS. This modification transforms the DATA STATUS into the DATA STATUS & ECC DESIGNATION and transforms the BLOCK STATUS into the BLOCK STATUS & ECC DESIGNATION. Preferably, this modification is implemented by changing a source responsible for maintaining the settings of the bits stored in the DATA STATUS and in the BLOCK STATUS. The source can reside in the newly-designed SSFDC controller or can reside in any appropriate location apparent to those skilled in the art. Finally, the data reliability procedure is preferably implemented by the newly-designed SSFDC controller or implemented by any appropriate circuit or software apparent to those skilled in the art.

FIG. 5 and FIG. 6 illustrate the increased data reliability of the SSFDC flash memory device provided by the present invention.

FIG. 5 illustrates the interaction between the SSFDC flash memory device 500 formatted according to the present invention and a data reliability procedure module of the newly-designed SSFDC controller during the program/write mode of the SSFDC flash memory device 500. A unit of data bits 510 to be programmed into the SSFDC flash memory device 500 is first processed by the data reliability procedure module, Hamming Code & HP ECC 550. From the Hamming Code & HP ECC 550, the unit of data bits 520 is sent to the SSFDC flash memory device 500 for storing. Since the decoding of the DATA STATUS & ECC DESIGNATION (not shown) and BLOCK STATUS & ECC DESIGNATION (not shown) indicates support for the HP ECC for the unit of data bits 510 the Hamming Code & HP ECC 550 generates the data reliability bits (HP) 530 for the HP ECC code and the data reliability bits (HC) 540 for the Hamming Code and stores them with the unit of data bits 520 in the NEW ECC (not shown) and in ECC1(not shown) or ECC2(not shown), respectively--as described previously.

FIG. 6 illustrates the interaction between the SSFDC flash memory device 600 formatted according to the present invention and the data reliability procedure module of the newly-designed SSFDC controller during the read mode of the SSFDC flash memory device 600. Focusing on FIG. 6, a unit of data bits 610 read from the SSFDC flash memory device 600 is first processed by the data reliability procedure module Hamming Code & HP ECC 650. Since the decoding of the DATA STATUS & ECC DESIGNATION (not shown) and BLOCK STATUS & ECC DESIGNATION (not shown) indicates support for the HP ECC, the data reliability bits (HP) 620 previously generated by the Hamming Code & HP ECC 550 (FIG. 5) are also transmitted to the Hamming Code & HP ECC 650. Within the Hamming Code & HP ECC 650, the unit of data bits 610 is checked by HP ECC for errors and corrected if any errors are detected--refer to the earlier description of the ECC for an explanation of how the ECC accomplishes the error detection and correction. From the Hamming Code & HP ECC 650, the unit of data bits 660--now checked and corrected--proceeds to its destination in a host computer system or other location. Since the HP ECC within the Hamming Code & HP ECC 650 performed a high level of error detection and correction, the unit of data bits 660 possesses a higher level of integrity and accuracy for use in a variety of critical operations or noncritical operations.

FIG. 7 and FIG. 8 illustrate the compatibility of the method for increasing the data reliability of the SSFDC flash memory device with existing SSFDC flash memory devices and an existing memory format, as provided by the present invention.

FIG. 7 illustrates the interaction between the SSFDC flash memory device 700 formatted according to the prior art and the data reliability procedure module of the newly-designed SSFDC controller during the program/write mode of the SSFDC flash memory device 700. A unit of data bits 710 to be programmed into the SSFDC flash memory device 700 is first processed by the data reliability procedure module, Hamming Code & HP ECC 750. From the Hamming Code & HP ECC 750, the unit of data bits 720 is sent to the SSFDC flash memory device 700 for storing. Since the decoding of the DATA STATUS (not shown) and BLOCK STATUS (not shown) fails to indicate support for the HP ECC, for the unit of data bits 710 the Hamming Code & HP ECC 750 generates only the data reliability bits (HC) 730 for the Hamming Code and stores them with the unit of data bits 720 in the ECC1(not shown) or ECC2(not shown)--as described previously.

FIG. 8 illustrates the interaction between the SSFDC flash memory device 800 formatted according to the prior art and the data reliability procedure module of the newly-designed SSFDC controller during the read mode of the SSFDC flash memory device 800. Focusing on FIG. 8, a unit of data bits 810 read from the SSFDC flash memory device 800 is first processed by the data reliability procedure module, Hamming Code & HP ECC 850. Since the decoding of the DATA STATUS (not shown) and BLOCK STATUS (not shown) fails to indicate support for the HP ECC, this time the data reliability bits (HC) 820 for the Hamming Code previously generated by the Hamming Code & HP ECC 750 (FIG. 7) are also transmitted to the Hamming Code & HP ECC 850. Within the Hamming Code & HP ECC 850, the unit of data bits 810 is checked by the Hamming Code for errors and corrected if any errors are detected--refer to the earlier description of the ECC for an explanation of how the ECC accomplishes the error detection and correction. From the Hamming Code & HP ECC 850, the unit of data bits 860--now checked and corrected--proceeds to its destination in a host computer system or other location.

When a flash memory device, which is formatted according to the present invention, interacts with an existing SSFDC controller, the process proceeds similarly as described in FIG. 2 and FIG. 3, thus satisfying the goal of increasing data reliability without compromising compatibility.

The above figures are merely intended to illustrate a particular implementation of the present invention, but are not intended to limit the scope of the present invention to this particular implementation.

Although potentially all the bits in the DATA STATUS and in the BLOCK STATUS can be modified by the present invention, modifying fewer than all the bits or modifying other bits in other locations would not depart from the scope and spirit of the present invention. Additionally, the location for the data reliability bits for the HP ECC can be changed to a different location without departing from the scope or spirit of the present invention.

The present invention has been described in terms of specific embodiments incorporating details to facilitate the understanding of the principles of construction and operation of the invention. Such reference herein to specific embodiments and details thereof is not intended to limit the scope of the claims appended hereto. It will be apparent to those skilled in the art that modifications may be made in the embodiments chosen for illustration without departing from the spirit and scope of the invention.

Claims (41)

I claim:
1. A method of increasing data reliability of a memory device without compromising compatibility, the method comprising steps of:
a. modifying a predetermined bit located in a predetermined location within the memory device;
b. decoding the predetermined bit, the predetermined bit holding a data reliability procedure code; and
c. performing a data reliability procedure corresponding to the data reliability procedure code on a data bit.
2. The method according to claim 1 wherein the memory device is a flash memory device.
3. The method according to claim 2 wherein the flash memory device is configured as a Solid State Floppy Disk Card forum flash memory device.
4. The method according to claim 1 wherein the data reliability procedure is an error correcting code procedure.
5. The method according to claim 1 wherein the data reliability procedure code is designed such that the predetermined bit can continue carrying out a previously assigned function.
6. The method according to claim 1 wherein the data reliability procedure code is equivalent to a normal operational state of the predetermined bit.
7. The method according to claim 1 wherein the step of performing the data reliability procedure includes steps of generating a data reliability bit associated with the data reliability procedure being performed and storing the data reliability bit in the predetermined location in the memory device.
8. The method according to claim 7 wherein the predetermined location is a SCRATCH DATA designated location within the memory device.
9. The method according to claim 7 wherein the predetermined location is an ECC1 designated location within the memory device.
10. The method according to claim 7 wherein the predetermined location is an ECC2 designated location within the memory device.
11. The method according to claim 7 wherein the predetermined location is chosen such that the predetermined location can continue carrying out a previously allocated function.
12. The method according to claim 1 wherein the step of performing the data reliability procedure includes steps of generating a first data reliability bit associated with a first data reliability procedure when a second data reliability procedure is performed and storing the first data reliability bit in a first predetermined location in the memory device.
13. The method according to claim 12 wherein the first predetermined location is an ECC1 designated location within the memory device.
14. The method according to claim 12 wherein the first predetermined location is an ECC2 designated location within the memory device.
15. The method according to claim 1 wherein the predetermined location is a DATA STATUS designated location within the memory device.
16. The method according to claim 1 wherein the predetermined location is a BLOCK STATUS designated location within the memory device.
17. A controller for increasing the data reliability of a memory device without compromising compatibility, the controller comprising:
a. means for decoding a predetermined bit located in a predetermined location within the memory device, the predetermined bit holding a data reliability procedure code; and
b. means for performing a data reliability procedure corresponding to the data reliability procedure code on a data bit, the means for performing the data reliability procedure being coupled to the means for decoding the predetermined bit.
18. The controller according to claim 17 wherein the memory device is a flash memory device.
19. The controller according to claim 18 wherein the flash memory device is configured as a Solid State Floppy Disk Card forum flash memory device.
20. The controller according to claim 17 wherein the data reliability procedure is an error correcting code procedure.
21. The controller according to claim 17 wherein the data reliability procedure code is designed such that the predetermined bit can continue carrying out a previously assigned function.
22. The controller according to claim 17 wherein the data reliability procedure code is equivalent to a normal operational state of the predetermined bit.
23. The controller according to claim 17 wherein the means for performing the data reliability procedure includes means for generating a data reliability bit associated with the data reliability procedure being performed and means for assigning the data reliability bit to the predetermined location in the memory device.
24. The controller according to claim 23 wherein the predetermined location is a SCRATCH DATA designated location within the memory device.
25. The controller according to claim 23 wherein the predetermined location is an ECC1 designated location within the memory device.
26. The controller according to claim 23 wherein the predetermined location is an ECC2 designated location within the memory device.
27. The controller according to claim 23 wherein the predetermined location is chosen such that the predetermined location can continue carrying out a previously allocated function.
28. The controller according to claim 17 wherein the means for performing the data reliability procedure includes means for generating a first data reliability bit associated with a first data reliability procedure when a second data reliability procedure is performed and means for assigning the first data reliability bit to a first predetermined location in the memory device.
29. The controller according to claim 28 wherein the first predetermined location is an ECC1 designated location within the memory device.
30. The controller according to claim 28 wherein the first predetermined location is an ECC2 designated location within the memory device.
31. The controller according to claim 17 wherein the predetermined location is a DATA STATUS designated location within the memory device.
32. The controller according to claim 17 wherein the predetermined location is a BLOCK STATUS designated location within the memory device.
33. A memory system achieving increased data reliability without compromising compatibility, the memory system comprising:
a. a memory device; and
b. a controller coupled to the memory device, the controller having:
i. means for decoding a predetermined bit located in a predetermined location within the memory device, the predetermined bit holding a data reliability procedure code; and
ii. means for performing a data reliability procedure corresponding to the data reliability procedure code on a data bit, the means for performing the data reliability procedure being coupled to the means tor decoding the predetermined bit.
34. The memory system according to claim 33 wherein the memory device is a flash memory device.
35. The memory system according to claim 34 wherein the flash memory device is configured as a Solid State Floppy Disk Card forum flash memory device.
36. The memory system according to claim 33 wherein the data reliability procedure is an error correcting code procedure.
37. The memory system according to claim 33 wherein the data reliability procedure code is designed such that the predetermined bit can continue carrying out a previously assigned function.
38. The memory system according to claim 33 wherein the data reliability procedure code is equivalent to a normal operational state of the predetermined bit.
39. The memory system according to claim 33 wherein the means for performing the data reliability procedure includes means for generating a data reliability bit associated with the data reliability procedure being performed and means for assigning the data reliability bit to the predetermined location in the memory device.
40. The memory system according to claim 39 wherein the predetermined location is chosen such that the predetermined location can continue carrying out a previously allocated function.
41. The memory system according to claim 33 wherein the means for performing the data reliability procedure includes means for generating a first data reliability bit associated with a first data reliability procedure when a second data reliability procedure is performed and means for assigning the first data reliability bit to a first predetermined location in the memory device.
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Cited By (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6426893B1 (en) 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20020112101A1 (en) * 1998-03-02 2002-08-15 Petro Estakhri Flash memory card with enhanced operating mode detection and user-friendly interfacing system
WO2002086719A2 (en) 2001-04-24 2002-10-31 Koninklijke Philips Electronics N.V. Improved error correction scheme for use in flash memory allowing bit alterability
US20030070036A1 (en) * 2001-09-28 2003-04-10 Gorobets Sergey Anatolievich Memory system for data storage and retrieval
US20030126481A1 (en) * 2001-09-28 2003-07-03 Payne Robert Edwin Power management system
US20030126451A1 (en) * 2001-09-28 2003-07-03 Gorobets Sergey Anatolievich Data processing
US20030161199A1 (en) * 2002-02-22 2003-08-28 Petro Estakhri Removable memory media with integral indicator light
US20030165076A1 (en) * 2001-09-28 2003-09-04 Gorobets Sergey Anatolievich Method of writing data to non-volatile memory
US20040083333A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Hybrid implementation for error correction codes within a non-volatile memory system
US20040083334A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Method and apparatus for managing the integrity of data in non-volatile memory system
US6772274B1 (en) 2000-09-13 2004-08-03 Lexar Media, Inc. Flash memory system and method implementing LBA to PBA correlation within flash memory array
US20040199714A1 (en) * 1995-07-31 2004-10-07 Petro Estakhri Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US20040225825A1 (en) * 2003-05-08 2004-11-11 Micron Technology, Inc. Scratch control memory array in a flash memory device
US20050055497A1 (en) * 1995-07-31 2005-03-10 Petro Estakhri Faster write operations to nonvolatile memory by manipulation of frequently-accessed sectors
US20050099867A1 (en) * 2002-02-20 2005-05-12 Cedric Groux Method for storing data blocks in a memory
US6901457B1 (en) 1998-11-04 2005-05-31 Sandisk Corporation Multiple mode communications system
US20050249010A1 (en) * 2004-05-06 2005-11-10 Klein Dean A Memory controller method and system compensating for memory cell data losses
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US20050271377A1 (en) * 2004-06-04 2005-12-08 Seong-Jun Hong Apparatus for processing multimedia data in portable device having NAND flash memory and method thereof
US20050289444A1 (en) * 2004-06-25 2005-12-29 Klein Dean A Low power cost-effective ECC memory system and method
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US20060013052A1 (en) * 2004-07-15 2006-01-19 Klein Dean A Method and system for controlling refresh to avoid memory cell data losses
US20060059405A1 (en) * 2004-09-10 2006-03-16 Parkinson Ward D Using a phase change memory as a high volume memory
US20060072157A1 (en) * 2004-09-24 2006-04-06 Hodder Leonard B Method of correcting NAND memory blocks and to a printing device employing the method
US20060140012A1 (en) * 2004-12-29 2006-06-29 Jun Wan Word line compensation in non-volatile memory erase operations
US20060221660A1 (en) * 2005-03-31 2006-10-05 Hemink Gerrit J Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US7155559B1 (en) * 2000-08-25 2006-12-26 Lexar Media, Inc. Flash memory architecture with separate storage of overhead and user data
US20070089034A1 (en) * 2005-10-13 2007-04-19 M-Systems Flash Disk Pioneers, Ltd. Method of error correction in MBC flash memory
US20070168837A1 (en) * 2006-01-18 2007-07-19 M-Systems Flash Disk Pioneers Ltd. Method for implementing error-correction codes in flash memory
US20070195894A1 (en) * 2006-02-21 2007-08-23 Digital Fountain, Inc. Multiple-field based code generator and decoder for communications systems
US20070258297A1 (en) * 2006-05-08 2007-11-08 Macronix International Co., Ltd. Method and Apparatus for Accessing Nonvolatile Memory With Read Error by Changing Read Reference
US20070283224A1 (en) * 2006-05-16 2007-12-06 Pitney Bowes Incorporated System and method for efficient uncorrectable error detection in flash memory
US20070283214A1 (en) * 2006-05-10 2007-12-06 M-Systems Flash Disk Pioneers, Ltd. Corruption-resistant data porting with multiple error correction schemes
US20070300127A1 (en) * 2006-05-10 2007-12-27 Digital Fountain, Inc. Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient users of the communications systems
US20080013360A1 (en) * 2005-03-31 2008-01-17 Hemink Gerrit J Erase Voltage Manipulation in Non-Volatile Memory for Controlled Shifts in Threshold Voltage
US20080019164A1 (en) * 2005-03-31 2008-01-24 Hemink Gerrit J Systems for Erase Voltage Manipulation in Non-Volatile Memory for Controlled Shifts in Threshold Voltage
US20080089133A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Systems for partitioned soft programming in non-volatile memory
US20080089135A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Systems for partitioned erase and erase verification in non-volatile memory
US20080092016A1 (en) * 2006-10-11 2008-04-17 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US20080089132A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Partitioned soft programming in non-volatile memory
US20080089134A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Partitioned erase and erase verification in non-volatile memory
WO2008051385A2 (en) * 2006-10-19 2008-05-02 Hewlett-Packard Development Company, L.P. Data allocation in memory chips
US20080109705A1 (en) * 2006-10-18 2008-05-08 Pawlowski J Thomas Memory system and method using ECC with flag bit to identify modified data
WO2008068706A1 (en) 2006-12-07 2008-06-12 Nxp B.V. Method and device for reconfiguration of reliability data in flash eeprom storage pages
US20080158959A1 (en) * 2006-12-29 2008-07-03 Nima Mokhlesi Page by page ecc variation in a memory device
US20080163028A1 (en) * 2006-12-29 2008-07-03 Nima Mokhlesi Page by page ecc variation in a memory device
US20080168319A1 (en) * 2007-01-08 2008-07-10 Samsung Electronics Co., Ltd. Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems
US20080205229A1 (en) * 2007-02-26 2008-08-28 Yung-Chih Li Method of identifying optical disc
US20080244368A1 (en) * 2007-03-31 2008-10-02 Henry Chin Guided Simulated Annealing in Non-Volatile Memory Error Correction Control
US20080244367A1 (en) * 2007-03-31 2008-10-02 Henry Chin Non-volatile memory with guided simulated annealing error correction control
US20080244360A1 (en) * 2007-03-31 2008-10-02 Nima Mokhlesi Non-Volatile Memory with Soft Bit Data Transmission for Error Correction Control
US20080244338A1 (en) * 2007-03-31 2008-10-02 Nima Mokhlesi Soft bit data transmission for error correction control in non-volatile memory
US20080250300A1 (en) * 2007-03-29 2008-10-09 Nima Mokhlesi Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US20080256418A1 (en) * 2006-06-09 2008-10-16 Digital Fountain, Inc Dynamic stream interleaving and sub-stream based delivery
US20080320175A1 (en) * 1998-03-02 2008-12-25 Lexar Media, Inc. Methods and apparatus for identifying operating modes for peripheral devices
US20090031199A1 (en) * 2004-05-07 2009-01-29 Digital Fountain, Inc. File download and streaming system
US20090043952A1 (en) * 1995-07-31 2009-02-12 Lexar Media, Inc. Moving sectors within a block of information in a flash memory mass storage architecture
US20090067551A1 (en) * 2007-09-12 2009-03-12 Digital Fountain, Inc. Generating and communicating source identification information to enable reliable communications
US20090077434A1 (en) * 2004-08-27 2009-03-19 Lexar Media, Inc. Status of overall health of nonvolatile memory
US20090172335A1 (en) * 2007-12-31 2009-07-02 Anand Krishnamurthi Kulkarni Flash devices with raid
US7559004B1 (en) 2003-10-01 2009-07-07 Sandisk Corporation Dynamic redundant area configuration in a non-volatile memory system
US20090189792A1 (en) * 2002-10-05 2009-07-30 Shokrollahi M Amin Systematic encoding and decoding of chain reaction codes
US20090201731A1 (en) * 2006-05-08 2009-08-13 Macronix International Co., Ltd. Method and Apparatus for Accessing Memory With Read Error By Changing Comparison
US20090204750A1 (en) * 1995-07-31 2009-08-13 Petro Estakhri Direct logical block addressing flash memory mass storage architecture
US20100125765A1 (en) * 2008-11-20 2010-05-20 Yair Orbach Uninitialized memory detection using error correction codes and built-in self test
US7734862B2 (en) 2000-07-21 2010-06-08 Lexar Media, Inc. Block management for mass storage
US20100211690A1 (en) * 2009-02-13 2010-08-19 Digital Fountain, Inc. Block partitioning for a data stream
US20100223530A1 (en) * 2009-02-27 2010-09-02 Samsung Electronics Co., Ltd. Semiconductor memory device and data processing method thereof
US20100223533A1 (en) * 2009-02-27 2010-09-02 Qualcomm Incorporated Mobile reception of digital video broadcasting-terrestrial services
US20110019769A1 (en) * 2001-12-21 2011-01-27 Qualcomm Incorporated Multi stage code generator and decoder for communication systems
US20110060962A1 (en) * 2006-05-08 2011-03-10 Macronix International Co., Ltd. Method and Apparatus for Accessing Memory With Read Error By Changing Comparison
US20110096828A1 (en) * 2009-09-22 2011-04-28 Qualcomm Incorporated Enhanced block-request streaming using scalable encoding
US20110103519A1 (en) * 2002-06-11 2011-05-05 Qualcomm Incorporated Systems and processes for decoding chain reaction codes through inactivation
US20110231519A1 (en) * 2006-06-09 2011-09-22 Qualcomm Incorporated Enhanced block-request streaming using url templates and construction rules
US20110238789A1 (en) * 2006-06-09 2011-09-29 Qualcomm Incorporated Enhanced block-request streaming system using signaling or block creation
US20110239078A1 (en) * 2006-06-09 2011-09-29 Qualcomm Incorporated Enhanced block-request streaming using cooperative parallel http and forward error correction
US20120233523A1 (en) * 2011-03-10 2012-09-13 Icform, Inc Programmable Data Storage Management
US8337252B2 (en) 2000-07-06 2012-12-25 Mcm Portfolio Llc Smartconnect flash card adapter
US20130019142A1 (en) * 2011-07-12 2013-01-17 Phison Electronics Corp. Memory storage device, memory controller thereof, and method for programming data thereof
US8806050B2 (en) 2010-08-10 2014-08-12 Qualcomm Incorporated Manifest file updates for network streaming of coded multimedia data
US8887020B2 (en) 2003-10-06 2014-11-11 Digital Fountain, Inc. Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters
US8910017B2 (en) 2012-07-02 2014-12-09 Sandisk Technologies Inc. Flash memory with random partition
US8958375B2 (en) 2011-02-11 2015-02-17 Qualcomm Incorporated Framing for an improved radio link protocol including FEC
US9136983B2 (en) 2006-02-13 2015-09-15 Digital Fountain, Inc. Streaming and buffering using variable FEC overhead and protection periods
US9135112B2 (en) * 2012-12-11 2015-09-15 Seagate Technology Llc Policy for read operations addressing on-the-fly decoding failure in non-volatile memory
US9246633B2 (en) 1998-09-23 2016-01-26 Digital Fountain, Inc. Information additive code generator and decoder for communication systems
US9253233B2 (en) 2011-08-31 2016-02-02 Qualcomm Incorporated Switch signaling methods providing improved switching between representations for adaptive HTTP streaming
US9270299B2 (en) 2011-02-11 2016-02-23 Qualcomm Incorporated Encoding and decoding using elastic codes with flexible source block mapping
US9288010B2 (en) 2009-08-19 2016-03-15 Qualcomm Incorporated Universal file delivery methods for providing unequal error protection and bundled file delivery services
US9294226B2 (en) 2012-03-26 2016-03-22 Qualcomm Incorporated Universal object delivery and template-based file delivery
US9380096B2 (en) 2006-06-09 2016-06-28 Qualcomm Incorporated Enhanced block-request streaming system for handling low-latency streaming
US9419749B2 (en) 2009-08-19 2016-08-16 Qualcomm Incorporated Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
US9558135B2 (en) 2000-07-06 2017-01-31 Larry Lawson Jones Flashcard reader and converter for reading serial and parallel flashcards
FR3039922A1 (en) * 2015-08-06 2017-02-10 Stmicroelectronics (Rousset) Sas A method of writing in a memory of the EEPROM type memory device and corresponding
US9602802B2 (en) 2010-07-21 2017-03-21 Qualcomm Incorporated Providing frame packing type information for video coding
US9843844B2 (en) 2011-10-05 2017-12-12 Qualcomm Incorporated Network streaming of media data
US9917874B2 (en) 2009-09-22 2018-03-13 Qualcomm Incorporated Enhanced block-request streaming using block partitioning or request controls for improved client-side handling
US10116336B2 (en) 2014-06-13 2018-10-30 Sandisk Technologies Llc Error correcting code adjustment for a data storage device
US10304550B1 (en) 2017-11-29 2019-05-28 Sandisk Technologies Llc Sense amplifier with negative threshold sensing for non-volatile memory

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233610A (en) * 1989-08-30 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having error correcting function
US5459742A (en) * 1992-06-11 1995-10-17 Quantum Corporation Solid state disk memory using storage devices with defects
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5740188A (en) * 1996-05-29 1998-04-14 Compaq Computer Corporation Error checking and correcting for burst DRAM devices
US5754753A (en) * 1992-06-11 1998-05-19 Digital Equipment Corporation Multiple-bit error correction in computer main memory
US5832005A (en) * 1997-12-11 1998-11-03 International Business Machines Corporation Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like
US5922080A (en) * 1996-05-29 1999-07-13 Compaq Computer Corporation, Inc. Method and apparatus for performing error detection and correction with memory devices
US5958079A (en) * 1997-01-08 1999-09-28 Mitsubishi Denki Kabushiki Kaisha Memory card with error correction scheme requiring reducing memory capacity

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233610A (en) * 1989-08-30 1993-08-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having error correcting function
US5459742A (en) * 1992-06-11 1995-10-17 Quantum Corporation Solid state disk memory using storage devices with defects
US5754753A (en) * 1992-06-11 1998-05-19 Digital Equipment Corporation Multiple-bit error correction in computer main memory
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
US5740188A (en) * 1996-05-29 1998-04-14 Compaq Computer Corporation Error checking and correcting for burst DRAM devices
US5922080A (en) * 1996-05-29 1999-07-13 Compaq Computer Corporation, Inc. Method and apparatus for performing error detection and correction with memory devices
US5958079A (en) * 1997-01-08 1999-09-28 Mitsubishi Denki Kabushiki Kaisha Memory card with error correction scheme requiring reducing memory capacity
US5832005A (en) * 1997-12-11 1998-11-03 International Business Machines Corporation Fault-tolerant method and means for managing access to an initial program load stored in read-only memory or the like

Cited By (299)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8554985B2 (en) 1995-07-31 2013-10-08 Micron Technology, Inc. Memory block identified by group of logical block addresses, storage device with movable sectors, and methods
US7774576B2 (en) 1995-07-31 2010-08-10 Lexar Media, Inc. Direct logical block addressing flash memory mass storage architecture
US20040199714A1 (en) * 1995-07-31 2004-10-07 Petro Estakhri Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US7908426B2 (en) 1995-07-31 2011-03-15 Lexar Media, Inc. Moving sectors within a block of information in a flash memory mass storage architecture
US20060155923A1 (en) * 1995-07-31 2006-07-13 Petro Estakhri Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US20090043952A1 (en) * 1995-07-31 2009-02-12 Lexar Media, Inc. Moving sectors within a block of information in a flash memory mass storage architecture
US8171203B2 (en) 1995-07-31 2012-05-01 Micron Technology, Inc. Faster write operations to nonvolatile memory using FSInfo sector manipulation
US8032694B2 (en) 1995-07-31 2011-10-04 Micron Technology, Inc. Direct logical block addressing flash memory mass storage architecture
US20090204750A1 (en) * 1995-07-31 2009-08-13 Petro Estakhri Direct logical block addressing flash memory mass storage architecture
US8793430B2 (en) 1995-07-31 2014-07-29 Micron Technology, Inc. Electronic system having memory with a physical block having a sector storing data and indicating a move status of another sector of the physical block
US20050055497A1 (en) * 1995-07-31 2005-03-10 Petro Estakhri Faster write operations to nonvolatile memory by manipulation of frequently-accessed sectors
US20080320175A1 (en) * 1998-03-02 2008-12-25 Lexar Media, Inc. Methods and apparatus for identifying operating modes for peripheral devices
US7111085B2 (en) 1998-03-02 2006-09-19 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US8291128B2 (en) 1998-03-02 2012-10-16 Micron Technology, Inc. Systems configured to identify an operating mode
US7174445B2 (en) 1998-03-02 2007-02-06 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US20100228890A1 (en) * 1998-03-02 2010-09-09 Lexar Media, Inc. Memory devices configured to identify an operating mode
US20060085578A1 (en) * 1998-03-02 2006-04-20 Petro Hatakhri Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US6721819B2 (en) 1998-03-02 2004-04-13 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US7721017B2 (en) 1998-03-02 2010-05-18 Lexar Media, Inc. Methods and apparatus for identifying operating modes for peripheral devices
US8073986B2 (en) 1998-03-02 2011-12-06 Micron Technology, Inc. Memory devices configured to identify an operating mode
US20020112101A1 (en) * 1998-03-02 2002-08-15 Petro Estakhri Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US20040039854A1 (en) * 1998-03-02 2004-02-26 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US7421523B2 (en) 1998-03-02 2008-09-02 Lexar Media, Inc. Flash memory card with enhanced operating mode detection and user-friendly interfacing system
US9246633B2 (en) 1998-09-23 2016-01-26 Digital Fountain, Inc. Information additive code generator and decoder for communication systems
US6901457B1 (en) 1998-11-04 2005-05-31 Sandisk Corporation Multiple mode communications system
US6426893B1 (en) 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6760255B2 (en) 2000-02-17 2004-07-06 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7889590B2 (en) 2000-02-17 2011-02-15 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20090175082A1 (en) * 2000-02-17 2009-07-09 Conley Kevin M Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks
US7362613B2 (en) 2000-02-17 2008-04-22 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6996008B2 (en) 2000-02-17 2006-02-07 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20090175080A1 (en) * 2000-02-17 2009-07-09 Conley Kevin M Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks
US8797798B2 (en) 2000-02-17 2014-08-05 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7646667B2 (en) 2000-02-17 2010-01-12 Sandisk Corporation Flash EEprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20100049910A1 (en) * 2000-02-17 2010-02-25 Conley Kevin M Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks
US7184306B2 (en) 2000-02-17 2007-02-27 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6580638B2 (en) 2000-02-17 2003-06-17 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US8503240B2 (en) 2000-02-17 2013-08-06 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US8223547B2 (en) 2000-02-17 2012-07-17 Sandisk Corporation Flash EEprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US20060109712A1 (en) * 2000-02-17 2006-05-25 Conley Kevin M Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7646666B2 (en) 2000-02-17 2010-01-12 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US7889554B2 (en) 2000-02-17 2011-02-15 Sandisk Corporation Flash EEPROM system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US8337252B2 (en) 2000-07-06 2012-12-25 Mcm Portfolio Llc Smartconnect flash card adapter
US9558135B2 (en) 2000-07-06 2017-01-31 Larry Lawson Jones Flashcard reader and converter for reading serial and parallel flashcards
US8019932B2 (en) 2000-07-21 2011-09-13 Micron Technology, Inc. Block management for mass storage
US8250294B2 (en) 2000-07-21 2012-08-21 Micron Technology, Inc. Block management for mass storage
US7734862B2 (en) 2000-07-21 2010-06-08 Lexar Media, Inc. Block management for mass storage
US20090259807A1 (en) * 2000-08-25 2009-10-15 Micron Technology, Inc. Flash memory architecture with separate storage of overhead and user data
US8595421B2 (en) 2000-08-25 2013-11-26 Petro Estakhri Flash memory architecture with separate storage of overhead and user data
US7155559B1 (en) * 2000-08-25 2006-12-26 Lexar Media, Inc. Flash memory architecture with separate storage of overhead and user data
US9384127B2 (en) 2000-08-25 2016-07-05 Micron Technology, Inc. Flash memory architecture with separate storage of overhead and user data
US10078449B2 (en) 2000-08-25 2018-09-18 Micron Technology, Inc. Flash memory architecture with separate storage of overhead and user data
US8161229B2 (en) 2000-08-25 2012-04-17 Micron Technology, Inc. Flash memory architecture with separate storage of overhead and user data
US6772274B1 (en) 2000-09-13 2004-08-03 Lexar Media, Inc. Flash memory system and method implementing LBA to PBA correlation within flash memory array
WO2002086719A2 (en) 2001-04-24 2002-10-31 Koninklijke Philips Electronics N.V. Improved error correction scheme for use in flash memory allowing bit alterability
US20030046631A1 (en) * 2001-04-24 2003-03-06 Steffen Gappisch Error correction scheme for use in flash memory allowing bit alterability
WO2002086719A3 (en) * 2001-04-24 2004-01-15 Koninkl Philips Electronics Nv Improved error correction scheme for use in flash memory allowing bit alterability
US8135925B2 (en) 2001-09-28 2012-03-13 Micron Technology, Inc. Methods of operating a memory system
US20080155184A1 (en) * 2001-09-28 2008-06-26 Lexar Media, Inc. Methods and apparatus for writing data to non-volatile memory
US7681057B2 (en) 2001-09-28 2010-03-16 Lexar Media, Inc. Power management of non-volatile memory systems
US20080215903A1 (en) * 2001-09-28 2008-09-04 Lexar Media, Inc. Power management of non-volatile memory systems
US8386695B2 (en) 2001-09-28 2013-02-26 Micron Technology, Inc. Methods and apparatus for writing data to non-volatile memory
US7917709B2 (en) 2001-09-28 2011-03-29 Lexar Media, Inc. Memory system for data storage and retrieval
US20030165076A1 (en) * 2001-09-28 2003-09-04 Gorobets Sergey Anatolievich Method of writing data to non-volatile memory
US20030126451A1 (en) * 2001-09-28 2003-07-03 Gorobets Sergey Anatolievich Data processing
US20030126481A1 (en) * 2001-09-28 2003-07-03 Payne Robert Edwin Power management system
US20030070036A1 (en) * 2001-09-28 2003-04-10 Gorobets Sergey Anatolievich Memory system for data storage and retrieval
US9032134B2 (en) 2001-09-28 2015-05-12 Micron Technology, Inc. Methods of operating a memory system that include outputting a data pattern from a sector allocation table to a host if a logical sector is indicated as being erased
US8694722B2 (en) 2001-09-28 2014-04-08 Micron Technology, Inc. Memory systems
US9489301B2 (en) 2001-09-28 2016-11-08 Micron Technology, Inc. Memory systems
US7634624B2 (en) 2001-09-28 2009-12-15 Micron Technology, Inc. Memory system for data storage and retrieval
US20110019769A1 (en) * 2001-12-21 2011-01-27 Qualcomm Incorporated Multi stage code generator and decoder for communication systems
US9236976B2 (en) 2001-12-21 2016-01-12 Digital Fountain, Inc. Multi stage code generator and decoder for communication systems
US7206250B2 (en) * 2002-02-20 2007-04-17 Nagracard S.A. Method for storing data blocks in a memory
US20050099867A1 (en) * 2002-02-20 2005-05-12 Cedric Groux Method for storing data blocks in a memory
US7535370B2 (en) 2002-02-22 2009-05-19 Lexar Media, Inc. Removable memory media with integral indicator light
US7277011B2 (en) 2002-02-22 2007-10-02 Micron Technology, Inc. Removable memory media with integral indicator light
US20080143542A1 (en) * 2002-02-22 2008-06-19 Lexar Media, Inc. Removable memory media with integral indicator light
US20030161199A1 (en) * 2002-02-22 2003-08-28 Petro Estakhri Removable memory media with integral indicator light
US20110103519A1 (en) * 2002-06-11 2011-05-05 Qualcomm Incorporated Systems and processes for decoding chain reaction codes through inactivation
US9240810B2 (en) 2002-06-11 2016-01-19 Digital Fountain, Inc. Systems and processes for decoding chain reaction codes through inactivation
USRE43741E1 (en) 2002-10-05 2012-10-16 Qualcomm Incorporated Systematic encoding and decoding of chain reaction codes
US20090189792A1 (en) * 2002-10-05 2009-07-30 Shokrollahi M Amin Systematic encoding and decoding of chain reaction codes
US9236885B2 (en) 2002-10-05 2016-01-12 Digital Fountain, Inc. Systematic encoding and decoding of chain reaction codes
CN1499532B (en) 2002-10-28 2011-05-18 三因迪斯克公司 Hybrid realization of error correcting code in non-volatile memory
US20040083333A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Hybrid implementation for error correction codes within a non-volatile memory system
EP1424631A1 (en) * 2002-10-28 2004-06-02 SanDisk Corporation Hybrid implementation for error correction codes within a non-volatile memory system
KR101017443B1 (en) 2002-10-28 2011-02-25 샌디스크 코포레이션 Hybrid implementation for error correction codes within a non-volatile memory system
EP1416380A2 (en) * 2002-10-28 2004-05-06 SanDisk Corporation Method and apparatus for managing the integrity of data in a non-volatile memory system
EP1416380A3 (en) * 2002-10-28 2006-04-26 SanDisk Corporation Method and apparatus for managing the integrity of data in a non-volatile memory system
US20040083334A1 (en) * 2002-10-28 2004-04-29 Sandisk Corporation Method and apparatus for managing the integrity of data in non-volatile memory system
US8412879B2 (en) * 2002-10-28 2013-04-02 Sandisk Technologies Inc. Hybrid implementation for error correction codes within a non-volatile memory system
US20070113002A1 (en) * 2003-05-08 2007-05-17 Micron Technology, Inc. Scratch control memory array in a flash memory device
US7069377B2 (en) 2003-05-08 2006-06-27 Micron Technology, Inc. Scratch control memory array in a flash memory device
US7277981B2 (en) 2003-05-08 2007-10-02 Micron Technology, Inc. Scratch control memory array in a flash memory device
US20040225825A1 (en) * 2003-05-08 2004-11-11 Micron Technology, Inc. Scratch control memory array in a flash memory device
US7181566B2 (en) 2003-05-08 2007-02-20 Micron Technology, Inc. Scratch control memory array in a flash memory device
US20060184725A1 (en) * 2003-05-08 2006-08-17 Micron Technology, Inc.; Scratch control memory array in a flash memory device
US7559004B1 (en) 2003-10-01 2009-07-07 Sandisk Corporation Dynamic redundant area configuration in a non-volatile memory system
US8887020B2 (en) 2003-10-06 2014-11-11 Digital Fountain, Inc. Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters
US7447973B2 (en) 2004-05-06 2008-11-04 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20050249010A1 (en) * 2004-05-06 2005-11-10 Klein Dean A Memory controller method and system compensating for memory cell data losses
US20060056259A1 (en) * 2004-05-06 2006-03-16 Klein Dean A Memory controller method and system compensating for memory cell data losses
US7428687B2 (en) 2004-05-06 2008-09-23 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060056260A1 (en) * 2004-05-06 2006-03-16 Klein Dean A Memory controller method and system compensating for memory cell data losses
US20060069856A1 (en) * 2004-05-06 2006-03-30 Klein Dean A Memory controller method and system compensating for memory cell data losses
US8689077B2 (en) 2004-05-06 2014-04-01 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7099221B2 (en) 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20090024884A1 (en) * 2004-05-06 2009-01-22 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US9064600B2 (en) 2004-05-06 2015-06-23 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7836374B2 (en) 2004-05-06 2010-11-16 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US7447974B2 (en) 2004-05-06 2008-11-04 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20090031199A1 (en) * 2004-05-07 2009-01-29 Digital Fountain, Inc. File download and streaming system
US9136878B2 (en) 2004-05-07 2015-09-15 Digital Fountain, Inc. File download and streaming system
US9236887B2 (en) 2004-05-07 2016-01-12 Digital Fountain, Inc. File download and streaming system
US20050271377A1 (en) * 2004-06-04 2005-12-08 Seong-Jun Hong Apparatus for processing multimedia data in portable device having NAND flash memory and method thereof
US7461320B2 (en) 2004-06-24 2008-12-02 Micron Technology, Inc. Memory system and method having selective ECC during low power refresh
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US20060206769A1 (en) * 2004-06-24 2006-09-14 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US20050289444A1 (en) * 2004-06-25 2005-12-29 Klein Dean A Low power cost-effective ECC memory system and method
US20060218469A1 (en) * 2004-06-25 2006-09-28 Klein Dean A Low power cost-effective ECC memory system and method
US7526713B2 (en) 2004-06-25 2009-04-28 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7272066B2 (en) 2004-07-15 2007-09-18 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US20060158950A1 (en) * 2004-07-15 2006-07-20 Klein Dean A Method and system for controlling refresh to avoid memory cell data losses
US7898892B2 (en) 2004-07-15 2011-03-01 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US20060152989A1 (en) * 2004-07-15 2006-07-13 Klein Dean A Method and system for controlling refresh to avoid memory cell data losses
US7280386B2 (en) 2004-07-15 2007-10-09 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7558142B2 (en) 2004-07-15 2009-07-07 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US20060013052A1 (en) * 2004-07-15 2006-01-19 Klein Dean A Method and system for controlling refresh to avoid memory cell data losses
US8279683B2 (en) 2004-07-15 2012-10-02 Micron Technology, Inc. Digit line comparison circuits
US20080002503A1 (en) * 2004-07-15 2008-01-03 Klein Dean A Method and system for controlling refresh to avoid memory cell data losses
US7277345B2 (en) 2004-07-15 2007-10-02 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7116602B2 (en) 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US7623392B2 (en) 2004-07-15 2009-11-24 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US8446783B2 (en) 2004-07-15 2013-05-21 Micron Technology, Inc. Digit line comparison circuits
US20090077434A1 (en) * 2004-08-27 2009-03-19 Lexar Media, Inc. Status of overall health of nonvolatile memory
US20100231408A1 (en) * 2004-08-27 2010-09-16 Lexar Media, Inc. Display configured to display health status of a memory device
US7743290B2 (en) 2004-08-27 2010-06-22 Lexar Media, Inc. Status of overall health of nonvolatile memory
US7184352B2 (en) 2004-08-31 2007-02-27 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US6965537B1 (en) 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
US20060044913A1 (en) * 2004-08-31 2006-03-02 Klein Dean A Memory system and method using ECC to achieve low power refresh
US8566674B2 (en) * 2004-09-10 2013-10-22 Ovonyx, Inc. Using a phase change memory as a high volume memory
US7590918B2 (en) * 2004-09-10 2009-09-15 Ovonyx, Inc. Using a phase change memory as a high volume memory
US20090300467A1 (en) * 2004-09-10 2009-12-03 Parkinson Ward D Using a Phase Change Memory as a High Volume Memory
US20060059405A1 (en) * 2004-09-10 2006-03-16 Parkinson Ward D Using a phase change memory as a high volume memory
US20060072157A1 (en) * 2004-09-24 2006-04-06 Hodder Leonard B Method of correcting NAND memory blocks and to a printing device employing the method
US7509526B2 (en) 2004-09-24 2009-03-24 Seiko Epson Corporation Method of correcting NAND memory blocks and to a printing device employing the method
US7606074B2 (en) 2004-12-29 2009-10-20 Sandisk Corporation Word line compensation in non-volatile memory erase operations
US20090021983A1 (en) * 2004-12-29 2009-01-22 Sandisk Corporation Word Line Compensation In Non-Volatile Memory Erase Operations
US20060140012A1 (en) * 2004-12-29 2006-06-29 Jun Wan Word line compensation in non-volatile memory erase operations
US7450433B2 (en) * 2004-12-29 2008-11-11 Sandisk Corporation Word line compensation in non-volatile memory erase operations
US20060221660A1 (en) * 2005-03-31 2006-10-05 Hemink Gerrit J Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US20060221705A1 (en) * 2005-03-31 2006-10-05 Hemink Gerrit J Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US20060221703A1 (en) * 2005-03-31 2006-10-05 Masaaki Higashitani Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells
US7400537B2 (en) 2005-03-31 2008-07-15 Sandisk Corporation Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US7403428B2 (en) 2005-03-31 2008-07-22 Sandisk Corporation Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells
US20060221708A1 (en) * 2005-03-31 2006-10-05 Masaaki Higashitani Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells
US7606100B2 (en) 2005-03-31 2009-10-20 Sandisk Corporation Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US7403424B2 (en) 2005-03-31 2008-07-22 Sandisk Corporation Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US20060221709A1 (en) * 2005-03-31 2006-10-05 Hemink Gerrit J Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells
US7408804B2 (en) 2005-03-31 2008-08-05 Sandisk Corporation Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US20060221661A1 (en) * 2005-03-31 2006-10-05 Hemink Gerrit J Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US7430138B2 (en) 2005-03-31 2008-09-30 Sandisk Corporation Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells
US7486564B2 (en) 2005-03-31 2009-02-03 Sandisk Corporation Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US7457166B2 (en) 2005-03-31 2008-11-25 Sandisk Corporation Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
US20080013360A1 (en) * 2005-03-31 2008-01-17 Hemink Gerrit J Erase Voltage Manipulation in Non-Volatile Memory for Controlled Shifts in Threshold Voltage
US20080019164A1 (en) * 2005-03-31 2008-01-24 Hemink Gerrit J Systems for Erase Voltage Manipulation in Non-Volatile Memory for Controlled Shifts in Threshold Voltage
US7522457B2 (en) 2005-03-31 2009-04-21 Sandisk Corporation Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage
US20070089034A1 (en) * 2005-10-13 2007-04-19 M-Systems Flash Disk Pioneers, Ltd. Method of error correction in MBC flash memory
US7681109B2 (en) * 2005-10-13 2010-03-16 Ramot At Tel Aviv University Ltd. Method of error correction in MBC flash memory
US20090070657A1 (en) * 2005-10-13 2009-03-12 Ramot At Tel Aviv University Ltd. Method of error correction in mbc flash memory
US8261157B2 (en) 2005-10-13 2012-09-04 Ramot et Tel Aviv University Ltd. Method of error correction in MBC flash memory
US7783955B2 (en) * 2006-01-18 2010-08-24 Sandisk Il Ltd. Method for implementing error-correction codes in flash memory
US7992071B2 (en) 2006-01-18 2011-08-02 Sandisk Il Ltd. Method for implementing error-correction codes in non-volatile memory
US20070168837A1 (en) * 2006-01-18 2007-07-19 M-Systems Flash Disk Pioneers Ltd. Method for implementing error-correction codes in flash memory
US20100257428A1 (en) * 2006-01-18 2010-10-07 Mark Murin Method for implementing error-correction codes in non-volatile memory
US9136983B2 (en) 2006-02-13 2015-09-15 Digital Fountain, Inc. Streaming and buffering using variable FEC overhead and protection periods
US9270414B2 (en) 2006-02-21 2016-02-23 Digital Fountain, Inc. Multiple-field based code generator and decoder for communications systems
US20070195894A1 (en) * 2006-02-21 2007-08-23 Digital Fountain, Inc. Multiple-field based code generator and decoder for communications systems
US7471562B2 (en) 2006-05-08 2008-12-30 Macronix International Co., Ltd. Method and apparatus for accessing nonvolatile memory with read error by changing read reference
US20090201731A1 (en) * 2006-05-08 2009-08-13 Macronix International Co., Ltd. Method and Apparatus for Accessing Memory With Read Error By Changing Comparison
US7773421B2 (en) 2006-05-08 2010-08-10 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
US20110060962A1 (en) * 2006-05-08 2011-03-10 Macronix International Co., Ltd. Method and Apparatus for Accessing Memory With Read Error By Changing Comparison
US8077516B2 (en) 2006-05-08 2011-12-13 Macronix International Co., Ltd. Method and apparatus for accessing memory with read error by changing comparison
US20070258297A1 (en) * 2006-05-08 2007-11-08 Macronix International Co., Ltd. Method and Apparatus for Accessing Nonvolatile Memory With Read Error by Changing Read Reference
US7823043B2 (en) * 2006-05-10 2010-10-26 Sandisk Il Ltd. Corruption-resistant data porting with multiple error correction schemes
US9264069B2 (en) 2006-05-10 2016-02-16 Digital Fountain, Inc. Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient uses of the communications systems
US20070300127A1 (en) * 2006-05-10 2007-12-27 Digital Fountain, Inc. Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient users of the communications systems
US20070283214A1 (en) * 2006-05-10 2007-12-06 M-Systems Flash Disk Pioneers, Ltd. Corruption-resistant data porting with multiple error correction schemes
US7971129B2 (en) * 2006-05-10 2011-06-28 Digital Fountain, Inc. Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient users of the communications systems
US20100205509A1 (en) * 2006-05-16 2010-08-12 Pitney Bowes Inc. Systems and methods for efficient uncorrectable error detection in flash memory
US20070283224A1 (en) * 2006-05-16 2007-12-06 Pitney Bowes Incorporated System and method for efficient uncorrectable error detection in flash memory
US7707481B2 (en) 2006-05-16 2010-04-27 Pitney Bowes Inc. System and method for efficient uncorrectable error detection in flash memory
US8010873B2 (en) 2006-05-16 2011-08-30 Pitney Bowes Inc. Systems and methods for efficient uncorrectable error detection in flash memory
US9432433B2 (en) 2006-06-09 2016-08-30 Qualcomm Incorporated Enhanced block-request streaming system using signaling or block creation
US9380096B2 (en) 2006-06-09 2016-06-28 Qualcomm Incorporated Enhanced block-request streaming system for handling low-latency streaming
US9178535B2 (en) 2006-06-09 2015-11-03 Digital Fountain, Inc. Dynamic stream interleaving and sub-stream based delivery
US20080256418A1 (en) * 2006-06-09 2008-10-16 Digital Fountain, Inc Dynamic stream interleaving and sub-stream based delivery
US20110239078A1 (en) * 2006-06-09 2011-09-29 Qualcomm Incorporated Enhanced block-request streaming using cooperative parallel http and forward error correction
US9209934B2 (en) 2006-06-09 2015-12-08 Qualcomm Incorporated Enhanced block-request streaming using cooperative parallel HTTP and forward error correction
US9191151B2 (en) 2006-06-09 2015-11-17 Qualcomm Incorporated Enhanced block-request streaming using cooperative parallel HTTP and forward error correction
US20110231519A1 (en) * 2006-06-09 2011-09-22 Qualcomm Incorporated Enhanced block-request streaming using url templates and construction rules
US9386064B2 (en) 2006-06-09 2016-07-05 Qualcomm Incorporated Enhanced block-request streaming using URL templates and construction rules
US20110238789A1 (en) * 2006-06-09 2011-09-29 Qualcomm Incorporated Enhanced block-request streaming system using signaling or block creation
US9286161B2 (en) 2006-10-11 2016-03-15 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US8359517B2 (en) 2006-10-11 2013-01-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US20080092016A1 (en) * 2006-10-11 2008-04-17 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US20110138251A1 (en) * 2006-10-11 2011-06-09 Pawlowski J Thomas Memory system and method using partial ecc to achieve low power refresh and fast access to data
US8832522B2 (en) 2006-10-11 2014-09-09 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7768826B2 (en) 2006-10-13 2010-08-03 Sandisk Corporation Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects
US20080089133A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Systems for partitioned soft programming in non-volatile memory
US7499317B2 (en) 2006-10-13 2009-03-03 Sandisk Corporation System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling
US7535766B2 (en) 2006-10-13 2009-05-19 Sandisk Corporation Systems for partitioned soft programming in non-volatile memory
US7499338B2 (en) 2006-10-13 2009-03-03 Sandisk Corporation Partitioned soft programming in non-volatile memory
US20080089134A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Partitioned erase and erase verification in non-volatile memory
US20080089135A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Systems for partitioned erase and erase verification in non-volatile memory
US7495954B2 (en) 2006-10-13 2009-02-24 Sandisk Corporation Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory
US20080089132A1 (en) * 2006-10-13 2008-04-17 Fumitoshi Ito Partitioned soft programming in non-volatile memory
US20090180325A1 (en) * 2006-10-13 2009-07-16 Sandisk Corporation Partitioned Erase And Erase Verification In Non-Volatile Memory
US8413007B2 (en) 2006-10-18 2013-04-02 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US8601341B2 (en) 2006-10-18 2013-12-03 Micron Technologies, Inc. Memory system and method using ECC with flag bit to identify modified data
US8880974B2 (en) 2006-10-18 2014-11-04 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US20080109705A1 (en) * 2006-10-18 2008-05-08 Pawlowski J Thomas Memory system and method using ECC with flag bit to identify modified data
US20080109704A1 (en) * 2006-10-19 2008-05-08 Jeffrey Christenson Data allocation in memory chips
US7856588B2 (en) 2006-10-19 2010-12-21 Hewlett-Packard Development Company, L.P. Data allocation in memory chips
WO2008051385A3 (en) * 2006-10-19 2008-07-17 Hewlett Packard Development Co Data allocation in memory chips
WO2008051385A2 (en) * 2006-10-19 2008-05-02 Hewlett-Packard Development Company, L.P. Data allocation in memory chips
CN101558452B (en) 2006-12-07 2012-08-29 Nxp股份有限公司 Method and device for reconfiguration of reliability data in flash eeprom storage pages
US20100070686A1 (en) * 2006-12-07 2010-03-18 Nxp, B.V. Method and device for reconfiguration of reliability data in flash eeprom storage pages
WO2008068706A1 (en) 2006-12-07 2008-06-12 Nxp B.V. Method and device for reconfiguration of reliability data in flash eeprom storage pages
US8060688B2 (en) 2006-12-07 2011-11-15 Nxp B.V. Method and device for reconfiguration of reliability data in flash EEPROM storage pages
US20080163028A1 (en) * 2006-12-29 2008-07-03 Nima Mokhlesi Page by page ecc variation in a memory device
US7877665B2 (en) * 2006-12-29 2011-01-25 Sandisk Corporation Page by page ECC variation in a memory device
US20080158959A1 (en) * 2006-12-29 2008-07-03 Nima Mokhlesi Page by page ecc variation in a memory device
US7870457B2 (en) * 2006-12-29 2011-01-11 Sandisk Corporation Page by page ECC variation in a memory device
US8112692B2 (en) 2007-01-08 2012-02-07 Samsung Electronics Co., Ltd. Flash memory device error correction code controllers and related methods and memory systems
US7904790B2 (en) * 2007-01-08 2011-03-08 Samsung Electronics Co., Ltd. Flash memory device error correction code controllers and related methods and memory systems
US8788905B2 (en) 2007-01-08 2014-07-22 Samsung Electronics Co., Ltd. Flash memory device error correction code controllers and related methods and memory systems
US20080168319A1 (en) * 2007-01-08 2008-07-10 Samsung Electronics Co., Ltd. Flash memory Device Error Correction Code Controllers and Related Methods and Memory Systems
US20110119561A1 (en) * 2007-01-08 2011-05-19 Chang-Duck Lee Flash Memory Device Error Correction Code Controllers and Related Methods and Memory Systems
US20110119560A1 (en) * 2007-01-08 2011-05-19 Chang-Duck Lee Flash Memory Device Error Correction Code Controllers and Related Methods and Memory Systems
US20080205229A1 (en) * 2007-02-26 2008-08-28 Yung-Chih Li Method of identifying optical disc
US20080250300A1 (en) * 2007-03-29 2008-10-09 Nima Mokhlesi Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US7904793B2 (en) * 2007-03-29 2011-03-08 Sandisk Corporation Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US8468424B2 (en) * 2007-03-29 2013-06-18 Sandisk Technologies Inc. Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US20110131473A1 (en) * 2007-03-29 2011-06-02 Sandisk Corporation Method For Decoding Data In Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads
US8966350B2 (en) * 2007-03-29 2015-02-24 Sandisk Technologies Inc. Providing reliability metrics for decoding data in non-volatile storage
US20130246720A1 (en) * 2007-03-29 2013-09-19 Sandisk Technologies Inc. Providing Reliability Metrics For Decoding Data In Non-Volatile Storage
US7966546B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Non-volatile memory with soft bit data transmission for error correction control
US20080244360A1 (en) * 2007-03-31 2008-10-02 Nima Mokhlesi Non-Volatile Memory with Soft Bit Data Transmission for Error Correction Control
US7971127B2 (en) * 2007-03-31 2011-06-28 Sandisk Technologies Inc. Guided simulated annealing in non-volatile memory error correction control
US20110252283A1 (en) * 2007-03-31 2011-10-13 Nima Mokhlesi Soft Bit Data Transmission For Error Correction Control In Non-Volatile Memory
US7966550B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Soft bit data transmission for error correction control in non-volatile memory
US20080244338A1 (en) * 2007-03-31 2008-10-02 Nima Mokhlesi Soft bit data transmission for error correction control in non-volatile memory
US7975209B2 (en) 2007-03-31 2011-07-05 Sandisk Technologies Inc. Non-volatile memory with guided simulated annealing error correction control
US8145981B2 (en) * 2007-03-31 2012-03-27 Sandisk Technologies Inc. Soft bit data transmission for error correction control in non-volatile memory
US20080244367A1 (en) * 2007-03-31 2008-10-02 Henry Chin Non-volatile memory with guided simulated annealing error correction control
US20080244368A1 (en) * 2007-03-31 2008-10-02 Henry Chin Guided Simulated Annealing in Non-Volatile Memory Error Correction Control
US20090067551A1 (en) * 2007-09-12 2009-03-12 Digital Fountain, Inc. Generating and communicating source identification information to enable reliable communications
US9237101B2 (en) 2007-09-12 2016-01-12 Digital Fountain, Inc. Generating and communicating source identification information to enable reliable communications
US20090172335A1 (en) * 2007-12-31 2009-07-02 Anand Krishnamurthi Kulkarni Flash devices with raid
US8001432B2 (en) * 2008-11-20 2011-08-16 Lsi Corporation Uninitialized memory detection using error correction codes and built-in self test
US20110276846A1 (en) * 2008-11-20 2011-11-10 Yair Orbach Uninitialized memory detection using error correction codes and built-in self test
US8261140B2 (en) * 2008-11-20 2012-09-04 Lsi Corporation Uninitialized memory detection using error correction codes and built-in self test
US20100125765A1 (en) * 2008-11-20 2010-05-20 Yair Orbach Uninitialized memory detection using error correction codes and built-in self test
US20100211690A1 (en) * 2009-02-13 2010-08-19 Digital Fountain, Inc. Block partitioning for a data stream
US20100223530A1 (en) * 2009-02-27 2010-09-02 Samsung Electronics Co., Ltd. Semiconductor memory device and data processing method thereof
US8321760B2 (en) * 2009-02-27 2012-11-27 Samsung Electronics Co., Ltd. Semiconductor memory device and data processing method thereof
US20100223533A1 (en) * 2009-02-27 2010-09-02 Qualcomm Incorporated Mobile reception of digital video broadcasting-terrestrial services
US9281847B2 (en) 2009-02-27 2016-03-08 Qualcomm Incorporated Mobile reception of digital video broadcasting—terrestrial services
US9419749B2 (en) 2009-08-19 2016-08-16 Qualcomm Incorporated Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
US9660763B2 (en) 2009-08-19 2017-05-23 Qualcomm Incorporated Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
US9876607B2 (en) 2009-08-19 2018-01-23 Qualcomm Incorporated Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
US9288010B2 (en) 2009-08-19 2016-03-15 Qualcomm Incorporated Universal file delivery methods for providing unequal error protection and bundled file delivery services
US9917874B2 (en) 2009-09-22 2018-03-13 Qualcomm Incorporated Enhanced block-request streaming using block partitioning or request controls for improved client-side handling
US20110096828A1 (en) * 2009-09-22 2011-04-28 Qualcomm Incorporated Enhanced block-request streaming using scalable encoding
US9602802B2 (en) 2010-07-21 2017-03-21 Qualcomm Incorporated Providing frame packing type information for video coding
US8806050B2 (en) 2010-08-10 2014-08-12 Qualcomm Incorporated Manifest file updates for network streaming of coded multimedia data
US9319448B2 (en) 2010-08-10 2016-04-19 Qualcomm Incorporated Trick modes for network streaming of coded multimedia data
US9456015B2 (en) 2010-08-10 2016-09-27 Qualcomm Incorporated Representation groups for network streaming of coded multimedia data
US9270299B2 (en) 2011-02-11 2016-02-23 Qualcomm Incorporated Encoding and decoding using elastic codes with flexible source block mapping
US8958375B2 (en) 2011-02-11 2015-02-17 Qualcomm Incorporated Framing for an improved radio link protocol including FEC
US20120233523A1 (en) * 2011-03-10 2012-09-13 Icform, Inc Programmable Data Storage Management
US8732538B2 (en) * 2011-03-10 2014-05-20 Icform, Inc. Programmable data storage management
US9213597B2 (en) * 2011-07-12 2015-12-15 Phison Electronics Corp. Memory storage device, memory controller thereof, and method for programming data thereof
US20130019142A1 (en) * 2011-07-12 2013-01-17 Phison Electronics Corp. Memory storage device, memory controller thereof, and method for programming data thereof
US9253233B2 (en) 2011-08-31 2016-02-02 Qualcomm Incorporated Switch signaling methods providing improved switching between representations for adaptive HTTP streaming
US9843844B2 (en) 2011-10-05 2017-12-12 Qualcomm Incorporated Network streaming of media data
US9294226B2 (en) 2012-03-26 2016-03-22 Qualcomm Incorporated Universal object delivery and template-based file delivery
US8910017B2 (en) 2012-07-02 2014-12-09 Sandisk Technologies Inc. Flash memory with random partition
US9135112B2 (en) * 2012-12-11 2015-09-15 Seagate Technology Llc Policy for read operations addressing on-the-fly decoding failure in non-volatile memory
US10116336B2 (en) 2014-06-13 2018-10-30 Sandisk Technologies Llc Error correcting code adjustment for a data storage device
FR3039922A1 (en) * 2015-08-06 2017-02-10 Stmicroelectronics (Rousset) Sas A method of writing in a memory of the EEPROM type memory device and corresponding
US10013208B2 (en) 2015-08-06 2018-07-03 Stmicroelectronics (Rousset) Sas Method for writing in an EEPROM memory and corresponding memory
CN106448730A (en) * 2015-08-06 2017-02-22 意法半导体(鲁塞)公司 Method for Writing in an EEPROM Memory and Corresponding Memory
US10304550B1 (en) 2017-11-29 2019-05-28 Sandisk Technologies Llc Sense amplifier with negative threshold sensing for non-volatile memory

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