JP2001345294A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2001345294A
JP2001345294A JP2000163045A JP2000163045A JP2001345294A JP 2001345294 A JP2001345294 A JP 2001345294A JP 2000163045 A JP2000163045 A JP 2000163045A JP 2000163045 A JP2000163045 A JP 2000163045A JP 2001345294 A JP2001345294 A JP 2001345294A
Authority
JP
Japan
Prior art keywords
wafer
film
substrate
edge
bevel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000163045A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001345294A5 (enExample
Inventor
Hiroyuki Yano
博之 矢野
Katsuya Okumura
勝弥 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000163045A priority Critical patent/JP2001345294A/ja
Priority to US09/870,085 priority patent/US6924236B2/en
Publication of JP2001345294A publication Critical patent/JP2001345294A/ja
Publication of JP2001345294A5 publication Critical patent/JP2001345294A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2000163045A 2000-05-31 2000-05-31 半導体装置の製造方法 Pending JP2001345294A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000163045A JP2001345294A (ja) 2000-05-31 2000-05-31 半導体装置の製造方法
US09/870,085 US6924236B2 (en) 2000-05-31 2001-05-30 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000163045A JP2001345294A (ja) 2000-05-31 2000-05-31 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2001345294A true JP2001345294A (ja) 2001-12-14
JP2001345294A5 JP2001345294A5 (enExample) 2005-06-16

Family

ID=18666862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000163045A Pending JP2001345294A (ja) 2000-05-31 2000-05-31 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US6924236B2 (enExample)
JP (1) JP2001345294A (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933234B2 (en) 2001-11-26 2005-08-23 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and polishing apparatus
JP2008042220A (ja) * 2007-09-25 2008-02-21 Ebara Corp 基板処理方法及び装置
US7621799B2 (en) 2006-08-08 2009-11-24 Sony Corporation Polishing method and polishing device
JP2010212440A (ja) * 2009-03-10 2010-09-24 Fuji Electric Systems Co Ltd 半導体装置の製造方法
US8210905B2 (en) 2008-04-30 2012-07-03 Sony Corporation Wafer polishing device and method
KR20120112242A (ko) * 2011-03-31 2012-10-11 이와타니 산교 가부시키가이샤 기판 세정 장치 및 진공 처리 시스템
US8926402B2 (en) 2010-11-26 2015-01-06 Ebara Corporation Method of polishing a substrate using a polishing tape having fixed abrasive

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555895B1 (en) * 2000-07-17 2003-04-29 General Semiconductor, Inc. Devices and methods for addressing optical edge effects in connection with etched trenches
JP2002313757A (ja) * 2001-04-17 2002-10-25 Hitachi Ltd 半導体集積回路装置の製造方法
KR20030044205A (ko) * 2001-11-29 2003-06-09 동부전자 주식회사 반도체 제조 장치 및 방법
JP2005026413A (ja) 2003-07-01 2005-01-27 Renesas Technology Corp 半導体ウエハ、半導体素子およびその製造方法
US20060172526A1 (en) * 2003-10-16 2006-08-03 United Microelectronics Corp. Method for preventing edge peeling defect
TW200527485A (en) * 2004-01-30 2005-08-16 Semiconductor Leading Edge Tec Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device
JP4284215B2 (ja) * 2004-03-24 2009-06-24 株式会社東芝 基板処理方法
US7998865B2 (en) * 2005-05-31 2011-08-16 Texas Instruments Incorporated Systems and methods for removing wafer edge residue and debris using a residue remover mechanism
US20060266383A1 (en) * 2005-05-31 2006-11-30 Texas Instruments Incorporated Systems and methods for removing wafer edge residue and debris using a wafer clean solution
KR100722128B1 (ko) * 2005-12-28 2007-05-25 동부일렉트로닉스 주식회사 반도체 소자 제조방법
DE102006030266A1 (de) * 2006-06-30 2008-01-03 Advanced Micro Devices, Inc., Sunnyvale Verringern der Kontamination von Halbleitersubstraten während der Metallisierungsbearbeitung durch Bereitstellen einer Schutzschicht am Substratrand
TW200845302A (en) * 2007-05-09 2008-11-16 Promos Technologies Inc A method of two-step backside etching
CN104882405B (zh) * 2014-02-27 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
JP6304445B2 (ja) * 2015-03-16 2018-04-04 富士電機株式会社 半導体装置の製造方法
JP6676365B2 (ja) * 2015-12-21 2020-04-08 キヤノン株式会社 撮像装置の製造方法
CN110718462B (zh) 2018-07-10 2022-01-18 联华电子股份有限公司 在半导体晶片上制作半导体结构的方法
KR102898430B1 (ko) 2019-08-26 2025-12-09 삼성전자 주식회사 반도체 소자 제조 방법
FR3113182B1 (fr) * 2020-07-31 2022-08-12 Commissariat Energie Atomique Procédé d'assemblage de plaques par collage moléculaire
TWI892014B (zh) 2022-05-25 2025-08-01 聯華電子股份有限公司 半導體結構及其製造方法
TWI869824B (zh) * 2023-04-19 2025-01-11 力晶積成電子製造股份有限公司 晶圓的處理方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154614A (ja) 1985-12-27 1987-07-09 Toshiba Corp 接合型半導体基板の製造方法
JP2645478B2 (ja) 1988-10-07 1997-08-25 富士通株式会社 半導体装置の製造方法
JP2857816B2 (ja) 1992-05-29 1999-02-17 株式会社サンシン ウエハー材縁端面研磨装置
US5578516A (en) * 1995-07-07 1996-11-26 Vanguard International Semiconductor Corporation High capacitance dynamic random access memory manufacturing process
US5795804A (en) * 1996-03-07 1998-08-18 United Microelectronics Corporation Method of fabricating a stack/trench capacitor for a dynamic random access memory (DRAM)
US6291315B1 (en) * 1996-07-11 2001-09-18 Denso Corporation Method for etching trench in manufacturing semiconductor devices
JP3311979B2 (ja) 1997-12-12 2002-08-05 株式会社東芝 半導体集積回路装置
US6265314B1 (en) * 1998-06-09 2001-07-24 Advanced Micro Devices, Inc. Wafer edge polish
US6267649B1 (en) 1999-08-23 2001-07-31 Industrial Technology Research Institute Edge and bevel CMP of copper wafer
US6722964B2 (en) 2000-04-04 2004-04-20 Ebara Corporation Polishing apparatus and method

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6933234B2 (en) 2001-11-26 2005-08-23 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and polishing apparatus
US7351131B2 (en) 2001-11-26 2008-04-01 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and polishing apparatus
US7621799B2 (en) 2006-08-08 2009-11-24 Sony Corporation Polishing method and polishing device
JP2008042220A (ja) * 2007-09-25 2008-02-21 Ebara Corp 基板処理方法及び装置
US8210905B2 (en) 2008-04-30 2012-07-03 Sony Corporation Wafer polishing device and method
JP2010212440A (ja) * 2009-03-10 2010-09-24 Fuji Electric Systems Co Ltd 半導体装置の製造方法
US8926402B2 (en) 2010-11-26 2015-01-06 Ebara Corporation Method of polishing a substrate using a polishing tape having fixed abrasive
KR20120112242A (ko) * 2011-03-31 2012-10-11 이와타니 산교 가부시키가이샤 기판 세정 장치 및 진공 처리 시스템
JP2012216636A (ja) * 2011-03-31 2012-11-08 Tokyo Electron Ltd 基板洗浄装置及び真空処理システム
US9214364B2 (en) 2011-03-31 2015-12-15 Tokyo Electron Limited Substrate cleaning apparatus and vacuum processing system
KR101671555B1 (ko) 2011-03-31 2016-11-01 도쿄엘렉트론가부시키가이샤 기판 세정 장치 및 진공 처리 시스템

Also Published As

Publication number Publication date
US20010051432A1 (en) 2001-12-13
US6924236B2 (en) 2005-08-02

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