JP2001186009A5 - - Google Patents

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Publication number
JP2001186009A5
JP2001186009A5 JP1999365664A JP36566499A JP2001186009A5 JP 2001186009 A5 JP2001186009 A5 JP 2001186009A5 JP 1999365664 A JP1999365664 A JP 1999365664A JP 36566499 A JP36566499 A JP 36566499A JP 2001186009 A5 JP2001186009 A5 JP 2001186009A5
Authority
JP
Japan
Prior art keywords
node
potential
switch means
logic
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP1999365664A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001186009A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP36566499A priority Critical patent/JP2001186009A/ja
Priority claimed from JP36566499A external-priority patent/JP2001186009A/ja
Priority to TW089103242A priority patent/TW463166B/zh
Priority to US09/514,256 priority patent/US6374393B1/en
Priority to CNB001083511A priority patent/CN1175421C/zh
Priority to EP00400539A priority patent/EP1111615A1/en
Priority to KR1020000010243A priority patent/KR100613738B1/ko
Publication of JP2001186009A publication Critical patent/JP2001186009A/ja
Publication of JP2001186009A5 publication Critical patent/JP2001186009A5/ja
Abandoned legal-status Critical Current

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JP36566499A 1999-12-22 1999-12-22 論理回路 Abandoned JP2001186009A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP36566499A JP2001186009A (ja) 1999-12-22 1999-12-22 論理回路
TW089103242A TW463166B (en) 1999-12-22 2000-02-24 Logic circuit
US09/514,256 US6374393B1 (en) 1999-12-22 2000-02-28 Logic circuit evaluation using sensing latch logic
CNB001083511A CN1175421C (zh) 1999-12-22 2000-02-29 逻辑电路
EP00400539A EP1111615A1 (en) 1999-12-22 2000-02-29 Logic circuit
KR1020000010243A KR100613738B1 (ko) 1999-12-22 2000-02-29 논리 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36566499A JP2001186009A (ja) 1999-12-22 1999-12-22 論理回路

Publications (2)

Publication Number Publication Date
JP2001186009A JP2001186009A (ja) 2001-07-06
JP2001186009A5 true JP2001186009A5 (https=) 2006-10-19

Family

ID=18484821

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36566499A Abandoned JP2001186009A (ja) 1999-12-22 1999-12-22 論理回路

Country Status (6)

Country Link
US (1) US6374393B1 (https=)
EP (1) EP1111615A1 (https=)
JP (1) JP2001186009A (https=)
KR (1) KR100613738B1 (https=)
CN (1) CN1175421C (https=)
TW (1) TW463166B (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10022263A1 (de) * 2000-05-08 2001-11-22 Infineon Technologies Ag Speicher-Leseverstärker
US6557149B2 (en) * 2001-04-04 2003-04-29 Intel Corporation Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate
DE10217375B4 (de) * 2002-04-18 2006-08-24 Infineon Technologies Ag Schaltungsanordnung und Verfahren zur Erzeugung eines Dual-Rail-Signals
US6886152B1 (en) * 2002-08-09 2005-04-26 Xilinx, Inc. Delay optimization in signal routing
AU2003257119A1 (en) * 2002-08-23 2004-03-11 Sun Microsystems, Inc. Clocked full-rail differential logic with sense amplifier and shut-off
DE102004037591A1 (de) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual-Rail Precharged Flip-Flop
US7131092B2 (en) * 2004-12-21 2006-10-31 Via Technologies, Inc. Clock gating circuit
JP4859370B2 (ja) * 2005-01-19 2012-01-25 三菱電機株式会社 電子素子
US7302659B2 (en) * 2005-02-10 2007-11-27 International Business Machines Corporation System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
US7447620B2 (en) * 2006-02-23 2008-11-04 International Business Machines Corporation Modeling asynchronous behavior from primary inputs and latches
US7437584B2 (en) * 2006-02-27 2008-10-14 Atmel Corporation Apparatus and method for reducing power consumption in electronic devices
US7490305B2 (en) * 2006-07-17 2009-02-10 International Business Machines Corporation Method for driving values to DC adjusted/untimed nets to identify timing problems
US7882473B2 (en) * 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
US20090167395A1 (en) * 2007-12-31 2009-07-02 Texas Instruments Incorporated High performance latches
US7861200B2 (en) * 2008-03-24 2010-12-28 Freescale Semiconductor, Inc. Setup and hold time characterization device and method
US8122410B2 (en) * 2008-11-05 2012-02-21 International Business Machines Corporation Specifying and validating untimed nets
US20110016367A1 (en) * 2009-07-14 2011-01-20 Bo Tang Skew tolerant scannable master/slave flip-flop including embedded logic
KR20110105153A (ko) * 2010-03-18 2011-09-26 삼성전자주식회사 플립플롭 회로 및 스캔 플립 플롭 회로
US8975949B2 (en) * 2013-03-14 2015-03-10 Samsung Electronics Co., Ltd. Integrated clock gater (ICG) using clock cascode complimentary switch logic
US9256245B2 (en) * 2014-04-02 2016-02-09 Mediatek Inc. Clock tree circuit and memory controller
KR20160005535A (ko) * 2014-07-07 2016-01-15 에스케이하이닉스 주식회사 반도체 장치의 리시버 회로
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US11658656B2 (en) 2020-11-26 2023-05-23 Samsung Electronics Co., Ltd. Low power clock gating cell and an integrated circuit including the same
KR20220143272A (ko) 2021-04-16 2022-10-25 삼성전자주식회사 직렬 스택 구조의 트랜지스터들을 포함하는 플립 플롭
TW202533531A (zh) * 2023-12-27 2025-08-16 日商索尼半導體解決方案公司 邏輯運算電路

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002270A (en) * 1995-11-09 1999-12-14 Spaceborne, Inc. Synchronous differential logic system for hyperfrequency operation
JPH10269774A (ja) * 1997-03-26 1998-10-09 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR100434965B1 (ko) * 1997-12-29 2004-07-16 주식회사 하이닉스반도체 센스앰프 구동장치

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