KR100613738B1 - 논리 회로 - Google Patents

논리 회로 Download PDF

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Publication number
KR100613738B1
KR100613738B1 KR1020000010243A KR20000010243A KR100613738B1 KR 100613738 B1 KR100613738 B1 KR 100613738B1 KR 1020000010243 A KR1020000010243 A KR 1020000010243A KR 20000010243 A KR20000010243 A KR 20000010243A KR 100613738 B1 KR100613738 B1 KR 100613738B1
Authority
KR
South Korea
Prior art keywords
logic
switch means
node
potential
logic output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020000010243A
Other languages
English (en)
Korean (ko)
Other versions
KR20010082496A (ko
Inventor
히라이리고지
Original Assignee
소니 가부시끼 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Publication of KR20010082496A publication Critical patent/KR20010082496A/ko
Application granted granted Critical
Publication of KR100613738B1 publication Critical patent/KR100613738B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
KR1020000010243A 1999-12-22 2000-02-29 논리 회로 Expired - Fee Related KR100613738B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP36566499A JP2001186009A (ja) 1999-12-22 1999-12-22 論理回路
JP99-365664 1999-12-22

Publications (2)

Publication Number Publication Date
KR20010082496A KR20010082496A (ko) 2001-08-30
KR100613738B1 true KR100613738B1 (ko) 2006-08-22

Family

ID=18484821

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000010243A Expired - Fee Related KR100613738B1 (ko) 1999-12-22 2000-02-29 논리 회로

Country Status (6)

Country Link
US (1) US6374393B1 (https=)
EP (1) EP1111615A1 (https=)
JP (1) JP2001186009A (https=)
KR (1) KR100613738B1 (https=)
CN (1) CN1175421C (https=)
TW (1) TW463166B (https=)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10022263A1 (de) * 2000-05-08 2001-11-22 Infineon Technologies Ag Speicher-Leseverstärker
US6557149B2 (en) * 2001-04-04 2003-04-29 Intel Corporation Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate
DE10217375B4 (de) * 2002-04-18 2006-08-24 Infineon Technologies Ag Schaltungsanordnung und Verfahren zur Erzeugung eines Dual-Rail-Signals
US6886152B1 (en) * 2002-08-09 2005-04-26 Xilinx, Inc. Delay optimization in signal routing
AU2003257119A1 (en) * 2002-08-23 2004-03-11 Sun Microsystems, Inc. Clocked full-rail differential logic with sense amplifier and shut-off
DE102004037591A1 (de) * 2004-08-03 2006-03-16 Infineon Technologies Ag Dual-Rail Precharged Flip-Flop
US7131092B2 (en) * 2004-12-21 2006-10-31 Via Technologies, Inc. Clock gating circuit
JP4859370B2 (ja) * 2005-01-19 2012-01-25 三菱電機株式会社 電子素子
US7302659B2 (en) * 2005-02-10 2007-11-27 International Business Machines Corporation System and method for unfolding/replicating logic paths to facilitate propagation delay modeling
US7447620B2 (en) * 2006-02-23 2008-11-04 International Business Machines Corporation Modeling asynchronous behavior from primary inputs and latches
US7437584B2 (en) * 2006-02-27 2008-10-14 Atmel Corporation Apparatus and method for reducing power consumption in electronic devices
US7490305B2 (en) * 2006-07-17 2009-02-10 International Business Machines Corporation Method for driving values to DC adjusted/untimed nets to identify timing problems
US7882473B2 (en) * 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
US20090167395A1 (en) * 2007-12-31 2009-07-02 Texas Instruments Incorporated High performance latches
US7861200B2 (en) * 2008-03-24 2010-12-28 Freescale Semiconductor, Inc. Setup and hold time characterization device and method
US8122410B2 (en) * 2008-11-05 2012-02-21 International Business Machines Corporation Specifying and validating untimed nets
US20110016367A1 (en) * 2009-07-14 2011-01-20 Bo Tang Skew tolerant scannable master/slave flip-flop including embedded logic
KR20110105153A (ko) * 2010-03-18 2011-09-26 삼성전자주식회사 플립플롭 회로 및 스캔 플립 플롭 회로
US8975949B2 (en) * 2013-03-14 2015-03-10 Samsung Electronics Co., Ltd. Integrated clock gater (ICG) using clock cascode complimentary switch logic
US9256245B2 (en) * 2014-04-02 2016-02-09 Mediatek Inc. Clock tree circuit and memory controller
KR20160005535A (ko) * 2014-07-07 2016-01-15 에스케이하이닉스 주식회사 반도체 장치의 리시버 회로
TWI705666B (zh) * 2015-06-15 2020-09-21 日商新力股份有限公司 傳送裝置、接收裝置、通信系統
US11658656B2 (en) 2020-11-26 2023-05-23 Samsung Electronics Co., Ltd. Low power clock gating cell and an integrated circuit including the same
KR20220143272A (ko) 2021-04-16 2022-10-25 삼성전자주식회사 직렬 스택 구조의 트랜지스터들을 포함하는 플립 플롭
TW202533531A (zh) * 2023-12-27 2025-08-16 日商索尼半導體解決方案公司 邏輯運算電路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10269774A (ja) * 1997-03-26 1998-10-09 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR19990057358A (ko) * 1997-12-29 1999-07-15 김영환 센스앰프 구동장치
US6002270A (en) * 1995-11-09 1999-12-14 Spaceborne, Inc. Synchronous differential logic system for hyperfrequency operation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002270A (en) * 1995-11-09 1999-12-14 Spaceborne, Inc. Synchronous differential logic system for hyperfrequency operation
JPH10269774A (ja) * 1997-03-26 1998-10-09 Matsushita Electric Ind Co Ltd 半導体記憶装置
KR19990057358A (ko) * 1997-12-29 1999-07-15 김영환 센스앰프 구동장치

Also Published As

Publication number Publication date
US6374393B1 (en) 2002-04-16
CN1175421C (zh) 2004-11-10
TW463166B (en) 2001-11-11
JP2001186009A (ja) 2001-07-06
CN1301023A (zh) 2001-06-27
EP1111615A1 (en) 2001-06-27
KR20010082496A (ko) 2001-08-30

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