JP2001185552A - 半導体集積回路装置およびその製造方法 - Google Patents

半導体集積回路装置およびその製造方法

Info

Publication number
JP2001185552A
JP2001185552A JP37079099A JP37079099A JP2001185552A JP 2001185552 A JP2001185552 A JP 2001185552A JP 37079099 A JP37079099 A JP 37079099A JP 37079099 A JP37079099 A JP 37079099A JP 2001185552 A JP2001185552 A JP 2001185552A
Authority
JP
Japan
Prior art keywords
film
wiring
interlayer insulating
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP37079099A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001185552A5 (https=
Inventor
Takashi Aoyanagi
隆 青柳
Junji Ogishima
淳史 荻島
Hironao Kobayashi
宏尚 小林
Yuji Hara
雄次 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP37079099A priority Critical patent/JP2001185552A/ja
Priority to TW089126482A priority patent/TW503492B/zh
Priority to KR1020000075456A priority patent/KR20010062344A/ko
Priority to US09/748,163 priority patent/US6573170B2/en
Priority to US09/811,535 priority patent/US20010019180A1/en
Publication of JP2001185552A publication Critical patent/JP2001185552A/ja
Publication of JP2001185552A5 publication Critical patent/JP2001185552A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H10W72/9232—Bond pads having multiple stacked layers with additional elements interposed between layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
JP37079099A 1999-12-27 1999-12-27 半導体集積回路装置およびその製造方法 Pending JP2001185552A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP37079099A JP2001185552A (ja) 1999-12-27 1999-12-27 半導体集積回路装置およびその製造方法
TW089126482A TW503492B (en) 1999-12-27 2000-12-12 Semiconductor integrated circuit device and manufacturing method of the same
KR1020000075456A KR20010062344A (ko) 1999-12-27 2000-12-12 반도체 집적회로장치 및 그 제조방법
US09/748,163 US6573170B2 (en) 1999-12-27 2000-12-27 Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device
US09/811,535 US20010019180A1 (en) 1999-12-27 2001-03-20 Semiconductor integrated circuit device and process for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37079099A JP2001185552A (ja) 1999-12-27 1999-12-27 半導体集積回路装置およびその製造方法

Publications (2)

Publication Number Publication Date
JP2001185552A true JP2001185552A (ja) 2001-07-06
JP2001185552A5 JP2001185552A5 (https=) 2004-10-28

Family

ID=18497607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP37079099A Pending JP2001185552A (ja) 1999-12-27 1999-12-27 半導体集積回路装置およびその製造方法

Country Status (4)

Country Link
US (2) US6573170B2 (https=)
JP (1) JP2001185552A (https=)
KR (1) KR20010062344A (https=)
TW (1) TW503492B (https=)

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KR100400047B1 (ko) * 2001-11-19 2003-09-29 삼성전자주식회사 반도체 소자의 본딩패드 구조 및 그 형성방법
US6696357B2 (en) 2001-08-30 2004-02-24 Renesas Technology Corporation Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film
JP2007227556A (ja) * 2006-02-22 2007-09-06 Nec Electronics Corp 半導体装置
US8178981B2 (en) 2004-02-26 2012-05-15 Renesas Electronics Corporation Semiconductor device
JP2015222819A (ja) * 2009-06-18 2015-12-10 ローム株式会社 半導体装置

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KR100400033B1 (ko) * 2001-02-08 2003-09-29 삼성전자주식회사 다층 배선 구조를 갖는 반도체 소자 및 그의 제조방법
KR100389925B1 (ko) * 2001-03-05 2003-07-04 삼성전자주식회사 반도체 메모리 소자 및 그의 제조 방법
US6984892B2 (en) * 2001-03-28 2006-01-10 Lam Research Corporation Semiconductor structure implementing low-K dielectric materials and supporting stubs
JP2003017522A (ja) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP3790469B2 (ja) * 2001-12-21 2006-06-28 富士通株式会社 半導体装置
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP3974470B2 (ja) * 2002-07-22 2007-09-12 株式会社東芝 半導体装置
JP2004095916A (ja) 2002-08-30 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
US7692315B2 (en) * 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
KR100545865B1 (ko) * 2003-06-25 2006-01-24 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR100591146B1 (ko) * 2003-07-11 2006-06-19 동부일렉트로닉스 주식회사 반도체 소자 및 반도체 소자의 본딩 패드 형성 방법
US8319307B1 (en) 2004-11-19 2012-11-27 Voxtel, Inc. Active pixel sensors with variable threshold reset
JP2006196668A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 半導体装置及びその製造方法
US7678713B2 (en) * 2005-08-04 2010-03-16 Texas Instruments Incorporated Energy beam treatment to improve packaging reliability
JP4708148B2 (ja) 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4995455B2 (ja) * 2005-11-30 2012-08-08 ルネサスエレクトロニクス株式会社 半導体装置
KR100873019B1 (ko) 2007-07-13 2008-12-10 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
JP2009027048A (ja) * 2007-07-23 2009-02-05 Panasonic Corp 半導体装置の製造方法
US8030775B2 (en) * 2007-08-27 2011-10-04 Megica Corporation Wirebond over post passivation thick metal
KR100933685B1 (ko) * 2007-12-18 2009-12-23 주식회사 하이닉스반도체 필링 방지를 위한 본딩패드 및 그 형성 방법
KR101406225B1 (ko) * 2008-04-11 2014-06-13 삼성전자주식회사 반도체 소자의 제조방법
US8440508B2 (en) * 2009-03-06 2013-05-14 Texas Instruments Incorporated Hydrogen barrier for ferroelectric capacitors
JP5837783B2 (ja) * 2011-09-08 2015-12-24 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US10217644B2 (en) 2012-07-24 2019-02-26 Infineon Technologies Ag Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures
KR101455255B1 (ko) * 2014-02-28 2014-10-31 삼성전자주식회사 반도체 소자의 제조방법
KR20160050431A (ko) * 2014-10-29 2016-05-11 삼성전자주식회사 Ｍｉｓ 접합을 가지는 메모리 소자와 그 제조방법
US11114444B2 (en) * 2019-05-24 2021-09-07 Nanya Technology Corporation Semiconductor device with conductive cap layer over conductive plug and method for forming the same
US12245423B2 (en) 2019-05-24 2025-03-04 Nanya Technology Corporation Semiconductor device with conductive cap layer over conductive plug and method for preparinging the same

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JPH08191104A (ja) * 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3526376B2 (ja) * 1996-08-21 2004-05-10 株式会社東芝 半導体装置及びその製造方法
JPH10247664A (ja) * 1997-03-04 1998-09-14 Hitachi Ltd 半導体集積回路装置およびその製造方法
TW408433B (en) * 1997-06-30 2000-10-11 Hitachi Ltd Method for fabricating semiconductor integrated circuit
JP3686248B2 (ja) * 1998-01-26 2005-08-24 株式会社日立製作所 半導体集積回路装置およびその製造方法
JP2000012796A (ja) * 1998-06-19 2000-01-14 Hitachi Ltd 半導体装置ならびにその製造方法および製造装置
JP2000077625A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体集積回路装置の製造方法
JP2000156480A (ja) * 1998-09-03 2000-06-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6239681B1 (en) * 1998-11-30 2001-05-29 Harrie R. Buswell Wire core for induction coils
JP3955404B2 (ja) * 1998-12-28 2007-08-08 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6291331B1 (en) * 1999-10-04 2001-09-18 Taiwan Semiconductor Manufacturing Company Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6696357B2 (en) 2001-08-30 2004-02-24 Renesas Technology Corporation Method for manufacturing semiconductor integrated circuit devices using a conductive layer to prevent peeling between a bonding pad and an underlying insulating film
KR100400047B1 (ko) * 2001-11-19 2003-09-29 삼성전자주식회사 반도체 소자의 본딩패드 구조 및 그 형성방법
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JP2007227556A (ja) * 2006-02-22 2007-09-06 Nec Electronics Corp 半導体装置
JP2015222819A (ja) * 2009-06-18 2015-12-10 ローム株式会社 半導体装置
US9780069B2 (en) 2009-06-18 2017-10-03 Rohm Co., Ltd. Semiconductor device
US10163850B2 (en) 2009-06-18 2018-12-25 Rohm Co., Ltd. Semiconductor device

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US20010019180A1 (en) 2001-09-06
US6573170B2 (en) 2003-06-03
KR20010062344A (ko) 2001-07-07
US20010005624A1 (en) 2001-06-28
TW503492B (en) 2002-09-21

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