JP2001184253A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2001184253A5 JP2001184253A5 JP1999365662A JP36566299A JP2001184253A5 JP 2001184253 A5 JP2001184253 A5 JP 2001184253A5 JP 1999365662 A JP1999365662 A JP 1999365662A JP 36566299 A JP36566299 A JP 36566299A JP 2001184253 A5 JP2001184253 A5 JP 2001184253A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- module
- column
- processor
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36566299A JP2001184253A (ja) | 1999-12-22 | 1999-12-22 | プロセッサシステムおよび記憶回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36566299A JP2001184253A (ja) | 1999-12-22 | 1999-12-22 | プロセッサシステムおよび記憶回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001184253A JP2001184253A (ja) | 2001-07-06 |
| JP2001184253A5 true JP2001184253A5 (enExample) | 2006-08-03 |
Family
ID=18484817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36566299A Pending JP2001184253A (ja) | 1999-12-22 | 1999-12-22 | プロセッサシステムおよび記憶回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001184253A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009098861A (ja) * | 2007-10-16 | 2009-05-07 | Renesas Technology Corp | 並列演算処理装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06103599B2 (ja) * | 1990-11-16 | 1994-12-14 | 三菱電機株式会社 | 半導体集積回路装置 |
| JP3458518B2 (ja) * | 1994-08-30 | 2003-10-20 | ソニー株式会社 | 並列プロセッサ |
| KR0140179B1 (ko) * | 1994-12-19 | 1998-07-15 | 김광호 | 불휘발성 반도체 메모리 |
| JPH10228765A (ja) * | 1996-10-31 | 1998-08-25 | Sony Corp | 半導体記憶装置 |
-
1999
- 1999-12-22 JP JP36566299A patent/JP2001184253A/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7990798B2 (en) | Integrated circuit including a memory module having a plurality of memory banks | |
| EP0264893A3 (en) | Semiconductor memory | |
| KR19990007287A (ko) | 반도체 집적회로, 컴퓨터 시스템, 데이터 처리장치 및 데이터 처리방법 | |
| JPS62152050A (ja) | 半導体メモリ | |
| EP0771006A3 (en) | Semiconductor memory | |
| KR100582821B1 (ko) | 멀티-포트 메모리 소자 | |
| EP0101884A3 (en) | Monolithic semiconductor memory | |
| US5745914A (en) | Technique for converting system signals from one address configuration to a different address configuration | |
| JPH0444695A (ja) | 半導体記憶装置 | |
| KR0164391B1 (ko) | 고속동작을 위한 회로 배치 구조를 가지는 반도체 메모리 장치 | |
| JP3781819B2 (ja) | 三重ポートを有する半導体メモリ装置 | |
| JPH0642536B2 (ja) | 半導体記憶装置 | |
| KR100718533B1 (ko) | 반도체 메모리 및 그 제어방법 | |
| JP2001184253A5 (enExample) | ||
| KR100599444B1 (ko) | 글로벌 데이터 버스 연결회로를 구비하는 멀티-포트메모리 소자 | |
| EP0883131A3 (en) | Semiconductor storage device such as cache memory | |
| JPS61227289A (ja) | 半導体記憶装置 | |
| JPS60133587A (ja) | 半導体記憶装置 | |
| JPS63300492A (ja) | 半導体メモリ装置 | |
| JP3715663B2 (ja) | マルチポートメモリの列デコーダ配置構造 | |
| US6141289A (en) | Structure of random access memory formed of multibit cells | |
| JP2567855B2 (ja) | 半導体記憶装置 | |
| KR100328374B1 (ko) | 반도체메모리및그구동방법 | |
| JPH0255877B2 (enExample) | ||
| JPH0517639B2 (enExample) |