JP2000299385A5 - - Google Patents

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Publication number
JP2000299385A5
JP2000299385A5 JP1999108915A JP10891599A JP2000299385A5 JP 2000299385 A5 JP2000299385 A5 JP 2000299385A5 JP 1999108915 A JP1999108915 A JP 1999108915A JP 10891599 A JP10891599 A JP 10891599A JP 2000299385 A5 JP2000299385 A5 JP 2000299385A5
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JP
Japan
Prior art keywords
nmos transistor
pmos transistor
gate
source
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999108915A
Other languages
English (en)
Japanese (ja)
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JP2000299385A (ja
JP3986036B2 (ja
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Publication date
Priority claimed from JP10891599A external-priority patent/JP3986036B2/ja
Priority to JP10891599A priority Critical patent/JP3986036B2/ja
Application filed filed Critical
Priority to US09/549,711 priority patent/US6356118B1/en
Priority to TW089106998A priority patent/TW494568B/zh
Priority to KR1020000019771A priority patent/KR100713765B1/ko
Publication of JP2000299385A publication Critical patent/JP2000299385A/ja
Priority to US10/052,251 priority patent/US6690206B2/en
Publication of JP2000299385A5 publication Critical patent/JP2000299385A5/ja
Publication of JP3986036B2 publication Critical patent/JP3986036B2/ja
Application granted granted Critical
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP10891599A 1999-04-16 1999-04-16 半導体集積回路装置 Expired - Lifetime JP3986036B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10891599A JP3986036B2 (ja) 1999-04-16 1999-04-16 半導体集積回路装置
US09/549,711 US6356118B1 (en) 1999-04-16 2000-04-14 Semiconductor integrated circuit device
TW089106998A TW494568B (en) 1999-04-16 2000-04-14 Semiconductor integrated circuit device
KR1020000019771A KR100713765B1 (ko) 1999-04-16 2000-04-15 반도체 집적 회로 장치
US10/052,251 US6690206B2 (en) 1999-04-16 2002-01-23 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10891599A JP3986036B2 (ja) 1999-04-16 1999-04-16 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2000299385A JP2000299385A (ja) 2000-10-24
JP2000299385A5 true JP2000299385A5 (enExample) 2004-09-16
JP3986036B2 JP3986036B2 (ja) 2007-10-03

Family

ID=14496881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10891599A Expired - Lifetime JP3986036B2 (ja) 1999-04-16 1999-04-16 半導体集積回路装置

Country Status (4)

Country Link
US (2) US6356118B1 (enExample)
JP (1) JP3986036B2 (enExample)
KR (1) KR100713765B1 (enExample)
TW (1) TW494568B (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3555080B2 (ja) * 2000-10-19 2004-08-18 Ｎｅｃエレクトロニクス株式会社 汎用ロジックモジュール及びこれを用いたセル
US6779158B2 (en) * 2001-06-15 2004-08-17 Science & Technology Corporation @ Unm Digital logic optimization using selection operators
JP4156864B2 (ja) * 2002-05-17 2008-09-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2003338750A (ja) * 2002-05-20 2003-11-28 Nec Electronics Corp 汎用ロジックセル、これを用いた汎用ロジックセルアレイ、及びこの汎用ロジックセルアレイを用いたａｓｉｃ
DE102004007398B4 (de) * 2004-02-16 2007-10-18 Infineon Technologies Ag Konfigurierbare Gate-Array-Zelle mit erweiterter Gate-Elektrode
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
MY152456A (en) 2008-07-16 2014-09-30 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
WO2010122754A1 (ja) * 2009-04-22 2010-10-28 パナソニック株式会社 半導体集積回路
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US11062739B2 (en) * 2019-06-27 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor chip having memory and logic cells
CN112908987B (zh) * 2021-03-22 2025-06-27 西安紫光国芯半导体股份有限公司 三维集成电路及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200907A (en) * 1990-04-16 1993-04-06 Tran Dzung J Transmission gate logic design method
US5079614A (en) * 1990-09-26 1992-01-07 S-Mos Systems, Inc. Gate array architecture with basic cell interleaved gate electrodes
US5162666A (en) 1991-03-15 1992-11-10 Tran Dzung J Transmission gate series multiplexer
JP3144967B2 (ja) 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
JP3072887B2 (ja) * 1995-12-11 2000-08-07 川崎製鉄株式会社 フィールドプログラマブルゲートアレイ
US6097221A (en) * 1995-12-11 2000-08-01 Kawasaki Steel Corporation Semiconductor integrated circuit capable of realizing logic functions
JP3072888B2 (ja) * 1995-12-14 2000-08-07 川崎製鉄株式会社 フィールドプログラマブルゲートアレイ
US5955912A (en) * 1995-10-25 1999-09-21 Texas Instruments Incorporated Multiplexer circuits
KR100439527B1 (ko) * 1997-04-11 2004-07-12 가부시키가이샤 히타치세이사쿠쇼 반도체집적회로
KR100278275B1 (ko) * 1997-06-30 2001-01-15 김영환 저전력-고속스택틱캐스코드회로

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