JP2000151384A5 - - Google Patents

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JP2000151384A5
JP2000151384A5 JP1999313641A JP31364199A JP2000151384A5 JP 2000151384 A5 JP2000151384 A5 JP 2000151384A5 JP 1999313641 A JP1999313641 A JP 1999313641A JP 31364199 A JP31364199 A JP 31364199A JP 2000151384 A5 JP2000151384 A5 JP 2000151384A5
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pfets
driver
nfets
electrically connected
pull
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JP4430175B2 (ja
JP2000151384A (ja
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【特許請求の範囲】
【請求項】
半導体素子の信号パッド（241）を介して信号を駆動する可変インピーダンス出力ドライバ（200）であって、
電気的に並列に接続された複数のｐチャネル電界効果トランジスタ（ＰＦＥＴ）（210）であって、該複数のＰＦＥＴ（211〜219）のそれぞれのソースノードが互いに電気的に接続され、前記複数のＰＦＥＴ（211〜219）のそれぞれのドレインノードが互いに電気的に接続される、前記複数のｐチャネル電界効果トランジスタ（ＰＦＥＴ）（210）と、
電気的に並列に接続された複数のｎチャネル電界効果トランジスタ（ＮＦＥＴ）（220）であって、該複数のＮＦＥＴ（221〜229）のそれぞれのソースノードが互いに電気的に接続され、前記複数のＮＦＥＴ（221〜229）のそれぞれのドレインノードが電気的に接続されており、前記複数のＰＦＥＴ（211〜219）のそれぞれのドレインノードが、前記複数のＮＦＥＴ（221〜229）のそれぞれのソースノードに電気的に接続されて、更に信号パッド（241）に電気的に接続されている、前記複数のｎチャネル電界効果トランジスタ（ＮＦＥＴ）（220）とが含まれており、
前記複数のＰＦＥＴ（211〜219）の第１のＰＦＥＴ（211）が、プルアッププリドライバ回路（232）の出力によって駆動されるゲートノードを備えており、前記複数のＮＦＥＴ（221〜229）の第１のＮＦＥＴ（221）が、プルダウンプリドライバ回路（234）の出力によって駆動されるゲートノードを備えており、残りのＰＦＥＴ及びＮＦＥＴが、それぞれ、制御回路（250）によって生成される較正ワードによって制御されるに従って、前記プルアップ及びプルダウンプリドライバ回路（232,234）によって駆動されるゲートノードを備えている、
ドライバ。
【請求項２】
前記複数のＰＦＥＴ（211〜219）のサイズが可変である請求項１のドライバ。
【請求項３】
前記複数のＰＦＥＴ（211〜219）のサイズは、前記第１のＰＦＥＴ（211）を除いて幅寸法が漸進的に小さくなるようになっている請求項２のドライバ。
【請求項４】
前記複数のＰＦＥＴ（211〜219）のサイズは、前記第１のＰＦＥＴ（211）を除いて幅寸法が漸進的に１／２に変化する請求項２のドライバ。
【請求項５】
前記複数のＮＦＥＴ（221〜229）のサイズが可変である請求項１のドライバ。
【請求項６】
前記複数のＮＦＥＴ（221〜229）のサイズは、前記第１のＮＦＥＴ（221）を除いて幅寸法が漸進的に小さくなるようになっている請求項５のドライバ。
【請求項７】
前記複数のＮＦＥＴ（221〜229）のサイズは、前記第１のＮＦＥＴ（221）を除いて幅寸法が漸進的に１／２に変化する請求項６のドライバ。
【請求項８】
前記信号パッドと、前記複数のＰＦＥＴ（211〜219）のドレインノード及び前記複数のＮＦＥＴ（221〜229）のソースノードの共通接続部との間に、電気的に直列に配置された抵抗器（242）を更に含む請求項１のドライバ。
【請求項９】
半導体素子の信号パッド（241）を介して信号を駆動する可変インピーダンス出力ドライバ（200）であって、
前記信号パッド（241）に対する出力信号を低状態から高状態に駆動するように構成されたプルアッププリドライバ回路（232）と、
前記信号パッド（241）に対する出力信号を高状態から低状態に駆動するように構成されたプルダウンプリドライバ回路（234）と、
前記信号パッド（241）と、前記プルアッププリドライバ回路（232）及び前記プルダウンプリドライバ回路（234）の両方との間に挿入された電界効果トランジスタ（ＦＥＴ）回路網と、
前記ＦＥＴ回路網に入力される複数の出力信号（208a,208b）を有するインピーダンス制御回路（250）とが含まれており、それによって前記インピーダンス制御回路の出力信号（208a,208b）が、前記出力ドライバ（200）の出力インピーダンスを制御可能に変化させる働きをする、
ドライバ。
【請求項１０】
前記ＦＥＴ回路網に、電気的に並列に接続された複数のｐチャネル電界効果トランジスタ（ＦＥＴ）（210）が含まれており、前記複数のＰＦＥＴ（211〜219）のそれぞれのソースノードが、互いに電気的に接続され、前記複数のＰＦＥＴ（211〜219）のそれぞれのドレインノードが、互いに電気的に接続されている請求項９のドライバ。
JP31364199A 1998-11-04 1999-11-04 デジタル制御出力ドライバ及びインピーダンス整合方法 Expired - Fee Related JP4430175B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/186,006 US6118310A (en) 1998-11-04 1998-11-04 Digitally controlled output driver and method for impedance matching
US186006 1998-11-04

Publications (3)

Publication Number Publication Date
JP2000151384A JP2000151384A (ja) 2000-05-30
JP2000151384A5 true JP2000151384A5 (ja) 2007-01-25
JP4430175B2 JP4430175B2 (ja) 2010-03-10

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US (1) US6118310A (ja)
EP (1) EP0999643A1 (ja)
JP (1) JP4430175B2 (ja)

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6366129B1 (en) * 1998-11-10 2002-04-02 Intel Corporation Method and apparatus for buffering an input-output node of an integrated circuit
US6204683B1 (en) * 1999-05-18 2001-03-20 Intel Corporation Apparatus and method for reducing crosstalk in an integrated circuit which includes a signal bus
US6278306B1 (en) 1999-06-07 2001-08-21 Sun Microsystems, Inc. Method for an output driver with improved slew rate control
US6366139B1 (en) 1999-06-07 2002-04-02 Sun Microsystems, Inc. Method for an output driver with improved impedance control
US6281729B1 (en) 1999-06-07 2001-08-28 Sun Microsystems, Inc. Output driver with improved slew rate control
US6339351B1 (en) 1999-06-07 2002-01-15 Sun Microsystems, Inc. Output driver with improved impedance control
US6297677B1 (en) 1999-09-20 2001-10-02 Sun Microsystems, Inc. Method for a dynamic termination logic driver with improved slew rate control
US6316957B1 (en) * 1999-09-20 2001-11-13 Sun Microsystems, Inc. Method for a dynamic termination logic driver with improved impedance control
US6294924B1 (en) 1999-09-20 2001-09-25 Sun Microsystems, Inc. Dynamic termination logic driver with improved slew rate control
US6420913B1 (en) 1999-09-20 2002-07-16 Sun Microsystems, Inc. Dynamic termination logic driver with improved impedance control
US6316956B1 (en) * 1999-10-22 2001-11-13 Motorola, Inc. Multiple redundant reliability enhancement method for integrated circuits and transistors
US6300789B1 (en) * 1999-12-22 2001-10-09 Intel Corporation Dynamic termination for non-symmetric transmission line network topologies
US6347850B1 (en) * 1999-12-23 2002-02-19 Intel Corporation Programmable buffer circuit
US6356105B1 (en) * 2000-06-28 2002-03-12 Intel Corporation Impedance control system for a center tapped termination bus
US6864706B1 (en) * 2000-07-20 2005-03-08 Silicon Graphics, Inc. GTL+Driver
US7222208B1 (en) 2000-08-23 2007-05-22 Intel Corporation Simultaneous bidirectional port with synchronization circuit to synchronize the port with another port
US6424175B1 (en) * 2000-09-11 2002-07-23 Intel Corporation Biased control loop circuit for setting impedance of output driver
US6693450B1 (en) * 2000-09-29 2004-02-17 Intel Corporation Dynamic swing voltage adjustment
KR100391150B1 (ko) * 2000-11-15 2003-07-16 삼성전자주식회사 다단의 상위 코드 선택기를 갖는 반도체 장치의 임피던스콘트롤 출력회로 및 그의 동작방법
KR100410536B1 (ko) * 2001-02-05 2003-12-18 삼성전자주식회사 터미네이션 회로의 임피던스 업데이트 장치 및 방법
US6437610B1 (en) 2001-02-15 2002-08-20 Infineon Technologies Ag High-speed output driver
DE50110188D1 (de) * 2001-02-15 2006-07-27 Infineon Technologies Ag Hochgeschwindigkeitsausgangstreiber
US6522185B2 (en) 2001-02-28 2003-02-18 Agilent Technologies, Inc. Variable delay CMOS circuit with PVT control
US6559690B2 (en) * 2001-03-15 2003-05-06 Micron Technology, Inc. Programmable dual drive strength output buffer with a shared boot circuit
US20020135406A1 (en) * 2001-03-20 2002-09-26 Hossain Km Mozammel Controlled impedance driver receiving a combination binary and thermometer code
US6448811B1 (en) 2001-04-02 2002-09-10 Intel Corporation Integrated circuit current reference
US6522174B2 (en) * 2001-04-16 2003-02-18 Intel Corporation Differential cascode current mode driver
EP1396126A2 (en) 2001-05-21 2004-03-10 Acuid Corporation Limited Method and apparatus for impedance matching in a transmission line
JP2002359548A (ja) * 2001-05-31 2002-12-13 Hitachi Ltd 半導体集積回路
US6791356B2 (en) 2001-06-28 2004-09-14 Intel Corporation Bidirectional port with clock channel used for synchronization
US6636821B2 (en) * 2001-07-03 2003-10-21 International Business Machines Corporation Output driver impedance calibration circuit
US6509757B1 (en) 2001-08-02 2003-01-21 Agilent Technologies, Inc. Binary weighted thermometer code for PVT controlled output drivers
US6798237B1 (en) 2001-08-29 2004-09-28 Altera Corporation On-chip impedance matching circuit
US6529037B1 (en) 2001-09-13 2003-03-04 Intel Corporation Voltage mode bidirectional port with data channel used for synchronization
KR100427037B1 (ko) 2001-09-24 2004-04-14 주식회사 하이닉스반도체 적응적 출력 드라이버를 갖는 반도체 기억장치
US6836144B1 (en) 2001-12-10 2004-12-28 Altera Corporation Programmable series on-chip termination impedance and impedance matching
US6812734B1 (en) * 2001-12-11 2004-11-02 Altera Corporation Programmable termination with DC voltage level control
US7109744B1 (en) 2001-12-11 2006-09-19 Altera Corporation Programmable termination with DC voltage level control
US6781416B1 (en) 2001-12-19 2004-08-24 Rambus Inc. Push-pull output driver
JP3626452B2 (ja) * 2001-12-27 2005-03-09 株式会社東芝 半導体装置
GB0208014D0 (en) * 2002-04-05 2002-05-15 Acuid Corp Ltd Line termination incorporating compensation for device and package parasites
KR100481854B1 (ko) * 2002-07-29 2005-04-11 삼성전자주식회사 온칩 터미네이션기능을 가진 집적회로장치
US7239170B2 (en) * 2003-07-08 2007-07-03 Lsi Corporation Apparatus and methods for improved input/output cells
US6894529B1 (en) 2003-07-09 2005-05-17 Integrated Device Technology, Inc. Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
US6888369B1 (en) 2003-07-17 2005-05-03 Altera Corporation Programmable on-chip differential termination impedance
DE10338077A1 (de) * 2003-08-19 2005-03-17 Infineon Technologies Ag Verfahren und Schaltungsanordnung zum schrittweisen Abgleich der Treiberimpedanz in integrierten Halbleiterschaltungschips
US6859064B1 (en) 2003-08-20 2005-02-22 Altera Corporation Techniques for reducing leakage current in on-chip impedance termination circuits
US6888370B1 (en) 2003-08-20 2005-05-03 Altera Corporation Dynamically adjustable termination impedance control techniques
US6912165B2 (en) * 2003-08-22 2005-06-28 International Business Machines Corporation Method for transparent updates of output driver impedance
KR100500921B1 (ko) * 2003-08-25 2005-07-14 주식회사 하이닉스반도체 데이터 출력드라이버의 임피던스를 조정할 수 있는 반도체메모리 장치
KR100543197B1 (ko) * 2003-08-25 2006-01-20 주식회사 하이닉스반도체 데이터 출력드라이버
TW594187B (en) * 2003-10-21 2004-06-21 Au Optronics Corp Mechanism for preventing ESD damages and LCD panel applying the same
JP4086757B2 (ja) 2003-10-23 2008-05-14 Ｎｅｃエレクトロニクス株式会社 半導体集積回路の入出力インターフェース回路
US7057415B2 (en) * 2003-12-10 2006-06-06 Hewlett-Packard Development Company, L.P. Output buffer compensation control
US6967501B1 (en) 2003-12-18 2005-11-22 Integrated Device Technology, Inc. Impedance-matched output driver circuits having enhanced predriver control
US7248636B2 (en) * 2004-04-20 2007-07-24 Hewlett-Packard Development Company, L.P. Systems and methods for adjusting an output driver
US7005886B2 (en) 2004-04-30 2006-02-28 Agilent Technologies, Inc. Tristateable CMOS driver with controlled slew rate for integrated circuit I/O pads
US7088129B2 (en) 2004-04-30 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
KR100699828B1 (ko) * 2004-10-11 2007-03-27 삼성전자주식회사 임피던스 교정 회로와 이를 포함하는 집적 회로 및 이를이용한 출력 드라이버의 임피던스 조절 방법
KR100670672B1 (ko) * 2004-11-02 2007-01-17 주식회사 하이닉스반도체 반도체메모리소자
US7221193B1 (en) 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
US7218155B1 (en) 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7327167B2 (en) * 2005-04-28 2008-02-05 Silicon Graphics, Inc. Anticipatory programmable interface pre-driver
KR100702838B1 (ko) * 2005-05-09 2007-04-03 삼성전자주식회사 반도체 장치에서의 임피던스 콘트롤러블 출력 구동회로 및그에 따른 임피던스 콘트롤 방법
KR100655083B1 (ko) * 2005-05-11 2006-12-08 삼성전자주식회사 반도체 장치에서의 임피던스 콘트롤 회로 및 임피던스콘트롤 방법
JP2006352272A (ja) * 2005-06-13 2006-12-28 Renesas Technology Corp 半導体集積回路装置
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
CN1980057B (zh) * 2005-12-01 2011-10-26 瑞昱半导体股份有限公司 输出驱动电路的阻抗匹配装置
TWI323467B (en) * 2005-12-27 2010-04-11 Hynix Semiconductor Inc On-die termination circuit for semiconductor memory apparatus
US7391229B1 (en) 2006-02-18 2008-06-24 Altera Corporation Techniques for serially transmitting on-chip termination control signals
US7420386B2 (en) 2006-04-06 2008-09-02 Altera Corporation Techniques for providing flexible on-chip termination control on integrated circuits
RU2296363C1 (ru) * 2006-04-27 2007-03-27 Общество с ограниченной ответственностью "АСТРОМА" Способ и средство защиты программного обеспечения от несанкционированного использования
JP4996880B2 (ja) * 2006-06-08 2012-08-08 日本オプネクスト株式会社 双方向通信システムおよび校正器
US7417452B1 (en) * 2006-08-05 2008-08-26 Altera Corporation Techniques for providing adjustable on-chip termination impedance
US7423450B2 (en) * 2006-08-22 2008-09-09 Altera Corporation Techniques for providing calibrated on-chip termination impedance
US7656209B2 (en) * 2006-11-03 2010-02-02 Micron Technology, Inc. Output slew rate control
US7646229B2 (en) * 2006-11-03 2010-01-12 Micron Technology, Inc. Method of output slew rate control
US7902875B2 (en) * 2006-11-03 2011-03-08 Micron Technology, Inc. Output slew rate control
US7372295B1 (en) 2006-12-22 2008-05-13 Altera Corporation Techniques for calibrating on-chip termination impedances
US7443193B1 (en) 2006-12-30 2008-10-28 Altera Corporation Techniques for providing calibrated parallel on-chip termination impedance
TW200910373A (en) 2007-06-08 2009-03-01 Mosaid Technologies Inc Dynamic impedance control for input/output buffers
KR100878310B1 (ko) * 2007-06-11 2009-01-14 주식회사 하이닉스반도체 데이터 출력 드라이버 회로
TW200912591A (en) * 2007-09-07 2009-03-16 Realtek Semiconductor Corp Calibration device and method for chip output current
US7586325B1 (en) * 2007-12-03 2009-09-08 Lattice Semiconductor Corporation Integrated circuit having independent voltage and process/temperature control
US20090175378A1 (en) * 2008-01-08 2009-07-09 Robert Bogdan Staszewski System and Method for Impedance Mismatch Compensation in Digital Communications Systems
US20090184395A1 (en) * 2008-01-23 2009-07-23 Che-Yuan Jao Input/output (i/o) buffer
JP2009231891A (ja) 2008-03-19 2009-10-08 Nec Electronics Corp 半導体装置
US7443194B1 (en) 2008-04-24 2008-10-28 International Business Machines Corporation I/O driver for integrated circuit with output impedance control
US20110019760A1 (en) * 2009-07-21 2011-01-27 Rambus Inc. Methods and Systems for Reducing Supply and Termination Noise
US8471602B2 (en) 2010-04-30 2013-06-25 SK Hynix Inc. Output driver and semiconductor apparatus having the same
US8766663B2 (en) 2012-06-18 2014-07-01 International Business Machines Corporation Implementing linearly weighted thermal coded I/O driver output stage calibration
US8957715B2 (en) 2012-10-17 2015-02-17 Allegro Microsystems, Llc Output driver having improved electromagnetic compatibility (EMC) and associated methods
US9484916B1 (en) 2015-03-16 2016-11-01 Altera Corporation Adaptive on-chip termination circuitry
KR20160148112A (ko) * 2015-06-15 2016-12-26 에스케이하이닉스 주식회사 출력 드라이버 및 이를 이용하는 반도체 장치 및 시스템
US9928194B2 (en) 2015-11-30 2018-03-27 Allegro Microsystems, Llc Non-linear transmit biasing for a serial bus transmitter
US9621140B1 (en) 2016-01-15 2017-04-11 Allegro Microsystems, Llc Electronic circuit for driving an output current signal and method of driving the output current signal from the electronic circuit to achieve an altered transition of the output current signal
US9793888B2 (en) * 2016-03-14 2017-10-17 Altera Corporation Techniques for enabling and disabling transistor legs in an output driver circuit
WO2023250313A2 (en) * 2022-06-22 2023-12-28 Rambus Inc. A high-speed, low-power, and area-efficient transmitter

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719369A (en) * 1985-08-14 1988-01-12 Hitachi, Ltd. Output circuit having transistor monitor for matching output impedance to load impedance
US5134311A (en) * 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
US5162672A (en) * 1990-12-24 1992-11-10 Motorola, Inc. Data processor having an output terminal with selectable output impedances
US5306965A (en) * 1992-07-01 1994-04-26 Hewlett-Packard Co. Process compensating variable impedence I/O driver with feedback
FR2709217B1 (fr) * 1993-08-19 1995-09-15 Bull Sa Procédé et dispositif d'adaptation d'impédance pour un émetteur et/ou récepteur, circuit intégré et système de transmission les mettant en Óoeuvre.
US5602494A (en) * 1995-03-09 1997-02-11 Honeywell Inc. Bi-directional programmable I/O cell
US5581197A (en) * 1995-05-31 1996-12-03 Hewlett-Packard Co. Method of programming a desired source resistance for a driver stage

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