ITMI920178A1 - Dispositivo a semiconduttore sigillato con resina da stampaggio e procedimento per la fabbricazione del medesimo - Google Patents

Dispositivo a semiconduttore sigillato con resina da stampaggio e procedimento per la fabbricazione del medesimo

Info

Publication number
ITMI920178A1
ITMI920178A1 IT000178A ITMI920178A ITMI920178A1 IT MI920178 A1 ITMI920178 A1 IT MI920178A1 IT 000178 A IT000178 A IT 000178A IT MI920178 A ITMI920178 A IT MI920178A IT MI920178 A1 ITMI920178 A1 IT MI920178A1
Authority
IT
Italy
Prior art keywords
manufacture
same
molding resin
sealed device
semiconductor sealed
Prior art date
Application number
IT000178A
Other languages
English (en)
Inventor
Etsushi Adachi
Hiroshi Adachi
Hirozoh Kanegae
Hiroshi Mochizuki
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI920178A0 publication Critical patent/ITMI920178A0/it
Publication of ITMI920178A1 publication Critical patent/ITMI920178A1/it
Application granted granted Critical
Publication of IT1258835B publication Critical patent/IT1258835B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/296—Organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/01—Chemical elements
    • H01L2924/01092—Uranium [U]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Silicon Polymers (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
ITMI920178A 1991-01-31 1992-01-30 Dispositivo a semiconduttore sigillato con resina da stampaggio e procedimento per la fabbricazione del medesimo IT1258835B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3010908A JPH04261049A (ja) 1991-01-31 1991-01-31 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
ITMI920178A0 ITMI920178A0 (it) 1992-01-30
ITMI920178A1 true ITMI920178A1 (it) 1993-07-30
IT1258835B IT1258835B (it) 1996-02-29

Family

ID=11763389

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI920178A IT1258835B (it) 1991-01-31 1992-01-30 Dispositivo a semiconduttore sigillato con resina da stampaggio e procedimento per la fabbricazione del medesimo

Country Status (5)

Country Link
US (1) US5180691A (it)
JP (1) JPH04261049A (it)
KR (1) KR950006431B1 (it)
DE (1) DE4202290C2 (it)
IT (1) IT1258835B (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3383329B2 (ja) * 1992-08-27 2003-03-04 株式会社東芝 半導体装置の製造方法
JP2923408B2 (ja) * 1992-12-21 1999-07-26 三菱電機株式会社 高純度シリコーンラダーポリマーの製造方法
JPH0799271A (ja) * 1993-06-16 1995-04-11 Mitsubishi Electric Corp 半導体装置
JP3214186B2 (ja) * 1993-10-07 2001-10-02 三菱電機株式会社 半導体装置の製造方法
DE4432294A1 (de) * 1994-09-12 1996-03-14 Telefunken Microelectron Verfahren zur Reduzierung der Oberflächenrekombinationsgeschwindigkeit in Silizium
US5600151A (en) * 1995-02-13 1997-02-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor device comprising a semiconductor substrate, an element formed thereon, and a stress-buffering film made of a silicone ladder resin
KR100216991B1 (ko) * 1996-09-11 1999-09-01 윤종용 접착층이 형성된 리드 프레임
TW480636B (en) * 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
EP0890981B1 (en) * 1997-07-11 2003-02-12 Robert Bosch Gmbh Enhanced underfill adhesion of flip chips
US5869219A (en) * 1997-11-05 1999-02-09 Taiwan Semiconductor Manufacturing Co. Ltd. Method for depositing a polyimide film
DE19827593A1 (de) * 1998-06-20 1999-12-23 Abb Patent Gmbh Verfahren zur Ertüchtigung von Freileitungsisolatoren
US6110815A (en) * 1998-06-23 2000-08-29 Lsi Logic Corporation Electroplating fixture for high density substrates
US6599995B2 (en) * 2001-05-01 2003-07-29 Korea Institute Of Science And Technology Polyalkylaromaticsilsesquioxane and preparation method thereof
US7091131B2 (en) * 2002-03-21 2006-08-15 Micron Technology, Inc. Method of forming integrated circuit structures in silicone ladder polymer
US20040102022A1 (en) * 2002-11-22 2004-05-27 Tongbi Jiang Methods of fabricating integrated circuitry

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Publication number Priority date Publication date Assignee Title
NL241488A (it) * 1958-07-21 1900-01-01
US3792012A (en) * 1972-03-17 1974-02-12 Gen Electric Silicone resin useful in molding compositions
JPS5336997B2 (it) * 1973-10-12 1978-10-05
DE2548060C2 (de) * 1975-10-27 1984-06-20 Siemens AG, 1000 Berlin und 8000 München Halbleitervorrichtung und Verfahren zu ihrer Herstellung
JPS56118334A (en) * 1980-02-22 1981-09-17 Fujitsu Ltd Semiconductor device
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device
JPH0783075B2 (ja) * 1986-03-14 1995-09-06 三菱電機株式会社 半導体装置の製造方法
JPS63104450A (ja) * 1986-10-22 1988-05-09 Hitachi Ltd 保護膜の窓開法
JPS63213347A (ja) * 1987-02-27 1988-09-06 Mitsubishi Electric Corp 半導体装置
JPH0192224A (ja) * 1987-04-20 1989-04-11 Mitsubishi Electric Corp 高純度フェニルシリコーンラダーポリマーの製造法
JPS63269554A (ja) * 1987-04-27 1988-11-07 Mitsubishi Electric Corp 半導体装置
US4827326A (en) * 1987-11-02 1989-05-02 Motorola, Inc. Integrated circuit having polyimide/metal passivation layer and method of manufacture using metal lift-off
JP2503565B2 (ja) * 1988-01-21 1996-06-05 三菱電機株式会社 半導体装置の製造方法
JP2597396B2 (ja) * 1988-12-21 1997-04-02 ローム株式会社 シリコーンゴム膜のパターン形成方法
US5081202A (en) * 1989-11-17 1992-01-14 Mitsubishi Denki Kabushiki Kaisha High purity phenyl silicone ladder polymer and method for producing the same
JP2613128B2 (ja) * 1990-10-01 1997-05-21 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
DE4202290C2 (de) 2001-07-19
JPH04261049A (ja) 1992-09-17
DE4202290A1 (de) 1992-08-13
IT1258835B (it) 1996-02-29
KR920015495A (ko) 1992-08-27
US5180691A (en) 1993-01-19
ITMI920178A0 (it) 1992-01-30
KR950006431B1 (ko) 1995-06-15

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