ITMI20020812A1 - Circuito e procedimento di immissione di dati per dispositivi di memoria a semiconduttore sincrona - Google Patents

Circuito e procedimento di immissione di dati per dispositivi di memoria a semiconduttore sincrona

Info

Publication number
ITMI20020812A1
ITMI20020812A1 IT2002MI000812A ITMI20020812A ITMI20020812A1 IT MI20020812 A1 ITMI20020812 A1 IT MI20020812A1 IT 2002MI000812 A IT2002MI000812 A IT 2002MI000812A IT MI20020812 A ITMI20020812 A IT MI20020812A IT MI20020812 A1 ITMI20020812 A1 IT MI20020812A1
Authority
IT
Italy
Prior art keywords
circuit
semiconductor memory
data input
memory devices
synchronous semiconductor
Prior art date
Application number
IT2002MI000812A
Other languages
English (en)
Inventor
Jung-Bae Lee
One-Gyun La
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR10-2001-0044065A external-priority patent/KR100403632B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI20020812A0 publication Critical patent/ITMI20020812A0/it
Publication of ITMI20020812A1 publication Critical patent/ITMI20020812A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
IT2002MI000812A 2001-05-03 2002-04-17 Circuito e procedimento di immissione di dati per dispositivi di memoria a semiconduttore sincrona ITMI20020812A1 (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20010024044 2001-05-03
KR10-2001-0044065A KR100403632B1 (ko) 2001-05-03 2001-07-21 동기형 반도체 메모리 장치의 데이터 입력회로 및 데이터입력 방법

Publications (2)

Publication Number Publication Date
ITMI20020812A0 ITMI20020812A0 (it) 2002-04-17
ITMI20020812A1 true ITMI20020812A1 (it) 2003-10-17

Family

ID=26639043

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2002MI000812A ITMI20020812A1 (it) 2001-05-03 2002-04-17 Circuito e procedimento di immissione di dati per dispositivi di memoria a semiconduttore sincrona

Country Status (5)

Country Link
US (2) US6728162B2 (it)
JP (1) JP4249941B2 (it)
DE (1) DE10220559A1 (it)
IT (1) ITMI20020812A1 (it)
TW (1) TW552585B (it)

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KR101290764B1 (ko) * 2007-10-24 2013-07-30 삼성전자주식회사 고속동작에 적합한 입력 회로를 갖는 반도체 메모리 장치
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KR102087437B1 (ko) * 2013-06-17 2020-03-10 에스케이하이닉스 주식회사 수신장치를 포함하는 반도체시스템
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Also Published As

Publication number Publication date
JP4249941B2 (ja) 2009-04-08
ITMI20020812A0 (it) 2002-04-17
US6728162B2 (en) 2004-04-27
US7016237B2 (en) 2006-03-21
TW552585B (en) 2003-09-11
JP2002352583A (ja) 2002-12-06
DE10220559A1 (de) 2002-11-14
US20020122348A1 (en) 2002-09-05
US20050024984A1 (en) 2005-02-03

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