IT1272543B - Circuito amplificatore perfezionato e dispositivo di memoria a semiconduttore impiegando lo stesso - Google Patents

Circuito amplificatore perfezionato e dispositivo di memoria a semiconduttore impiegando lo stesso

Info

Publication number
IT1272543B
IT1272543B ITMI931871A ITMI931871A IT1272543B IT 1272543 B IT1272543 B IT 1272543B IT MI931871 A ITMI931871 A IT MI931871A IT MI931871 A ITMI931871 A IT MI931871A IT 1272543 B IT1272543 B IT 1272543B
Authority
IT
Italy
Prior art keywords
amplifier circuit
transistor
same
memory device
semiconductor memory
Prior art date
Application number
ITMI931871A
Other languages
English (en)
Inventor
Kenichi Okumura
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI931871A0 publication Critical patent/ITMI931871A0/it
Publication of ITMI931871A1 publication Critical patent/ITMI931871A1/it
Application granted granted Critical
Publication of IT1272543B publication Critical patent/IT1272543B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Amplifiers (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)

Abstract

Si fornisce un circuito amplificatore perfezionato sensibile a due segnali di ingresso complementari VI,/VI per fornire un segnale di uscita amplificato VO. Nel circuito amplificatore, un transistor PMOS (21) ed un transistor NMOS (4) resi conduttivi alternativamente in risposta al segnale di ingresso VI sono collegati in serie fra un potenziale Vcc di alimentazione di energia ed un potenziale di terra. Quando è applicato il segnale di ingresso VI ad un livello alto, il transistor (4) viene attivato, mentre viene disattivato il transistor (21). Poiché viene impedita la corrente passante che scorre dal potenziale di alimentazione di energia verso il potenziale di terra, possono essere perfezionati il consumo di energia e la velocità di funzionamento.
ITMI931871A 1992-09-01 1993-08-31 Circuito amplificatore perfezionato e dispositivo di memoria a semiconduttore impiegando lo stesso IT1272543B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4233356A JPH0685564A (ja) 1992-09-01 1992-09-01 増幅器回路

Publications (3)

Publication Number Publication Date
ITMI931871A0 ITMI931871A0 (it) 1993-08-31
ITMI931871A1 ITMI931871A1 (it) 1995-03-03
IT1272543B true IT1272543B (it) 1997-06-23

Family

ID=16953871

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI931871A IT1272543B (it) 1992-09-01 1993-08-31 Circuito amplificatore perfezionato e dispositivo di memoria a semiconduttore impiegando lo stesso

Country Status (5)

Country Link
US (1) US5373473A (it)
JP (1) JPH0685564A (it)
KR (1) KR0129790B1 (it)
DE (1) DE4324649C2 (it)
IT (1) IT1272543B (it)

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US5508643A (en) * 1994-11-16 1996-04-16 Intel Corporation Bitline level insensitive sense amplifier
JPH08190799A (ja) * 1995-01-09 1996-07-23 Mitsubishi Denki Semiconductor Software Kk センスアンプ回路
DE19547778C1 (de) * 1995-12-20 1997-05-07 Texas Instruments Deutschland CMOS-Treiberschaltung
KR100508023B1 (ko) * 1998-04-03 2005-11-30 삼성전자주식회사 엘디디형 다결정 규소 박막 트랜지스터 및 그 제조 방법
JP4531150B2 (ja) * 1998-11-09 2010-08-25 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
DE69929579D1 (de) * 1999-06-30 2006-04-13 St Microelectronics Nv LVDS Empfänger unter Verwendung von differentiellen Verstärkern
US6396329B1 (en) 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US7124221B1 (en) 1999-10-19 2006-10-17 Rambus Inc. Low latency multi-level communication interface
US7269212B1 (en) 2000-09-05 2007-09-11 Rambus Inc. Low-latency equalization in multi-level, multi-line communication systems
US7161513B2 (en) 1999-10-19 2007-01-09 Rambus Inc. Apparatus and method for improving resolution of a current mode driver
US7362800B1 (en) 2002-07-12 2008-04-22 Rambus Inc. Auto-configured equalizer
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration
US6944079B2 (en) * 2003-12-31 2005-09-13 Micron Technology, Inc. Digital switching technique for detecting data
US8283946B2 (en) 2010-04-15 2012-10-09 Micron Technology, Inc. Signaling systems, preamplifiers, memory devices and methods

Family Cites Families (19)

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Publication number Priority date Publication date Assignee Title
JPS5592008A (en) * 1978-12-29 1980-07-12 Fujitsu Ltd Cmos differential amplifier
JPS57198594A (en) * 1981-06-01 1982-12-06 Hitachi Ltd Semiconductor storage device
JPS5979486A (ja) * 1982-10-27 1984-05-08 Nec Corp センスアンプ
JPS59175089A (ja) * 1983-03-25 1984-10-03 Oki Electric Ind Co Ltd Ｍｏｓセンスアンプ回路
JPS6247897A (ja) * 1985-08-28 1987-03-02 Sony Corp 読み出し増幅器
JPH0743938B2 (ja) * 1985-10-09 1995-05-15 日本電気株式会社 差動増幅器
JPH0736272B2 (ja) * 1986-12-24 1995-04-19 株式会社日立製作所 半導体集積回路装置
JPS63178607A (ja) * 1987-01-19 1988-07-22 Mitsubishi Electric Corp 誤差増幅器
JPS63253706A (ja) * 1987-04-09 1988-10-20 Nec Corp 差動回路
JPS6462907A (en) * 1987-09-02 1989-03-09 Nec Corp Differential amplifier circuit
US4891792A (en) * 1987-09-04 1990-01-02 Hitachi, Ltd. Static type semiconductor memory with multi-stage sense amplifier
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
US5126974A (en) * 1989-01-20 1992-06-30 Hitachi, Ltd. Sense amplifier for a memory device
JP2647527B2 (ja) * 1990-02-21 1997-08-27 シャープ株式会社 センス増幅回路
JPH0482089A (ja) * 1990-07-23 1992-03-16 Nec Corp センスアンプ回路
JPH04163795A (ja) * 1990-10-29 1992-06-09 Nec Corp カレント・ミラー型感知増幅器
JPH04214297A (ja) * 1990-12-13 1992-08-05 Mitsubishi Electric Corp 増幅回路
JP2745251B2 (ja) * 1991-06-12 1998-04-28 三菱電機株式会社 半導体メモリ装置
US5237533A (en) * 1991-12-20 1993-08-17 National Semiconductor Corporation High speed switched sense amplifier

Also Published As

Publication number Publication date
DE4324649A1 (de) 1994-03-10
KR940008227A (ko) 1994-04-29
JPH0685564A (ja) 1994-03-25
DE4324649C2 (de) 1994-11-10
ITMI931871A0 (it) 1993-08-31
US5373473A (en) 1994-12-13
KR0129790B1 (ko) 1998-10-01
ITMI931871A1 (it) 1995-03-03

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960828