GB2505594B - Microelectronic substrate for alternate package functionality - Google Patents

Microelectronic substrate for alternate package functionality

Info

Publication number
GB2505594B
GB2505594B GB1321487.9A GB201321487A GB2505594B GB 2505594 B GB2505594 B GB 2505594B GB 201321487 A GB201321487 A GB 201321487A GB 2505594 B GB2505594 B GB 2505594B
Authority
GB
United Kingdom
Prior art keywords
microelectronic substrate
alternate package
package functionality
functionality
alternate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB1321487.9A
Other languages
English (en)
Other versions
GB2505594A (en
GB201321487D0 (en
Inventor
Md Altaf Hossain
Cliff C Lee
David W Browning
Itai M Pines
Brian P Kelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB201321487D0 publication Critical patent/GB201321487D0/en
Publication of GB2505594A publication Critical patent/GB2505594A/en
Application granted granted Critical
Publication of GB2505594B publication Critical patent/GB2505594B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Combinations Of Printed Boards (AREA)
  • Semiconductor Memories (AREA)
GB1321487.9A 2011-06-06 2012-06-04 Microelectronic substrate for alternate package functionality Expired - Fee Related GB2505594B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/153,608 US8674235B2 (en) 2011-06-06 2011-06-06 Microelectronic substrate for alternate package functionality
PCT/US2012/040677 WO2012170328A2 (en) 2011-06-06 2012-06-04 Microelectronic substrate for alternate package functionality

Publications (3)

Publication Number Publication Date
GB201321487D0 GB201321487D0 (en) 2014-01-22
GB2505594A GB2505594A (en) 2014-03-05
GB2505594B true GB2505594B (en) 2015-11-25

Family

ID=47260798

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1321487.9A Expired - Fee Related GB2505594B (en) 2011-06-06 2012-06-04 Microelectronic substrate for alternate package functionality

Country Status (8)

Country Link
US (2) US8674235B2 (ko)
JP (2) JP5940653B2 (ko)
KR (1) KR101555773B1 (ko)
CN (2) CN103597594B (ko)
DE (1) DE112012002370T5 (ko)
GB (1) GB2505594B (ko)
TW (1) TWI544600B (ko)
WO (1) WO2012170328A2 (ko)

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US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
US9420707B2 (en) 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
US8674235B2 (en) 2011-06-06 2014-03-18 Intel Corporation Microelectronic substrate for alternate package functionality
WO2013133827A1 (en) * 2012-03-07 2013-09-12 Intel Corporation Glass clad microelectronic substrate
WO2014190005A1 (en) * 2013-05-22 2014-11-27 Transient Electronics, Inc. Controlled transformation of non-transient electronics
US9204543B2 (en) * 2013-12-03 2015-12-01 Infineon Technologies Ag Integrated IC package
US9859896B1 (en) * 2015-09-11 2018-01-02 Xilinx, Inc. Distributed multi-die routing in a multi-chip module
US10522949B1 (en) * 2018-08-08 2019-12-31 Qualcomm Incorporated Optimized pin pattern for high speed input/output
US11585102B2 (en) 2018-11-07 2023-02-21 Viconic Sporting Llc Load distribution and absorption underpayment system
US10982451B2 (en) 2018-11-07 2021-04-20 Viconic Sporting Llc Progressive stage load distribution and absorption underlayment system
US20190115293A1 (en) * 2018-12-12 2019-04-18 Intel Corporation Multiple ball grid array (bga) configurations for a single integrated circuit (ic) package
US20220189880A1 (en) * 2020-12-16 2022-06-16 Srinivas V. Pietambaram Microelectronic structures including glass cores

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JPH09298217A (ja) * 1996-05-07 1997-11-18 Hitachi Ltd 半導体装置の製造方法、半導体装置および電子装置
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
JP2003188508A (ja) * 2001-12-18 2003-07-04 Toshiba Corp プリント配線板、面実装形回路部品および回路モジュール
KR100648040B1 (ko) * 2005-11-25 2006-11-23 삼성전자주식회사 다수의 금속 랜드를 가지는 인터포저 기판, 및 이로부터제작되는 인터포저를 포함하는 적층 칩 패키지
US20080271914A1 (en) * 2005-04-18 2008-11-06 Kabushiki Kaisha Toshiba Printed wiring board and information processing apparatus
KR20090105661A (ko) * 2008-04-03 2009-10-07 삼성전기주식회사 다층 인쇄회로기판 및 그 제조방법

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Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631807A (en) * 1995-01-20 1997-05-20 Minnesota Mining And Manufacturing Company Electronic circuit structure with aperture suspended component
JPH09298217A (ja) * 1996-05-07 1997-11-18 Hitachi Ltd 半導体装置の製造方法、半導体装置および電子装置
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
JP2003188508A (ja) * 2001-12-18 2003-07-04 Toshiba Corp プリント配線板、面実装形回路部品および回路モジュール
US20080271914A1 (en) * 2005-04-18 2008-11-06 Kabushiki Kaisha Toshiba Printed wiring board and information processing apparatus
KR100648040B1 (ko) * 2005-11-25 2006-11-23 삼성전자주식회사 다수의 금속 랜드를 가지는 인터포저 기판, 및 이로부터제작되는 인터포저를 포함하는 적층 칩 패키지
KR20090105661A (ko) * 2008-04-03 2009-10-07 삼성전기주식회사 다층 인쇄회로기판 및 그 제조방법

Also Published As

Publication number Publication date
JP5940653B2 (ja) 2016-06-29
WO2012170328A3 (en) 2013-04-25
GB2505594A (en) 2014-03-05
CN103597594B (zh) 2016-08-17
KR20140021032A (ko) 2014-02-19
KR101555773B1 (ko) 2015-09-25
GB201321487D0 (en) 2014-01-22
TWI544600B (zh) 2016-08-01
TW201308561A (zh) 2013-02-16
CN103597594A (zh) 2014-02-19
US20140133075A1 (en) 2014-05-15
JP2016154265A (ja) 2016-08-25
DE112012002370T5 (de) 2014-03-06
CN106057769B (zh) 2018-11-16
US20120305303A1 (en) 2012-12-06
WO2012170328A2 (en) 2012-12-13
JP6174195B2 (ja) 2017-08-02
JP2014517532A (ja) 2014-07-17
US9961769B2 (en) 2018-05-01
CN106057769A (zh) 2016-10-26
US8674235B2 (en) 2014-03-18

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20180604