GB2019091A - Semiconductor store - Google Patents

Semiconductor store

Info

Publication number
GB2019091A
GB2019091A GB7912246A GB7912246A GB2019091A GB 2019091 A GB2019091 A GB 2019091A GB 7912246 A GB7912246 A GB 7912246A GB 7912246 A GB7912246 A GB 7912246A GB 2019091 A GB2019091 A GB 2019091A
Authority
GB
United Kingdom
Prior art keywords
paths
silicide
polysilicon
diffused
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7912246A
Other versions
GB2019091B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB2019091A publication Critical patent/GB2019091A/en
Application granted granted Critical
Publication of GB2019091B publication Critical patent/GB2019091B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a semiconductor store comprising a plurality of storage cells consisting of an MOS selector transistor (AT) and a storage capacitor (CS) connected thereto, and drive lines (BL, WL) for operating the cells. For production reasons, it is desirable to use polysilicon paths (PS) or diffused paths (D) as the drive lines, and in order to increase the conductivity of the lines and thus the transit times, in accordance with the invention, polysilicon paths are provided with an outer layer of a metal silicide (SZ), or in the case of diffused paths, the diffused path zone (D) is covered with a polysilicon layer (PS) having an outer layer of silicide (SZ). The silicide layer may be formed by depositing a suitable metal on the surface of the polysilicon and heating to form the silicide. <IMAGE>
GB7912246A 1978-04-11 1979-04-06 Semiconductor store Expired GB2019091B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2815605A DE2815605C3 (en) 1978-04-11 1978-04-11 Semiconductor memory with control lines of high conductivity

Publications (2)

Publication Number Publication Date
GB2019091A true GB2019091A (en) 1979-10-24
GB2019091B GB2019091B (en) 1982-07-07

Family

ID=6036700

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7912246A Expired GB2019091B (en) 1978-04-11 1979-04-06 Semiconductor store

Country Status (3)

Country Link
DE (1) DE2815605C3 (en)
FR (1) FR2423030A1 (en)
GB (1) GB2019091B (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043451A2 (en) * 1980-06-30 1982-01-13 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
EP0046011A2 (en) * 1980-07-18 1982-02-17 Fujitsu Limited Semiconductor memory device
FR2494042A1 (en) * 1980-11-07 1982-05-14 Hitachi Ltd SEMICONDUCTOR DEVICES AND METHOD FOR MANUFACTURING SAME
EP0053672A2 (en) * 1980-12-08 1982-06-16 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique
EP0054129A2 (en) * 1980-12-17 1982-06-23 International Business Machines Corporation Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor
EP0062417A2 (en) * 1981-03-25 1982-10-13 Kabushiki Kaisha Toshiba Semiconductor device including a transistor and a capacitor and method for manufacturing it
FR2506989A1 (en) * 1981-06-12 1982-12-03 Hitachi Ltd Semiconductor memory - contg. network of memory cells, each having capacitor and IGFET formed in single semiconductor
EP0078501A2 (en) * 1981-10-28 1983-05-11 Hitachi, Ltd. Transistor-like semiconductor device and method of producing the same
GB2139418A (en) * 1983-05-05 1984-11-07 Standard Telephones Cables Ltd Semiconductor devices and conductors therefor
EP0147247A2 (en) * 1983-12-22 1985-07-03 Monolithic Memories, Inc. Method for forming hillock suppression layer in dual metal layer processing and structure formed thereby
GB2151847A (en) * 1983-12-23 1985-07-24 Hitachi Ltd Semiconductor device with metal silicide layer and fabrication process thereof.
EP0166964A1 (en) * 1984-06-04 1986-01-08 International Business Machines Corporation A double level polysilicon semiconductor structure
US4604641A (en) * 1981-11-30 1986-08-05 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US4612565A (en) * 1981-05-27 1986-09-16 Hitachi, Ltd. Semiconductor memory device
US4890148A (en) * 1984-08-31 1989-12-26 Hitachi, Ltd. Semiconductor memory cell device with thick insulative layer
DE4024318A1 (en) * 1989-08-11 1991-02-14 Ricoh Kk Semiconductor read-only memory with higher density - uses common contacts to word and bit-lines and source diffusion, reduces series resistance with metal- or silicide-layers
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
DE2926874A1 (en) * 1979-07-03 1981-01-22 Siemens Ag METHOD FOR PRODUCING LOW-RESISTANT, DIFFUSED AREAS IN SILICON GATE TECHNOLOGY
DE3250096C2 (en) * 1981-05-27 1997-09-11 Hitachi Ltd Semiconductor dynamic random access memory
DE3304651A1 (en) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München DYNAMIC SEMICONDUCTOR MEMORY CELL WITH OPTIONAL ACCESS (DRAM) AND METHOD FOR THEIR PRODUCTION

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2164745C3 (en) * 1971-12-27 1981-07-30 geb. Avvakumova Evdokija Kirillovna Moskva Šergold Semiconductor diode matrix
US4003036A (en) * 1975-10-23 1977-01-11 American Micro-Systems, Inc. Single IGFET memory cell with buried storage element

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0043451A2 (en) * 1980-06-30 1982-01-13 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
EP0043451A3 (en) * 1980-06-30 1984-07-25 International Business Machines Corporation Process for selectively forming refractory metal silicide layers on semiconductor devices
EP0046011A3 (en) * 1980-07-18 1983-08-24 Fujitsu Limited Semiconductor memory device
EP0046011A2 (en) * 1980-07-18 1982-02-17 Fujitsu Limited Semiconductor memory device
FR2494042A1 (en) * 1980-11-07 1982-05-14 Hitachi Ltd SEMICONDUCTOR DEVICES AND METHOD FOR MANUFACTURING SAME
EP0053672A2 (en) * 1980-12-08 1982-06-16 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique
EP0053672A3 (en) * 1980-12-08 1983-10-05 Siemens Aktiengesellschaft Method of producing a one-transistor memory cell employing the double silicon layer technique
EP0054129A2 (en) * 1980-12-17 1982-06-23 International Business Machines Corporation Method for forming a conductor line in an integrated semiconductor memory and an integrated semiconductor memory with cells including a capacitor and a field effect transistor
EP0054129A3 (en) * 1980-12-17 1983-08-24 International Business Machines Corporation Method of making a bit line in a ram structure and ram with such bit line
EP0062417A2 (en) * 1981-03-25 1982-10-13 Kabushiki Kaisha Toshiba Semiconductor device including a transistor and a capacitor and method for manufacturing it
US4732872A (en) * 1981-03-25 1988-03-22 Tokyo Shibaura Denki Kabushiki Kaisha Method for making a bipolar transistor and capacitors using doped polycrystalline silicon or metal silicide
EP0062417A3 (en) * 1981-03-25 1983-08-24 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device including a transistor and a capacitor and method for manufacturing it
US4612565A (en) * 1981-05-27 1986-09-16 Hitachi, Ltd. Semiconductor memory device
FR2506989A1 (en) * 1981-06-12 1982-12-03 Hitachi Ltd Semiconductor memory - contg. network of memory cells, each having capacitor and IGFET formed in single semiconductor
EP0078501A3 (en) * 1981-10-28 1986-06-04 Hitachi, Ltd. Transistor-like semiconductor device and method of producing the same
EP0078501A2 (en) * 1981-10-28 1983-05-11 Hitachi, Ltd. Transistor-like semiconductor device and method of producing the same
US4604641A (en) * 1981-11-30 1986-08-05 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
GB2139418A (en) * 1983-05-05 1984-11-07 Standard Telephones Cables Ltd Semiconductor devices and conductors therefor
EP0147247A2 (en) * 1983-12-22 1985-07-03 Monolithic Memories, Inc. Method for forming hillock suppression layer in dual metal layer processing and structure formed thereby
EP0147247A3 (en) * 1983-12-22 1986-07-16 Monolithic Memories, Inc. Method for forming hillock suppression layer in dual metal layer processing and structure formed thereby
GB2151847A (en) * 1983-12-23 1985-07-24 Hitachi Ltd Semiconductor device with metal silicide layer and fabrication process thereof.
EP0166964A1 (en) * 1984-06-04 1986-01-08 International Business Machines Corporation A double level polysilicon semiconductor structure
US4890148A (en) * 1984-08-31 1989-12-26 Hitachi, Ltd. Semiconductor memory cell device with thick insulative layer
DE4024318A1 (en) * 1989-08-11 1991-02-14 Ricoh Kk Semiconductor read-only memory with higher density - uses common contacts to word and bit-lines and source diffusion, reduces series resistance with metal- or silicide-layers
US5362662A (en) * 1989-08-11 1994-11-08 Ricoh Company, Ltd. Method for producing semiconductor memory device having a planar cell structure

Also Published As

Publication number Publication date
GB2019091B (en) 1982-07-07
DE2815605C3 (en) 1981-04-16
DE2815605A1 (en) 1979-10-18
DE2815605B2 (en) 1980-06-26
FR2423030A1 (en) 1979-11-09

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee