DE3304651A1 - DYNAMIC SEMICONDUCTOR MEMORY CELL WITH OPTIONAL ACCESS (DRAM) AND METHOD FOR THEIR PRODUCTION - Google Patents

Description

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SIEMENS AKTIENGESELLSCHAFT Our symbols Berlin and Munich VPA

83 P 10 63 OE

Dynamic semiconductor random access (DRAM) memory cell and method for making the same.

The invention relates to a dynamic semiconductor memory cell with random access (DRAM) in which the bit line is diffused into the semiconductor substrate in the area of the memory cells, adjacent to the bit line for generating the storage capacity over the semiconductor substrate and a storage electrode is arranged insulated from this and above the bit line and the Storage electrode insulates from these and the storage capacitance electrode at least partially overlapping that of a word line driven transfer electrode arranged is, as well as methods of making the same.

It is known to build semiconductor memories using MOS technology. These memory cells consist of, for example a storage capacity and a MOS transistor, the control electrode of which is connected to a word line. the Both controlled electrodes of the MOS transistor are located between the storage capacity and a bit line. Such memory cells are referred to as single-transistor RAM (= andom a.ccess jnemory) cells.

A disadvantage of such single-transistor memory cells is that for the diffused areas in the memory module Space is needed. However, there are as many memory cells as possible on one memory module in the case of semiconductor memories are to be arranged, there is a tendency to make the individual memory cell as small as possible.

Edt 1 Plr / January 26, 1983

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One possibility to realize this is to place the storage electrode for the formation of the storage capacity over the semiconductor substrate, to be arranged stripped from the semiconductor substrate. The Bit line diffused into the semiconductor substrate. To an exchange of charge between the storage capacity and to enable the bit line is on the semiconductor substrate The so-called transfer electrode, which provides the storage capacity, is arranged in isolation from the semiconductor substrate and the bit line at least partially overlaps.

Further space-saving possibilities result from the use of the double-poly-silicon technology the manufacture of the memory cells. A memory cell of the type mentioned at the outset with a diffused bit line with "buried contact" in two-layer poly-silicon technology is from an essay by V. L. Rideout from the IEEE Trans. Electron. Dev. Vol. ED-26, No. 6 (1979) to the Pages 839 to 852, in particular page 846, can be found.

The task on which the invention is based now exists in a further increase in the packing density of memory cells for dynamic semiconductor memory cells random access (DRAM) in a memory module and in particular in the specification of methods for their possible simple production, which ensures that mask-consuming process steps that have a high Require accuracy in the adjustment, can be omitted.

The object according to the invention is achieved by a memory cell of the type mentioned in that the bit line and the storage electrode are made of a doped one Silicide consist of a high-melting metal and the length of the transfer gate by the distance between the suicide is defined on the bit line and the silicide of the capacitance electrode.

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In a further development of the inventive concept it is provided that the bit line and the memory capacity electrode from a silicide of the metals tantalum, titanium, tungsten or doped with arsenic, phosphorus or boron Molybdenum consists, with more silicon being contained in the compound than corresponds to the stoichiometry, and that the transfer electrode made of polysilicon, the system polysilicon / high-melting point Metal, the polysilicon / metal silicide system, from a silicide of the metals tantalum, titanium, tungsten or molybdenum, or from pure metal consists.

To produce the memory cell according to the invention, a method is proposed which is characterized in that the drain region lying under the bit line by outdiffusion of those provided with a dopant of a second conductivity type, directly on the surface one, by thick oxide areas on or in its surface divided semiconductor substrate from the first Conduction type deposited silicide of a refractory metal is generated. The doping can be increased the deposition of the silicide layer by implanting dopant ions of the second conductivity type into the silicide take place; however, the metal silicide layer can also be doped by using a layer mixed with the dopant Tantalum, titanium, tungsten or molybdenum silicide targets by sputtering or by reactive sputtering of undoped Silicide can be applied in an atmosphere containing the dopant. As a dopant from the second Conductivity type is arsenic, phosphorus or boron used.

Further details of the method according to the invention are hereinafter based on an exemplary embodiment and FIGS. 1 to 4 in the drawing are explained in more detail. Figures 1 to 3 show in Sectional view and in detail the process steps essential to the invention for producing a dynamic

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RAM cell with n-channel transistors, the transfer gate overlaps both the edge of the drain area under the bit line and the edge of the storage capacitance electrode. Figure 4 shows another embodiment of the invention, in which the gate electrode is applied in a self-aligning manner. Same reference numbers have been used for the same parts. On the representation of the process steps essential to the invention details not concerned, the arrangement of the cell in an integrated circuit, passivation and implementation the metallization has been omitted here.

FIG. 1: On a p-doped silicon semiconductor substrate 1, structured SiOp layers 2 are produced using the so-called LOCOS or isoplanar method to separate the active areas. An oxidation process is then carried out over the entire surface and the resulting oxide layer 3 (40 nm) is structured to define the storage capacitances and the bit line. This is followed by the deposition of an arsenic-doped tantalum silicide layer 4 in a layer thickness of 200 nm, for example by sputtering using an arsenic-doped tantalum silicide target, with more silicon than the stoichiometry of Corresponds to tantalum silicide. On this layer (4) an insulation layer 5 consisting of SiOp is applied over the whole area to reduce the overlap capacitances and to avoid dopant diffusion in a layer thickness of approx. 300 nm and the SiOp layer 5 with the underlying tantalum silicide layer 4 in the bit line area 10 and in the Storage capacity area 11 structured by a reactive dry etching process. The distance between the thin oxide edge 14 and the bit line area 10 and the storage capacity 11 must at least correspond to the adjustment tolerance (in the exemplary embodiment the distance is in the range from 500 to 1000 nm). This ensures that the silicide

VPA 83 P 1 063 QE

layer 4, 11 has no contact with the Si substrate and the silicide layer 4, 10 over the entire surface of the substrate rests.

FIG. 2: This is followed by an oxide etching over the entire area, in which the oxide region 14 is removed. During the thermal treatment to produce the gate oxide 6 at 90O ⁰ C, the drain region 8 located below the silicide structure 4 in the bit line region 10 is produced by outdiffusion of arsenic (n) and the silicide flanks are provided with an oxide 7.

Figure 5: Following the generation of the channel zone 9 in the transfer gate area 12 by implantation of boron ions, the entire surface of the "Trans fergate 12 forming polysilicon layer 13 is deposited, which is structured so that the gate electrode is the edge of the channel zone 9 facing Drain area 8 and the edge of the storage capacitance electrode 11 facing the channel zone 9 overlaps.

Finally, as is no longer shown, an intermediate layer serving as an insulation oxide is produced which Contact holes for the conductor tracks are etched and the metallization is carried out.

FIG. 4 shows another advantageous embodiment of the invention, in which, in contrast to FIG. 3, the transfer gate (12) is not designed to overlap in order to generate minimal overlap capacitances, but is introduced between the silicide structures 4 in a self-adjusting manner using the so-called lift-off technique. This is done in the following way: instead of the insulation layer 5 made of SiOp (according to FIG. 1), an insulation layer 15 made of silicon nitride is applied, and instead of the polysilicon layer 13 (according to FIG. 3) forming the transfer gate, a metal silicide layer is applied.

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layer 23 used. During the vapor deposition of this metal silicide layer 23 inevitably tears off the connection at the silicon nitride edges in the transfer gate area 12. the FIG. 4 shows the arrangement after structuring the gate electrode. Those located on the nitride layer 15 Partial structures 23a and 23b are when the nitride layer 15 is removed using an isotropic etching process removed by taking off. Then, as is no longer shown, the insulation oxide is produced, the contact holes etched for the conductor tracks and carried out the metallization.

These processes are analogous also with p-channel transistors possible, as for example in the article by Shimohigashi in the IEEE Trans. Electron. Dev. Vol. ED-29, No. 4 (1982) pages 714-718.

By the memory cell according to the invention with the so-called Silicide field plate (4, 11 "fieldplate"), the bit line from the silicide (4, 10) and the η region 8 diffused from the silicide are compared to the known Arrangement (e.g. rideout) achieves the following advantages:

1. The silicide acts as a self-adjusting contact for the transfer transistor. As a result of the self-adjusting contact, a higher packing density is possible.

2. The gate length does not depend on the adjustment accuracy

dependent as they line by the spacing silicide bit and silicide field plate is defined.

3. By using the suicide one gets a very low bit line.

12 claims
4 figures

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Claims (12)

Claims (iJ Dynamic random access semiconductor memory cell (DRAM), in which the bit line in the area of the memory cell is diffused into the semiconductor substrate, adjacent to the bit line for generating the storage capacitance over the semiconductor substrate and insulated from it a storage electrode is arranged and insulated above the bit line and the storage electrode from the 10 "sen and the storage capacitance electrode at least partially the transfer electrode controlled by a word line is arranged overlapping, characterized that the bit line (4, 10) and the storage electrode (4, 11) are made of a doped silicide consist of a high-melting metal and the length of the transfer gate (12) by the distance of the suicide the bit line (4, 10) and the silicide of the storage capacitance electrode (4, 11) is defined. 2. Dynamic semiconductor memory cell according to claim 1, characterized in that the Bit line (10) and the storage capacitance electrode (11) made of a silicide doped with arsenic, phosphorus or boron the metals tantalum, titanium, tungsten or molybdenum, with more silicon in the compound than corresponds to 'stoichiometry. 3. Dynamic semiconductor memory cell according to claim 1 and / or 2, characterized 30 · net that the transfer electrode (12) made of polysilicon, the system polysilicon / refractory metal, the system polysilicon / metal silicide or from a A silicide of the metals tantalum, titanium, tungsten or molybdenum or consists of pure metal. 4. Process for the production of dynamic semiconductor memory cells with random access (DRAM) after -, r- VPA 83 P 1-0 6 3 DE Proverbs 1 to 3, characterized in that that the drain region (8) located under the bit line (10) is caused by outdiffusion of a dopant a second type of conduction, directly on the surface of a, through thick oxide areas (2) on or in its surface divided semiconductor substrate (1) of the first conductivity type deposited silicide (4) of a refractory metal is generated. 5. The method according to claim 4, characterized in that the doping after deposition the silicide layer (4) is carried out by implanting dopant ions of the second conductivity type. 6. The method according to claim 4, characterized in that the metal silicide layer (4) using a tantalum, titanium, tungsten or molybdenum silicide target to which the dopant has been added takes place by atomization. 7. Method according to claim 4, characterized that the metal silicide layer (4) by reactive sputtering of undoped silicide in an atmosphere containing the dopant is applied. 8. The method according to any one of claims 4 to 7, characterized in that as a dopant of the second conductivity type arsenic, phosphorus or boron is used. 9 · Method of manufacturing dynamic semiconductor memory cells with random access (DRAM) according to one of the method steps 1 to 8, characterized through the following process steps: -er- VPA 83 P 1 0 6 3 DE a) Production of structured SiO ^ layers (2) on a silicon semiconductor substrate (1) of a first
Line type for separating the active areas
the so-called LOCOS or isoplanar method, b) carrying out an oxidation process to generate the storage capacity oxide (3), c) Structuring of the storage capacity oxide (3) on the silicon semiconductor substrate (1) to define the Storage capacities, d) Deposition of a full-area layer (4) provided with the dopant of the second conductivity type and consisting of a siliconicide of the metals tantalum, titanium, tungsten or molybdenum with excess silicon
Vapor deposition, sputtering using a target mixed with the dopant or reactive sputtering in an atmosphere containing the dopant, e) full-surface deposition of an insulation layer (5) consisting _{of SiO 2 or silicon nitride,} f) structuring of those provided with the Si0_-layer (5) Metal silicide layer (4) in the bit line (10) and storage capacity area (11) by a reactive Dry etching process, g) full-surface oxide etching to remove the oxide area (14), h) Performing a thermal treatment to generate the gate oxide (6), the oxide on the silicide 35 edges (7) and the under the as bit line (10) serving metal silicide layer (4) lying drain area (8) by diffusion of the metal silicide in the '. VPA 83 P 1 063OE Zidschicht (4) contained dopant from the second Line type, i) Generation of a channel zone (9) in the gate region (12) by implantation of dopants of a first Line type, j) full-area deposition of one, the transfer gate (12) forming polysilicon layer (13), 10 k) structuring of the polysilicon layer (13) in such a way that the gate electrode formed corresponds to that of the channel zone (9) facing edge of the drain region (8) and the edge of the storage electrode facing the channel zone (9) (11) overlaps, l) production of an intermediate layer serving as insulation oxide, Etching the contact holes in the intermediate layer and performing the metallization in a known manner Way. 10. The method according to claim 9, characterized in that according to method step e) Silicon nitride is used as the insulation layer (15) that, instead of method step j), the transfer gate (12) forming metal silicide or metal layer (23) is vapor-deposited over the entire surface, with the nitride layer edge the connection of the metal silicide or metal layer (23) is interrupted, and that after the structuring the gate electrode according to method step k) by isotropic etching the silicon nitride layer (15) is removed, the metal silicide or metal layer structures (23a, 23b) located thereon also being lifted off will. 11. The method according to any one of claims 8 to 10, characterized in that the thickness :. '. X *: 33OA651 "·« 0 * 0 -Vf- VPA 83 P "1063 DE the storage oxide layer (3) is set to 20 - 50 nm will. 12. The method according to any one of claims 9 to 11, characterized in that the thickness the insulation layer according to method step e) on one Range is set from 100 to 500 nm.