CA1214271A - Dynamic semiconductor memory cell with random access (dram) and fabrication methods therefor - Google Patents
Dynamic semiconductor memory cell with random access (dram) and fabrication methods thereforInfo
- Publication number
- CA1214271A CA1214271A CA000446967A CA446967A CA1214271A CA 1214271 A CA1214271 A CA 1214271A CA 000446967 A CA000446967 A CA 000446967A CA 446967 A CA446967 A CA 446967A CA 1214271 A CA1214271 A CA 1214271A
- Authority
- CA
- Canada
- Prior art keywords
- silicide
- layer
- metal
- bit line
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 30
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 238000012546 transfer Methods 0.000 claims abstract description 17
- 238000002844 melting Methods 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 6
- 229910021332 silicide Inorganic materials 0.000 claims abstract 28
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract 28
- 239000000126 substance Substances 0.000 claims description 19
- 230000015654 memory Effects 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 229910052715 tantalum Inorganic materials 0.000 claims description 12
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- 229910052681 coesite Inorganic materials 0.000 claims 2
- 229910052906 cristobalite Inorganic materials 0.000 claims 2
- 239000000463 material Substances 0.000 claims 2
- 238000005546 reactive sputtering Methods 0.000 claims 2
- 239000000377 silicon dioxide Substances 0.000 claims 2
- 235000012239 silicon dioxide Nutrition 0.000 claims 2
- 238000004544 sputter deposition Methods 0.000 claims 2
- 229910052682 stishovite Inorganic materials 0.000 claims 2
- 229910052905 tridymite Inorganic materials 0.000 claims 2
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- 239000007787 solid Substances 0.000 claims 1
- 229910021341 titanium silicide Inorganic materials 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 238000012856 packing Methods 0.000 abstract description 3
- 238000000889 atomisation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 150000001768 cations Chemical class 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The invention relates to a dynamic semiconductor memory cell with random access (DRAM), in which a bit line and a storage capacitor electrode consist of a doped silicide of a metal of high melting point. The length of the transfer gate is defined by the spacing of the silicide on the bit line and on the silicide of the storage capacitor electrode. The invention relates also to a method for its fabrication. Due to the self-aligning (S/D) contact and through the use of the silicide a higher packing density and a very low-resistance bit line are made possible. The gate length does not depend on the adjustment accuracy as it is defined by the spacing of the silicide-bit line and silicide electrode.
The invention relates to a dynamic semiconductor memory cell with random access (DRAM), in which a bit line and a storage capacitor electrode consist of a doped silicide of a metal of high melting point. The length of the transfer gate is defined by the spacing of the silicide on the bit line and on the silicide of the storage capacitor electrode. The invention relates also to a method for its fabrication. Due to the self-aligning (S/D) contact and through the use of the silicide a higher packing density and a very low-resistance bit line are made possible. The gate length does not depend on the adjustment accuracy as it is defined by the spacing of the silicide-bit line and silicide electrode.
Description
Z 2036~-2361 BACKGROUND OF TIE INVENTION
This invention relates to a dynamic semiconductor memory cell wit random access (DRAM). In particular to a DRAM in which the bit line is diffused into the semiconductor substrate in the area of the memory cells; adjacent to the bit line a storage electrode for the creation of the storage capacity is arranged over the semiconductor substrate; and above the bit line and story age electrode, insulated therefrom and at least partially overlapping the storage capacity electrode, the transfer electrode controlled by a word line is arranged. Methods for the production of the DRY are also disclosed.
To fabricate semiconductor memories using MOW techniques is well known. These memory cells consist for example of a storage capacitor and a MOW
transistor, the control electrode of which is connected to a word line. The two controlled electrodes of the MOW transistor are arranged between the storage capacitor and a bit line. Such memory cells are referred to as single tray-sister RAM (Random Access Memory) cells.
A disadvantage of such single transistor memory cells is that space is needed for the diffused areas in the memory component. But because a maximum of memory cells are to be arranged on a memory component in semi-conductor memories, the trend is to make the individual memory cell as small as possible.
One known solution is to arrange tune storage electrode for the formation of the storage capacitor over the semiconductor substrate and in-sulfated therefrom. Adjacent to the storage capacitor the bit line is diffused into the semiconductor substrate. To permit a charge exchange between the storage capacitor and the bit line, arranged on the semiconductor substrate and insulated therefrom is a so-called transfer electrode, which overlaps the storage capacitor and the bit line at least partially.
Other space-saving possibilities are the use of the double-polysilicon technology in the production of memory cells. A memory cell of the previously mentioned kind with diffused bit line with "buried contact" in two-layer polysilicon technology has been described in an article by V. L.
Hideout in IEEE Trans. Electron. Dew. Vol. Ed-26, No. 6 (1979) at pages 839 to 852, specifically at page 846.
SUMMARY OF TIRE INVENTION
It is an object of the present invention to disclose memory cells for dynamic semiconductor memories with random access (DRAM) with in-creased packing density.
Furthermore, it is an object of the present invention to state methods for the simple production of Drills ensuring that process steps require in complicated masks which require high accuracy of adjustment are avoided.
The foregoing objectives and others are realized by a memory cell of the previously mentioned kind in which the bit line and the storage electrode comprise a doped solaced of a metal o-f high melting point and the length of the transfer gate is defined by the spacing of the solaced on the bit line and on the solaced of the capacitor electrode.
In a further embodiment of the invention it is provided that the bit line and the storage capacitor electrode include an arsenic, phosphorus, or boron doped solaced of the metals tantalum, titanium, tungsten, or Malibu-denim. More silicon is contained in the compound than corresponds to the dieselized stoichiometry. Furthermore, the transfer electrode consists of polysilicon, the system polysilicon/high melting metal, the system polysilicon/
metal solaced, a solaced of the metals tantalum, titanium, tungsten or molybdenum, or of pure metal.
For the fabrication of the memory cell of the invention a method is provided which is characterized in that the drain zone under the bit line is produced by diffusion of solaced of a metal of high melting point, provide Ed with a doping substance of a second conductivity type and deposited directly on the surface of a semiconductor substrate of the first conductivity type divided by thick oxide Jones on or in its surface. The doping can be effected after the deposition of the solaced layer by implantation of doping ions of the second conductivity type into the solaced. Alternatively, a metal solaced layer may be applied, doped by the use of a tantalum, titanium lung-stun or molybdenum solaced target mixed with the doping substance, by lo atomization or by reactive atomization of unhoped solaced in an atmosphere containing the doping substance. As doping substance of the second conductive fly type arsenic, phosphorus, or boron are used.
Other features and advantages of the invention will be apparent from the following description of the preferred embodiments and from the claims.
For a full understanding of the present invention, reference should now be made to the following detailed description of the preferred embodiments of the invention.
BRIEF DESCRIPTION OF Tiff DRAWINGS
.. _ _ . . . . . . _ Figures l to 3 show in sectional and partially cut away views the process steps for the dynamic RAM cell according to the invention.
Figure shows a further preferred embodiment of the invention in which a self-aligned method is used for generating the gate electrode.
DETAILED DESCRIPTION
... .. .. .. _ Figure l: On a p-doped silicon semiconductor substrate l, Sue layers 2 structured for the separation of the active zones are produced by the so-called LOOS or isoplanar method. Then over the whole area an oxidation process is carried out, and the resulting oxide Lowry no) is structured for I
the definition of the storage capacitors and of the bit line. Then follows the deposition of an arsenic-doped tantalum solaced layer 4 of a layer thickness of 200 no. This may be accomplished, for example, by atomizing with the use of an arsenic-doped tantalum solaced target, more silicon being present than corresponds to the stoichiometry of tantalum solaced, to permit subsequent reoxidation. On this layer (4) an insulation layer 5 consisting of Sue is applied over the whole area in a layer thickness of about 300 no, to reduce the overlap capacities and to avoid the out-diffusion of doping substance. The Sue layer 5 with the underlying tantalum solaced layer 4 is structured in the bit line zone 10 and in the storage capacity zone 11 by a reactive dry etching process. The distance of the thin oxide edge 14 from the bit line zone 10 and from the storage capacitor 11 must correspond at least to the adjustment toter-ante yin the embodiment the distance is in the range of 500 to 1000 no).
Thereby it is ensured that the solaced layer 4, 11 has no contact with the sift-con substrate and that the solaced layer 4, 10 rests on the whole area of the substrate.
Figure 2: Figure 2 shows an oxide etching over the whole area which follows the previous steps. By this etching the oxide zone 14 is removed.
Simultaneously with the thermal treatment for producillg the gate oxide 6 at 900C, the drain zone 8 lying under the solaced structure 4 in the bit line area 10 is produced by out-diffusion of arsenic (n ) and the solaced edges are provided with an oxide 7.
Figure 3: Following the production of the channel zone 9 in the transfer gate area 12 by implantation of boron ions, the polysilicon layer 13 forming the transfer gate 12 is deposited on the whole area. It is structured so that the gate electrode overlaps the edge of the drain zone 8 toward the channel zone 9 and the edge of the storage capacitor electrode 11 toward the channel zone 9.
Lastly, an intermediate layer serving as insulation oxide is pro-duped (this is not shown). The contact holes for the conductor tracks are etched and the metallization is carried out.
Figure 4: This figure shows another advantageous embodiment of the invention, in which, in contrast to Figure 3 and in order to produce minimum overlap capacities, the transfer gate 12 is designed to be not overlapping, but rather, using the so-called lift-off technique, to be introduced self-adjustingly (self-alignment) between the solaced structures I. This is done as follows: Instead of the insulation layer 5 consisting of Sue (according to Figure 1) an insulation layer 15 consisting of silicone nitride is applied, and instead of the polysilicon layer 13 forming the transfer gate (according to Figure 3), a metal solaced layer 23 is used. During vapor deposition of this metal solaced layer 23, the connection at the silicon nitride edges in the transfer gate region 12 necessarily breaks off. Figure 4 shows the arrangement after the structurization of the gate electrode. The partial structures aye and 23b present on the nitride layer 15 are removed upon removal of the nitride layer 15 using an isotropic etching method. Then, in a manner not shown, the insulation oxide is produced the contact holes for the conductor tracks are etched and the metallization is carried out.
These processes are similarly applicable with p-channel transistors, as is described for example in the article by Shimohigashi in IEEE Trans.
Electron, Dew. Vol. ED-29, No. 4 (1982) pages 714 to 718.
For the memory cell according to the invention with the so-called solaced field plate (4, 11), the bit line of solaced (4, 10) and the n zone 8 diffused out of the solaced, the following advantages over the known arrange-mint (for example Hideout) are achieved:
1. The solaced acts as a self-aligning contact for the transfer transistor. Because of the self-aligning contact a higher packing density is possible.
This invention relates to a dynamic semiconductor memory cell wit random access (DRAM). In particular to a DRAM in which the bit line is diffused into the semiconductor substrate in the area of the memory cells; adjacent to the bit line a storage electrode for the creation of the storage capacity is arranged over the semiconductor substrate; and above the bit line and story age electrode, insulated therefrom and at least partially overlapping the storage capacity electrode, the transfer electrode controlled by a word line is arranged. Methods for the production of the DRY are also disclosed.
To fabricate semiconductor memories using MOW techniques is well known. These memory cells consist for example of a storage capacitor and a MOW
transistor, the control electrode of which is connected to a word line. The two controlled electrodes of the MOW transistor are arranged between the storage capacitor and a bit line. Such memory cells are referred to as single tray-sister RAM (Random Access Memory) cells.
A disadvantage of such single transistor memory cells is that space is needed for the diffused areas in the memory component. But because a maximum of memory cells are to be arranged on a memory component in semi-conductor memories, the trend is to make the individual memory cell as small as possible.
One known solution is to arrange tune storage electrode for the formation of the storage capacitor over the semiconductor substrate and in-sulfated therefrom. Adjacent to the storage capacitor the bit line is diffused into the semiconductor substrate. To permit a charge exchange between the storage capacitor and the bit line, arranged on the semiconductor substrate and insulated therefrom is a so-called transfer electrode, which overlaps the storage capacitor and the bit line at least partially.
Other space-saving possibilities are the use of the double-polysilicon technology in the production of memory cells. A memory cell of the previously mentioned kind with diffused bit line with "buried contact" in two-layer polysilicon technology has been described in an article by V. L.
Hideout in IEEE Trans. Electron. Dew. Vol. Ed-26, No. 6 (1979) at pages 839 to 852, specifically at page 846.
SUMMARY OF TIRE INVENTION
It is an object of the present invention to disclose memory cells for dynamic semiconductor memories with random access (DRAM) with in-creased packing density.
Furthermore, it is an object of the present invention to state methods for the simple production of Drills ensuring that process steps require in complicated masks which require high accuracy of adjustment are avoided.
The foregoing objectives and others are realized by a memory cell of the previously mentioned kind in which the bit line and the storage electrode comprise a doped solaced of a metal o-f high melting point and the length of the transfer gate is defined by the spacing of the solaced on the bit line and on the solaced of the capacitor electrode.
In a further embodiment of the invention it is provided that the bit line and the storage capacitor electrode include an arsenic, phosphorus, or boron doped solaced of the metals tantalum, titanium, tungsten, or Malibu-denim. More silicon is contained in the compound than corresponds to the dieselized stoichiometry. Furthermore, the transfer electrode consists of polysilicon, the system polysilicon/high melting metal, the system polysilicon/
metal solaced, a solaced of the metals tantalum, titanium, tungsten or molybdenum, or of pure metal.
For the fabrication of the memory cell of the invention a method is provided which is characterized in that the drain zone under the bit line is produced by diffusion of solaced of a metal of high melting point, provide Ed with a doping substance of a second conductivity type and deposited directly on the surface of a semiconductor substrate of the first conductivity type divided by thick oxide Jones on or in its surface. The doping can be effected after the deposition of the solaced layer by implantation of doping ions of the second conductivity type into the solaced. Alternatively, a metal solaced layer may be applied, doped by the use of a tantalum, titanium lung-stun or molybdenum solaced target mixed with the doping substance, by lo atomization or by reactive atomization of unhoped solaced in an atmosphere containing the doping substance. As doping substance of the second conductive fly type arsenic, phosphorus, or boron are used.
Other features and advantages of the invention will be apparent from the following description of the preferred embodiments and from the claims.
For a full understanding of the present invention, reference should now be made to the following detailed description of the preferred embodiments of the invention.
BRIEF DESCRIPTION OF Tiff DRAWINGS
.. _ _ . . . . . . _ Figures l to 3 show in sectional and partially cut away views the process steps for the dynamic RAM cell according to the invention.
Figure shows a further preferred embodiment of the invention in which a self-aligned method is used for generating the gate electrode.
DETAILED DESCRIPTION
... .. .. .. _ Figure l: On a p-doped silicon semiconductor substrate l, Sue layers 2 structured for the separation of the active zones are produced by the so-called LOOS or isoplanar method. Then over the whole area an oxidation process is carried out, and the resulting oxide Lowry no) is structured for I
the definition of the storage capacitors and of the bit line. Then follows the deposition of an arsenic-doped tantalum solaced layer 4 of a layer thickness of 200 no. This may be accomplished, for example, by atomizing with the use of an arsenic-doped tantalum solaced target, more silicon being present than corresponds to the stoichiometry of tantalum solaced, to permit subsequent reoxidation. On this layer (4) an insulation layer 5 consisting of Sue is applied over the whole area in a layer thickness of about 300 no, to reduce the overlap capacities and to avoid the out-diffusion of doping substance. The Sue layer 5 with the underlying tantalum solaced layer 4 is structured in the bit line zone 10 and in the storage capacity zone 11 by a reactive dry etching process. The distance of the thin oxide edge 14 from the bit line zone 10 and from the storage capacitor 11 must correspond at least to the adjustment toter-ante yin the embodiment the distance is in the range of 500 to 1000 no).
Thereby it is ensured that the solaced layer 4, 11 has no contact with the sift-con substrate and that the solaced layer 4, 10 rests on the whole area of the substrate.
Figure 2: Figure 2 shows an oxide etching over the whole area which follows the previous steps. By this etching the oxide zone 14 is removed.
Simultaneously with the thermal treatment for producillg the gate oxide 6 at 900C, the drain zone 8 lying under the solaced structure 4 in the bit line area 10 is produced by out-diffusion of arsenic (n ) and the solaced edges are provided with an oxide 7.
Figure 3: Following the production of the channel zone 9 in the transfer gate area 12 by implantation of boron ions, the polysilicon layer 13 forming the transfer gate 12 is deposited on the whole area. It is structured so that the gate electrode overlaps the edge of the drain zone 8 toward the channel zone 9 and the edge of the storage capacitor electrode 11 toward the channel zone 9.
Lastly, an intermediate layer serving as insulation oxide is pro-duped (this is not shown). The contact holes for the conductor tracks are etched and the metallization is carried out.
Figure 4: This figure shows another advantageous embodiment of the invention, in which, in contrast to Figure 3 and in order to produce minimum overlap capacities, the transfer gate 12 is designed to be not overlapping, but rather, using the so-called lift-off technique, to be introduced self-adjustingly (self-alignment) between the solaced structures I. This is done as follows: Instead of the insulation layer 5 consisting of Sue (according to Figure 1) an insulation layer 15 consisting of silicone nitride is applied, and instead of the polysilicon layer 13 forming the transfer gate (according to Figure 3), a metal solaced layer 23 is used. During vapor deposition of this metal solaced layer 23, the connection at the silicon nitride edges in the transfer gate region 12 necessarily breaks off. Figure 4 shows the arrangement after the structurization of the gate electrode. The partial structures aye and 23b present on the nitride layer 15 are removed upon removal of the nitride layer 15 using an isotropic etching method. Then, in a manner not shown, the insulation oxide is produced the contact holes for the conductor tracks are etched and the metallization is carried out.
These processes are similarly applicable with p-channel transistors, as is described for example in the article by Shimohigashi in IEEE Trans.
Electron, Dew. Vol. ED-29, No. 4 (1982) pages 714 to 718.
For the memory cell according to the invention with the so-called solaced field plate (4, 11), the bit line of solaced (4, 10) and the n zone 8 diffused out of the solaced, the following advantages over the known arrange-mint (for example Hideout) are achieved:
1. The solaced acts as a self-aligning contact for the transfer transistor. Because of the self-aligning contact a higher packing density is possible.
2. The gate length is not dependent on the adjusting accuracy, as it is defined by the distance between solaced bit line and between solaced field plate created in the same lithography step.
3. By the use of the solaced one obtains a very low-resistance bit line.
There has thus been shown and described a novel DRY and a fabric cation method therefore which fulfills all the objects and advantageous sought therefore inn changes, modifications, variations and other uses and applique-lions of the subject invention will, however, become apparent to those skilled in the art after considering the specification and the accompanying drawings which disclose preferred embodiments thereof. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention which is limited only by the claims which follow.
There has thus been shown and described a novel DRY and a fabric cation method therefore which fulfills all the objects and advantageous sought therefore inn changes, modifications, variations and other uses and applique-lions of the subject invention will, however, become apparent to those skilled in the art after considering the specification and the accompanying drawings which disclose preferred embodiments thereof. All such changes, modifications, variations and other uses and applications which do not depart from the spirit and scope of the invention are deemed to be covered by the invention which is limited only by the claims which follow.
Claims (21)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a dynamic semiconductor memory with random access (DRAM) in which a bit line is diffused into a semiconductor substrate in the area of memory cells, adjacent to the bit line a storage electrode for the creation of a storage capacitor is arranged over the semiconductor substrate, and above the bit line and the storage electrode, insulated therefrom and at least partially overlapping the storage capacitor electrode, a transfer electrode controlled by a word line is arranged, the improvement wherein is that said bit line and said storage electrode comprise a doped silicide of a metal of high melting point and that the length of the transfer gate is defined by the spacing of the silicide on the bit line and of the silicide on the storage capacitor electrode.
2. Dynamic semiconductor memory according to claim 1, wherein said bit line and said storage capacitor electrode may be comprised of a silicide of the metals tantalum, titanium or molybdenum, doped with arsenic, phosphorus or boron, more silicon being contained in the compound than corresponds to the disilicide stoichiometry.
3. Dynamic semiconductor memory according to claim 1, wherein said transfer electrode may be comprised of the materials selected from the group consisting of polysilicon, the system polysilicon/high-melting metal, the sys-tem polysilicon/metal silicide, a silicide of the metals tantalum, titanium, tungsten, molybdenum or of pure metal.
4. Dynamic semiconductor memory according to claim 2, wherein said transfer electrode may be comprised of the materials selected from the group consisting of polysilicon, the system polysilicon/high-melting metal, the system polysilicon/metal silicide, a silicide of the metals tantalum, titanium, tungsten, molybdenum or of pure metal.
5. Method for producing a dynamic semiconductor memory of the random access (DRAM) type comprising the step of: dopant out-diffusion from silicide of a metal of high melting point to produce a drain zone lying under a bit line, said silicide being provided with a doping substance of a second conduc-tivity type and being deposited directly on the surface of a semiconductor substrate of a first conductivity type said semiconductor substrate being divided by thick surface defining oxide zones.
6. Method according to claim 5, wherein said out-diffusion includes:
implanting doping substance ions of said second conductivity type after deposition of the silicide layer into the silicide to create said doping substance.
implanting doping substance ions of said second conductivity type after deposition of the silicide layer into the silicide to create said doping substance.
7. Method according to claim 5, including: applying said silicide of a metal to said substrate by sputtering, using a tantalum, titanium, tung-sten or molybdenum silicide target mixed with said doping substance.
8. Method according to claim 5, including: applying said silicide of a metal to said substrate by reactive sputtering of undoped silicide in an atmosphere containing said doping substance.
9. Method according to claim 5, wherein said doping substance of the second conductivity type is selected from the group consisting of arsenic, phosphorus or boron.
10. Method according to claim 6, wherein said doping substance of the second conductivity type is selected from the group consisting of arsenic, phosphorus or boron.
11. Method according to claim 7, wherein said doping substance of the second conductivity type is selected from the group consisting of arsenic, phosphorus or boron.
12. Method according to claim 8, wherein said doping substance of the second conductivity type is selected from the group consisting of arsenic, phosphorus or boron.
13. Method for producing dynamic semiconductor memory cells with ran-dom access (DRAM) comprising the steps of:
a) producing structured SiO2 layers on a silicon semiconductor substrate of a first conductivity type for the separation of active regions by the so-called LOCOS or isoplanar method;
b) executing an oxidation process for the production of a storage capacitor oxide;
c) structuring of said storage capacitor oxide on the silicon semiconductor substrate for the definition of storage capacities;
d) depositing a solid layer provided with a doping substance of a second conductivity type, consisting of a silicide of the metals tantalum, titanium, tungsten or molybdenum with excess of silicon;
e) whole-area depositing of an insulation layer;
f) structuring of a metal silicide layer provided with the in-sulation layer in a bit line region and in a storage region by a reactive dry etching process;
g) whole-area oxide etching to remove an unwanted oxide region;
h) thermally treating said semiconductor to produce a gate oxide, an oxide on silicide edges and of a drain zone under said metal silicide layer serving as said bit line, by out-diffusion of the doping substance of the second conductivity type contained in the metal silicide layer;
i) producing a channel zone in the gate region by implantation of doping substances of said first conductivity type;
j) whole-area depositing of a polysilicon layer forming a trans-fer gate;
k) structuring said polysilicon layer so that the resulting gate electrode overlaps the edge of the drain zone toward the channel zone and the edge of a storage electrode toward the channel zone; and l) producing an intermediate layer serving as insulation oxide, etching the contact holes in the intermediate layer and effecting the metal-lization of the semiconductor.
a) producing structured SiO2 layers on a silicon semiconductor substrate of a first conductivity type for the separation of active regions by the so-called LOCOS or isoplanar method;
b) executing an oxidation process for the production of a storage capacitor oxide;
c) structuring of said storage capacitor oxide on the silicon semiconductor substrate for the definition of storage capacities;
d) depositing a solid layer provided with a doping substance of a second conductivity type, consisting of a silicide of the metals tantalum, titanium, tungsten or molybdenum with excess of silicon;
e) whole-area depositing of an insulation layer;
f) structuring of a metal silicide layer provided with the in-sulation layer in a bit line region and in a storage region by a reactive dry etching process;
g) whole-area oxide etching to remove an unwanted oxide region;
h) thermally treating said semiconductor to produce a gate oxide, an oxide on silicide edges and of a drain zone under said metal silicide layer serving as said bit line, by out-diffusion of the doping substance of the second conductivity type contained in the metal silicide layer;
i) producing a channel zone in the gate region by implantation of doping substances of said first conductivity type;
j) whole-area depositing of a polysilicon layer forming a trans-fer gate;
k) structuring said polysilicon layer so that the resulting gate electrode overlaps the edge of the drain zone toward the channel zone and the edge of a storage electrode toward the channel zone; and l) producing an intermediate layer serving as insulation oxide, etching the contact holes in the intermediate layer and effecting the metal-lization of the semiconductor.
14. Method according to claim 13, wherein said depositing in step d) is effected by vapor deposition.
15. Method according to claim 13, wherein said depositing in step d) is effected by sputtering with the use of a target mixed with the doping sub-stance.
16. Method according to claim 13, wherein said depositing in step d) is effected by reactive sputtering in an atmosphere containing the doping sub-stance.
17. Method according to claim 13, wherein said insulation layer of step e) comprises SiO2.
18. Method according to claim 13, wherein said insulation layer of step e) comprises silicon nitride.
19. Method according to claim 18, wherein instead of process step j) a metal silicide layer forming the transfer gate is vapor deposited on the whole area, the connection of the metal silicide being interrupted at the nitride layer edge, and that after the structurization of the gate electrode according to process step k) the silicon nitride layer is removed by isotropic etching, the metal silicide layer structures present thereon being lifted off.
20. Method according to claim 13, wherein the thickness of the insula-tion layer according to process step e) is adjusted to a range of from 100 to 500 nm.
21. Method according to claim 19, wherein the thickness of the in-sulation layer according to process step e) is adjusted to a range of from 100 to 500 nm.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19833304651 DE3304651A1 (en) | 1983-02-10 | 1983-02-10 | DYNAMIC SEMICONDUCTOR MEMORY CELL WITH OPTIONAL ACCESS (DRAM) AND METHOD FOR THEIR PRODUCTION |
| DEP3304651.4 | 1983-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1214271A true CA1214271A (en) | 1986-11-18 |
Family
ID=6190554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000446967A Expired CA1214271A (en) | 1983-02-10 | 1984-02-08 | Dynamic semiconductor memory cell with random access (dram) and fabrication methods therefor |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0116333A3 (en) |
| JP (1) | JPS59148361A (en) |
| CA (1) | CA1214271A (en) |
| DE (1) | DE3304651A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0279463A (en) * | 1988-09-14 | 1990-03-20 | Mitsubishi Electric Corp | Semiconductor memory |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2815605C3 (en) * | 1978-04-11 | 1981-04-16 | Siemens AG, 1000 Berlin und 8000 München | Semiconductor memory with control lines of high conductivity |
| JPS607389B2 (en) * | 1978-12-26 | 1985-02-23 | 超エル・エス・アイ技術研究組合 | Manufacturing method of semiconductor device |
| US4364166A (en) * | 1979-03-01 | 1982-12-21 | International Business Machines Corporation | Semiconductor integrated circuit interconnections |
| GB2077993A (en) * | 1980-06-06 | 1981-12-23 | Standard Microsyst Smc | Low sheet resistivity composite conductor gate MOS device |
| DE3027954A1 (en) * | 1980-07-23 | 1982-02-25 | Siemens AG, 1000 Berlin und 8000 München | MOS integrated circuit with supplementary wiring plane - of silicide of high melting metal completely independent of metal wiring plane |
| US4337476A (en) * | 1980-08-18 | 1982-06-29 | Bell Telephone Laboratories, Incorporated | Silicon rich refractory silicides as gate metal |
| JPS5780739A (en) * | 1980-11-07 | 1982-05-20 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPS5793572A (en) * | 1980-12-03 | 1982-06-10 | Nec Corp | Manufacture of semiconductor device |
| DE3046218C2 (en) * | 1980-12-08 | 1982-09-02 | Siemens AG, 1000 Berlin und 8000 München | Method for producing a single transistor memory cell using double silicon technology |
| JPS57194567A (en) * | 1981-05-27 | 1982-11-30 | Hitachi Ltd | Semiconductor memory device |
-
1983
- 1983-02-10 DE DE19833304651 patent/DE3304651A1/en not_active Withdrawn
-
1984
- 1984-01-30 EP EP84100930A patent/EP0116333A3/en not_active Withdrawn
- 1984-02-07 JP JP59020689A patent/JPS59148361A/en active Pending
- 1984-02-08 CA CA000446967A patent/CA1214271A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0116333A3 (en) | 1986-02-05 |
| EP0116333A2 (en) | 1984-08-22 |
| JPS59148361A (en) | 1984-08-25 |
| DE3304651A1 (en) | 1984-08-16 |
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