JPS5499531A - Semiconductor memory unit - Google Patents

Semiconductor memory unit

Info

Publication number
JPS5499531A
JPS5499531A JP248278A JP248278A JPS5499531A JP S5499531 A JPS5499531 A JP S5499531A JP 248278 A JP248278 A JP 248278A JP 248278 A JP248278 A JP 248278A JP S5499531 A JPS5499531 A JP S5499531A
Authority
JP
Japan
Prior art keywords
diffusion layer
drain
source
diffusion
etching process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP248278A
Other languages
Japanese (ja)
Inventor
Keizo Kobayashi
Kuniyuki Hamano
Minetoshi Asaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP248278A priority Critical patent/JPS5499531A/en
Publication of JPS5499531A publication Critical patent/JPS5499531A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To secure the writing and deletion with the low voltage by providing a single conducting region of a high density around the reverse conducting region inside the substrate and thus to realize both the high integration degree and high performance without increasing the times of the photo etching process. CONSTITUTION:The semiconductor nonvolatile memory element contains n<+> diffusion layer 2 and 2' of the source and drain on P<-> semiconductor substrate 1' of a low impurity density, and P<+> diffusion layer 10 and 10' are formed around layer 2 and 2'. These n<+> and p<+> diffusion layers are formed through the diffusion self- matching via the same aperture part of the source and drain, thus eliminating the extra photo etching process for formation of the p<+> diffusion layer. Furthermore, the p<+> diffusion layer covers not only the drain but the source diffusion layer so that the punch-through phenomenon can be prevented. As a result, the element featuring a small channel length becomes possible easily, realizing a high degree of integration and the high performance.
JP248278A 1978-01-12 1978-01-12 Semiconductor memory unit Pending JPS5499531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP248278A JPS5499531A (en) 1978-01-12 1978-01-12 Semiconductor memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP248278A JPS5499531A (en) 1978-01-12 1978-01-12 Semiconductor memory unit

Publications (1)

Publication Number Publication Date
JPS5499531A true JPS5499531A (en) 1979-08-06

Family

ID=11530556

Family Applications (1)

Application Number Title Priority Date Filing Date
JP248278A Pending JPS5499531A (en) 1978-01-12 1978-01-12 Semiconductor memory unit

Country Status (1)

Country Link
JP (1) JPS5499531A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834976A (en) * 1981-08-26 1983-03-01 Nec Corp Nonvolatile semiconductor device
US5216269A (en) * 1989-03-31 1993-06-01 U.S. Philips Corp. Electrically-programmable semiconductor memories with buried injector region
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834976A (en) * 1981-08-26 1983-03-01 Nec Corp Nonvolatile semiconductor device
JPS6322625B2 (en) * 1981-08-26 1988-05-12 Nippon Electric Co
US5904518A (en) * 1988-11-09 1999-05-18 Hitachi, Ltd. Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
US6255690B1 (en) 1988-11-09 2001-07-03 Hitachi, Ltd. Non-volatile semiconductor memory device
US6451643B2 (en) 1988-11-09 2002-09-17 Hitachi, Ltd. Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs
US6777282B2 (en) 1988-11-09 2004-08-17 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a memory cell portion including MISFETs with a floating gate and a peripheral circuit portion with MISFETs
US6960501B2 (en) 1988-11-09 2005-11-01 Renesas Technology Corp. Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
US7071050B2 (en) 1988-11-09 2006-07-04 Hitachi, Ltd. Semiconductor integrated circuit device having single-element type non-volatile memory elements
US7399667B2 (en) 1988-11-09 2008-07-15 Renesas Technology Corp. Method of manufacturing a semiconductor integrated circuit device having single-element type non-volatile memory elements
US5216269A (en) * 1989-03-31 1993-06-01 U.S. Philips Corp. Electrically-programmable semiconductor memories with buried injector region

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