JPS56138949A - Semiconductor memory element - Google Patents

Abstract

PURPOSE:To form a semiconductor memory element of a simple writing operation by forming one conductive type second impurity layer directly under a gate insulating film and the other conductivite type third impurity layer directly under the second layer in a substantially one insulating gate FET. CONSTITUTION:A P type epitaxial layer 2 is formed on an N type substrate 1. It is electrically isolated with an oxide film layer 10. An N type impurity layer 3, a P type impurity layer 4, a gate oxide film 5, a gate electrode 6, source and drain N<+> type diffused layers 7, 8 and a P<+> type diffused layer 9 are sequentially formed thereon. In the memory configuration with the MOS transistor of the element structure as memory cell, an RX electrode is used as a word line at the time of reading, P<+> type buried region 9 and the electrode 6 as word lines at the time of writing, and the source and the drain are used as bit lines. Thus, a semiconductor memory element having simple writing operation, sufficient operation margin and substantially one insulating gate FET without storage capacitor can be formed.