JPS55153375A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS55153375A
JPS55153375A JP6200179A JP6200179A JPS55153375A JP S55153375 A JPS55153375 A JP S55153375A JP 6200179 A JP6200179 A JP 6200179A JP 6200179 A JP6200179 A JP 6200179A JP S55153375 A JPS55153375 A JP S55153375A
Authority
JP
Japan
Prior art keywords
gate
transistor
film
electrode
polycrystaline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6200179A
Other languages
Japanese (ja)
Other versions
JPS6344307B2 (en
Inventor
Masanori Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6200179A priority Critical patent/JPS55153375A/en
Publication of JPS55153375A publication Critical patent/JPS55153375A/en
Publication of JPS6344307B2 publication Critical patent/JPS6344307B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To attach electrically cancelling property to the stacked gate type memory stably and easily by making the first gate insulator film of the stacked gate MOS type memory transistor thinner than the gate insulator film of the MOS transistor. CONSTITUTION:P airs of source and drain regions 7, 8 and 11 are provided on a main surface 2 of an Si monocrystaline semiconductor substrate 1 separated from each other, while the thin first gate SiO2 film 3 is provided on the main surface 2 between the both regions. In addition, a polycrystaline Si floating gate electrode 4 made of metal or semiconductor is provided on the film 3 and a polycrystaline Si controlling electrode 6 made of metal or semiconductor on the second gate SiO2 film to form the stacked gate MOS type memory transistor Tr. The MOS type transistor having the polycrystaline SiO2 film 9 and the polycrystaline Si gate electrode 10 is provided connected in series to the transistor. The film 9 and the electrode 10 are connected in common to the electrode 6 of the memory transistor and the regions 8 and 11. The threshold voltage of the memory device is stored as written with the memory transistor while the cancelling state is determined with the MOS transistor.
JP6200179A 1979-05-18 1979-05-18 Non-volatile semiconductor memory device Granted JPS55153375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6200179A JPS55153375A (en) 1979-05-18 1979-05-18 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6200179A JPS55153375A (en) 1979-05-18 1979-05-18 Non-volatile semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS55153375A true JPS55153375A (en) 1980-11-29
JPS6344307B2 JPS6344307B2 (en) 1988-09-05

Family

ID=13187473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6200179A Granted JPS55153375A (en) 1979-05-18 1979-05-18 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS55153375A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5066992A (en) * 1989-06-23 1991-11-19 Atmel Corporation Programmable and erasable MOS memory device
US5084745A (en) * 1983-04-18 1992-01-28 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating gate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5138938A (en) * 1974-09-30 1976-03-31 Nippon Electric Co
JPS5164338A (en) * 1975-09-01 1976-06-03 Tokyo Shibaura Electric Co

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5138938A (en) * 1974-09-30 1976-03-31 Nippon Electric Co
JPS5164338A (en) * 1975-09-01 1976-06-03 Tokyo Shibaura Electric Co

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5084745A (en) * 1983-04-18 1992-01-28 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating gate
US5066992A (en) * 1989-06-23 1991-11-19 Atmel Corporation Programmable and erasable MOS memory device

Also Published As

Publication number Publication date
JPS6344307B2 (en) 1988-09-05

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