GB2139418A - Semiconductor devices and conductors therefor - Google Patents
Semiconductor devices and conductors therefor Download PDFInfo
- Publication number
- GB2139418A GB2139418A GB08312280A GB8312280A GB2139418A GB 2139418 A GB2139418 A GB 2139418A GB 08312280 A GB08312280 A GB 08312280A GB 8312280 A GB8312280 A GB 8312280A GB 2139418 A GB2139418 A GB 2139418A
- Authority
- GB
- United Kingdom
- Prior art keywords
- polysilicon
- gate
- metal
- semiconductor devices
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000004020 conductor Substances 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 29
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010960 commercial process Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910021352 titanium disilicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Polysilicon elements of integrated interconnects, are provided with circuits, for example gates (24) or metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallisation. After polysilicon metallisation the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24). <IMAGE>
Description
SPECIFICATION
Semiconductor devices
This invention relates to semiconductor devices and the manufacture thereof and, in particular, to semiconductor processing employing silicides.
Polysilicon has conventionally been employed for gates and interconnections in integrated circuits. However, for small geometry, high speed integrated circuits it is desirable to use alternative materials with lower resistivity, such as silicide materials. The resistivity of polysilicon is high (1000 4Q cm) and roughly fifty times larger than some silicides, for example titanium disilicide has a resisitivity of 20 ,uQ cm, and thus interconnections of polysilicon are extremely resistive in fine-line circuits. The propagational delay of electrical signals in such interconnect lines is a function of the product of the lumped capacitance and resistance of the interconnect line.As devices sizes are scaled down to achieve higher packing densities and speeds, this delay becomes dominated by the resistive component and thus new materials must be used. Silicides comprise such alternative materials which can be entirely compatible with the other components of the manufacturing process. Provided that the introduction of the material does not significantly perturb the existing process, the advantage of the new material can also be exploited in present day technologies.
A process has been developed whereby the silicide is formed by interdiffusing a layer of metal (tungsten, molybdenum, titanium, tantalum, etc.) with a sheet of doped polysilicon used to form the conventional gate and interconnects. This heterogeneous layer is then etched to form the gate and interconnects of the device. However, because the silicide overlying the doped polysilicon etches at different rates from the polysilicon, some undesirable undercutting at the gate occurs.
An alternative process has been develped to silicide the gate and diffused region, however this is a complex process.
The undercutting problems of the first mentioned process and the complexity of the second represent considerable barriers to the implementation of silicide into an existing process.
According to the present invention there is provided a method of manufacturing semiconductor devices including the steps of defining at least one polysilicon element on an oxidised surface of a silicon substrate, metallising the at least one polysilicon element, and causing the interdifussion of the metal and the polysilicon whereby to form a metallic silicide layer extending over the at least one polysilicon element.
An embodiment of the present invention will now be described with reference to the accompanying drawings, in which:
Figs. 1 a to c represent in schematic crosssection successive stages in the first-mentioned known process;
Figs. 2a to c represent in schematic crosssection successive stages in the secondmentioned known process, and
Figs. 3a to c represent in schematic crosssection successive stages in a method according to the present invention.
The known process shown in Figs. 1 a to c comprises the following steps. On a silicon substrate 1 , an oxide layer 2, which is thin in the area where source, drain and gate regions of the device are to be formed, is provided by conventional means. A layer of doped polycrystalline silicon (polysilicon) 3 is provided over the oxide 2 (Fig. 1 a). A metal layer 4 (Fig. 1 b) of, for example, tungsten, molybdenum, titanium or tantalum, is deposited on the polysilicon layer 3. A metallic silicide layer (Fig. 1 c) is formed by interdiffusing layers 3 and 4. The structure is then etched to form the gate 6 of the device and interconnects (not shown) and, because the silicide 5 etches at a different rate from the doped polysilicon 3, undercutting as at 7 occurs.The source 8 and drain 9 regions are next defined and implanted or diffused, and the process continues with the conventional oxidation step (intermediate oxide) (not shown), the oxidation at the silicide layer of the gate 6 relying on the diffusion of silicon from the underlying polysilicon to feed the oxidation process. The commercial process which employs this procedure is termed the POLYCIDE process. Adoption of the POLYCIDE process results in few changes when compared with the conventional polysilicon process, except that it introduces difficulties in etching the heterogeneous structure.
In the other known process illustrated in Figs.
2a to c and termed the SALICIDE process, the gate, interconnect, and diffused regions are silicided. In this process a polysilicon gate 10 is defined conventionally upon oxide layer 2 on substrate 1. A layer of CVD (chemical vapour deposited) oxide is deposited over the gate 10 and interconnects (not shown) and this oxide is etched anisotropically to leave side wall spacers 1 1 of oxide adjacent the gate 10. This etching serves also to open windows 12, via which the source and drain regions 8 and 9 are formed conventionally, and to remove any oxide in the contact areas and on the polysilicon 10. A layer of metal, for example titanium, tantalum, etc., is then deposited over the substrate surface and metallic silicide 1 3 is formed by interdiffusing in a furnace the metal of the layer and the silicon.Only in the areas of exposed silicon can the silicide form and no change occurs where the metal is deposited over oxide. The residual (unreacted) metal is then etched away preferentially to leave the silicide 13 in the diffused, and gate interconnect areas as illustrated in Fig. 2c, together with other interconnect areas, now shown. This method is called SALICIDE (self-aligned silicide), the silicide being self-aligned to the exposed silicon.
Processing continues with the conventional oxidation step etc. The oxide sidewall spacers 11 introduce complexities with regard to processing, but they are essential to avoid gate to source/drain short circuits.
An embodiment of the present invention is illustrated in Figs. 3a to c. Fig. 3a shows a silicon substrate 20 in which source and drain regions 21 and 22 have been provided by suitable processing, for example selective diffusion or implantation. An oxide layer 23 extends over the entire surface of the substrate 20 and as illustrated is thinner in the source, drain, gate region due to the processing involved. A layer of doped polycrystalline silicon (polysilicon) is provided over the oxide 23 and etched to define a polysilicon gate 24 aligned with the source and drain regions 21 and 22, together with interconnects (not shown). A layer of metal 25 (Fig. 36), for example, titanium, tungsten, tantalum, molybdenum etc., is then deposited over the polysilicon gats 24, interconnects and the exposed oxide 23.During residence in a furnace the metal overlying the polysilicon gate 24 and polysilicon interconnects becomes interdiffused therewith to form a metallic silicide, whereas there is no reaction between the metal and any directly underlying oxide. The residual (unreacted) metal is etched away to leave a metallic silicide 26 (Fig.
3c) over the gate 24 and around its sidewalls and similarly over and around the interconnects.
Processing continues with the conventional intermediate oxidation using the underlying polysilicon as a source of silicon to feed the oxidation process at the gate. The etchant employed to define the polysilicon gate 24 and interconnects must be sufficiently selective to leave the oxide 23 over the diffused regions 21 and 22, otherwise silicides would form in these regions leading to gate to source/drain short circuits.
The proposed process is similar to the
POLYCIDE process but differs therefrom in that the gate and interconnects are defined before the metal deposition step and in that no undercutting results. The proposed process can be implemented with conventional processing technology and does not disturb the overall conventional polysilicon process significantly, whilst resulting in low interconnect resistance values and retaining the oxidisability of the resulting silicide composite.
Claims (6)
1. A method of manufacturing semiconductor devices including the steps of defining at least one polysilicon element on an oxidised surface of a silicon substrate, metallising the at least one polysilicon element, and causing the interdiffusion of th metal and the polysilicon whereby to form a metallic silicide layer extending over the at least one polysilicon element.
2. A method as claimed in claim 1, wherein the at least one polysilicon element comprises a polysilicon gate and/or an interconnection.
3. A method as claimed in claim 1 or claim 2, wherein those portions of the oxidised surface of the silicon substrate surrounding the at least one polysilicon element are metallised during the metallisation step, and wherein the metal is removed from said portions after the interdiffusion step.
4. A method as claimed in any one of the preceding claims including the step of defining source and drain regions in the substrate prior to definition of the at least one polysilicon element.
5. A method of manufacturing semiconductor devices substantially as herein described with reference to and as illustrated in Figs. 3a to c of the accompanying drawings.
6. A semiconductor device manufactured by a method according to any one of the preceding claims.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08312280A GB2139418A (en) | 1983-05-05 | 1983-05-05 | Semiconductor devices and conductors therefor |
| GB08328552A GB2139420B (en) | 1983-05-05 | 1983-10-26 | Semiconductor devices |
| EP84300995A EP0124960A3 (en) | 1983-05-05 | 1984-02-16 | Semiconductor devices comprising silicides |
| JP8606784A JPS59207664A (en) | 1983-05-05 | 1984-04-27 | Method of producing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08312280A GB2139418A (en) | 1983-05-05 | 1983-05-05 | Semiconductor devices and conductors therefor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8312280D0 GB8312280D0 (en) | 1983-06-08 |
| GB2139418A true GB2139418A (en) | 1984-11-07 |
Family
ID=10542195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08312280A Withdrawn GB2139418A (en) | 1983-05-05 | 1983-05-05 | Semiconductor devices and conductors therefor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS59207664A (en) |
| GB (1) | GB2139418A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4200284A1 (en) * | 1991-01-08 | 1992-07-09 | Mitsubishi Electric Corp | Connecting layer for semiconductor - in which device has semiconductor substrate, first insulating layer, first conducting layer, and second conducting layer of higher conductivity |
| GB2320134A (en) * | 1996-12-04 | 1998-06-10 | United Microelectronics Corp | Salicide electrodes for semiconductor devices |
| CN1067804C (en) * | 1997-04-10 | 2001-06-27 | 联华电子股份有限公司 | Method for making self-aligning silicide |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2019091A (en) * | 1978-04-11 | 1979-10-24 | Siemens Ag | Semiconductor store |
| GB2052857A (en) * | 1979-06-11 | 1981-01-28 | Gen Electric | Composite conductive structure for integrated circuits |
| GB2062959A (en) * | 1979-11-06 | 1981-05-28 | Hewlett Packard Co | Method of forming self-registering source drain and gate contacts for fet structures |
| GB2075255A (en) * | 1980-03-26 | 1981-11-11 | Nippon Electric Co | Contact electrodes for semiconductor devices |
| GB2083284A (en) * | 1980-08-27 | 1982-03-17 | Philips Nv | Metal silicide on polycrystalline silicon layers |
| GB2104728A (en) * | 1981-08-27 | 1983-03-09 | Western Electric Co | Method of making cobalt disilicide electrode |
-
1983
- 1983-05-05 GB GB08312280A patent/GB2139418A/en not_active Withdrawn
-
1984
- 1984-04-27 JP JP8606784A patent/JPS59207664A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2019091A (en) * | 1978-04-11 | 1979-10-24 | Siemens Ag | Semiconductor store |
| GB2052857A (en) * | 1979-06-11 | 1981-01-28 | Gen Electric | Composite conductive structure for integrated circuits |
| GB2062959A (en) * | 1979-11-06 | 1981-05-28 | Hewlett Packard Co | Method of forming self-registering source drain and gate contacts for fet structures |
| GB2075255A (en) * | 1980-03-26 | 1981-11-11 | Nippon Electric Co | Contact electrodes for semiconductor devices |
| GB2083284A (en) * | 1980-08-27 | 1982-03-17 | Philips Nv | Metal silicide on polycrystalline silicon layers |
| GB2104728A (en) * | 1981-08-27 | 1983-03-09 | Western Electric Co | Method of making cobalt disilicide electrode |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4200284A1 (en) * | 1991-01-08 | 1992-07-09 | Mitsubishi Electric Corp | Connecting layer for semiconductor - in which device has semiconductor substrate, first insulating layer, first conducting layer, and second conducting layer of higher conductivity |
| US5502324A (en) * | 1991-01-08 | 1996-03-26 | Mitsubishi Denki Kabushiki Kaisha | Composite wiring layer |
| US5627093A (en) * | 1991-01-08 | 1997-05-06 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a wiring layer for use in a semiconductor device having a plurality of conductive layers |
| GB2320134A (en) * | 1996-12-04 | 1998-06-10 | United Microelectronics Corp | Salicide electrodes for semiconductor devices |
| CN1067804C (en) * | 1997-04-10 | 2001-06-27 | 联华电子股份有限公司 | Method for making self-aligning silicide |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8312280D0 (en) | 1983-06-08 |
| JPS59207664A (en) | 1984-11-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |