GB1465830A - Reducing boundary charges in semiconductor layers grown on a substrate - Google Patents

Reducing boundary charges in semiconductor layers grown on a substrate

Info

Publication number
GB1465830A
GB1465830A GB3309174A GB3309174A GB1465830A GB 1465830 A GB1465830 A GB 1465830A GB 3309174 A GB3309174 A GB 3309174A GB 3309174 A GB3309174 A GB 3309174A GB 1465830 A GB1465830 A GB 1465830A
Authority
GB
United Kingdom
Prior art keywords
layer
dopant
substrate
epitaxial layer
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3309174A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of GB1465830A publication Critical patent/GB1465830A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/024Defect control-gettering and annealing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/053Field effect transistors fets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/097Lattice strain and defects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/91Controlling charging state at semiconductor-insulator interface
GB3309174A 1973-09-03 1974-07-26 Reducing boundary charges in semiconductor layers grown on a substrate Expired GB1465830A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2344320A DE2344320C2 (de) 1973-09-03 1973-09-03 Verfahren zur Kompensation von Grenzflächenladungen bei epitaktisch auf ein Substrat aufgewachsenen Siliziumdünnschichten

Publications (1)

Publication Number Publication Date
GB1465830A true GB1465830A (en) 1977-03-02

Family

ID=5891465

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3309174A Expired GB1465830A (en) 1973-09-03 1974-07-26 Reducing boundary charges in semiconductor layers grown on a substrate

Country Status (15)

Country Link
US (1) US3909307A (enExample)
JP (1) JPS5931222B2 (enExample)
AT (1) AT340480B (enExample)
BE (1) BE819487A (enExample)
CA (1) CA1044577A (enExample)
CH (1) CH570044A5 (enExample)
DE (1) DE2344320C2 (enExample)
DK (1) DK461074A (enExample)
FR (1) FR2242777B1 (enExample)
GB (1) GB1465830A (enExample)
IE (1) IE39656B1 (enExample)
IT (1) IT1020412B (enExample)
LU (1) LU70843A1 (enExample)
NL (1) NL7410851A (enExample)
SE (1) SE392782B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5931224B2 (ja) * 1974-02-18 1984-07-31 日本電気株式会社 半導体装置
JPS5716499B2 (enExample) * 1974-05-27 1982-04-05
US4183134A (en) * 1977-02-15 1980-01-15 Westinghouse Electric Corp. High yield processing for silicon-on-sapphire CMOS integrated circuits
FR2380637A1 (fr) * 1977-02-15 1978-09-08 Westinghouse Electric Corp Procede de traitement de circuits integres cmos et circuits obtenus
US4149906A (en) * 1977-04-29 1979-04-17 International Business Machines Corporation Process for fabrication of merged transistor logic (MTL) cells
JPS5466767A (en) * 1977-11-08 1979-05-29 Fujitsu Ltd Manufacture for sos construction
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
US4330343A (en) * 1979-01-04 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Refractory passivated ion-implanted GaAs ohmic contacts
US4459159A (en) * 1982-09-29 1984-07-10 Mara William C O Method for making semi-insulating substrate by post-process heating of oxygenated and doped silicon
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
JPS59159563A (ja) * 1983-03-02 1984-09-10 Toshiba Corp 半導体装置の製造方法
US4732867A (en) * 1986-11-03 1988-03-22 General Electric Company Method of forming alignment marks in sapphire
US4766482A (en) * 1986-12-09 1988-08-23 General Electric Company Semiconductor device and method of making the same
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3520741A (en) * 1967-12-18 1970-07-14 Hughes Aircraft Co Method of simultaneous epitaxial growth and ion implantation
US3658586A (en) * 1969-04-11 1972-04-25 Rca Corp Epitaxial silicon on hydrogen magnesium aluminate spinel single crystals
US3582410A (en) * 1969-07-11 1971-06-01 North American Rockwell Process for producing metal base semiconductor devices
US3767483A (en) * 1970-05-11 1973-10-23 Hitachi Ltd Method of making semiconductor devices

Also Published As

Publication number Publication date
SE7411020L (enExample) 1975-03-04
JPS5931222B2 (ja) 1984-07-31
FR2242777B1 (enExample) 1979-01-05
DE2344320B1 (de) 1974-11-07
BE819487A (fr) 1974-12-31
US3909307A (en) 1975-09-30
LU70843A1 (enExample) 1975-01-02
IT1020412B (it) 1977-12-20
SE392782B (sv) 1977-04-18
FR2242777A1 (enExample) 1975-03-28
AT340480B (de) 1977-12-12
ATA640174A (de) 1977-04-15
IE39656B1 (en) 1978-12-06
IE39656L (en) 1975-03-03
DE2344320C2 (de) 1975-06-26
CA1044577A (en) 1978-12-19
DK461074A (enExample) 1975-05-05
NL7410851A (nl) 1975-03-05
JPS5056184A (enExample) 1975-05-16
CH570044A5 (enExample) 1975-11-28

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee