GB1368315A - Method for producing semiconductor on-insulator electronic devices - Google Patents

Method for producing semiconductor on-insulator electronic devices

Info

Publication number
GB1368315A
GB1368315A GB4791271A GB4791271A GB1368315A GB 1368315 A GB1368315 A GB 1368315A GB 4791271 A GB4791271 A GB 4791271A GB 4791271 A GB4791271 A GB 4791271A GB 1368315 A GB1368315 A GB 1368315A
Authority
GB
United Kingdom
Prior art keywords
monocrystalline
mgo
electronic devices
semi
producing semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4791271A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of GB1368315A publication Critical patent/GB1368315A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/025Deposition multi-step
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/053Field effect transistors fets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/097Lattice strain and defects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/15Silicon on sapphire SOS
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/967Semiconductor on specified insulator

Abstract

1368315 Epitaxial deposition of semiconductor TEXAS INSTRUMENTS Inc 14 Oct 1971 [2 Nov 1970] 47912/71 Heading C7F [Also in Division H1] A monocrystalline SOI is produced by heattreating a monocrystalline spinel substrate at a temperature in the range 1040-1145‹C. in a reducing atmosphere for a period of time sufficient to modify the composition of its surface to a desired composition for growth of a single crystal semi-conductor material thereon and to eliminate crystal defects such as cracks, twins, dislocations and grain boundaries and epitaxiallly depositing a thin monocrystalline semi-conductor on the modified surface. For example, MgO. Al 2 O 3 is heated in H 2 to give MgO. x Al 2 O 3 where x = 1À05 to 1À1, and the hydrogen atmosphere is then changed to H 2 /0À3 vol % SiH 4 + PH 3 dopant to deposit P- doped Si.
GB4791271A 1970-11-02 1971-10-14 Method for producing semiconductor on-insulator electronic devices Expired GB1368315A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US8620570A 1970-11-02 1970-11-02

Publications (1)

Publication Number Publication Date
GB1368315A true GB1368315A (en) 1974-09-25

Family

ID=22196987

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4791271A Expired GB1368315A (en) 1970-11-02 1971-10-14 Method for producing semiconductor on-insulator electronic devices

Country Status (6)

Country Link
US (1) US3796597A (en)
JP (1) JPS557017B1 (en)
CA (1) CA957250A (en)
DE (1) DE2153862B2 (en)
FR (1) FR2113447A5 (en)
GB (1) GB1368315A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2129019A (en) * 1982-09-30 1984-05-10 Western Electric Co Method of forming a heterostructure comprising a heteroepitaxial multiconstituent material

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4177321A (en) * 1972-07-25 1979-12-04 Semiconductor Research Foundation Single crystal of semiconductive material on crystal of insulating material
US4016016A (en) * 1975-05-22 1977-04-05 Rca Corporation Method of simultaneously forming a polycrystalline silicon gate and a single crystal extension of said gate in silicon on sapphire MOS devices
US4147584A (en) * 1977-12-27 1979-04-03 Burroughs Corporation Method for providing low cost wafers for use as substrates for integrated circuits
US4330932A (en) * 1978-07-20 1982-05-25 The United States Of America As Represented By The Secretary Of The Navy Process for preparing isolated junctions in thin-film semiconductors utilizing shadow masked deposition to form graded-side mesas
IT1128752B (en) * 1980-01-18 1986-06-04 Olivetti & Co Spa POCKET ELECTRONIC CALCULATOR
JPS5879358U (en) * 1981-11-26 1983-05-28 シャープ株式会社 Small electronic device with printer
US4447497A (en) * 1982-05-03 1984-05-08 Rockwell International Corporation CVD Process for producing monocrystalline silicon-on-cubic zirconia and article produced thereby
JPS61120548U (en) * 1985-01-18 1986-07-30
US6839362B2 (en) * 2001-05-22 2005-01-04 Saint-Gobain Ceramics & Plastics, Inc. Cobalt-doped saturable absorber Q-switches and laser systems
US6844084B2 (en) 2002-04-03 2005-01-18 Saint-Gobain Ceramics & Plastics, Inc. Spinel substrate and heteroepitaxial growth of III-V materials thereon
US20050061230A1 (en) * 2003-09-23 2005-03-24 Saint-Gobain Ceramics & Plastics, Inc. Spinel articles and methods for forming same
US7045223B2 (en) * 2003-09-23 2006-05-16 Saint-Gobain Ceramics & Plastics, Inc. Spinel articles and methods for forming same
US7326477B2 (en) * 2003-09-23 2008-02-05 Saint-Gobain Ceramics & Plastics, Inc. Spinel boules, wafers, and methods for fabricating same
US7919815B1 (en) 2005-02-24 2011-04-05 Saint-Gobain Ceramics & Plastics, Inc. Spinel wafers and methods of preparation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2129019A (en) * 1982-09-30 1984-05-10 Western Electric Co Method of forming a heterostructure comprising a heteroepitaxial multiconstituent material

Also Published As

Publication number Publication date
FR2113447A5 (en) 1972-06-23
DE2153862A1 (en) 1972-05-10
CA957250A (en) 1974-11-05
DE2153862B2 (en) 1980-03-06
US3796597A (en) 1974-03-12
JPS557017B1 (en) 1980-02-21
DE2153862C3 (en) 1980-10-23

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee