IT1020412B - Procedimento per compensare cari che limitofe in strati sottili di silicio cresciuti per deposizione epitassiale su un substrato - Google Patents

Procedimento per compensare cari che limitofe in strati sottili di silicio cresciuti per deposizione epitassiale su un substrato

Info

Publication number
IT1020412B
IT1020412B IT26877/74A IT2687774A IT1020412B IT 1020412 B IT1020412 B IT 1020412B IT 26877/74 A IT26877/74 A IT 26877/74A IT 2687774 A IT2687774 A IT 2687774A IT 1020412 B IT1020412 B IT 1020412B
Authority
IT
Italy
Prior art keywords
dears
compensating
limits
procedure
substrate
Prior art date
Application number
IT26877/74A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Application granted granted Critical
Publication of IT1020412B publication Critical patent/IT1020412B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)
IT26877/74A 1973-09-03 1974-09-03 Procedimento per compensare cari che limitofe in strati sottili di silicio cresciuti per deposizione epitassiale su un substrato IT1020412B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2344320A DE2344320C2 (de) 1973-09-03 1973-09-03 Verfahren zur Kompensation von Grenzflächenladungen bei epitaktisch auf ein Substrat aufgewachsenen Siliziumdünnschichten

Publications (1)

Publication Number Publication Date
IT1020412B true IT1020412B (it) 1977-12-20

Family

ID=5891465

Family Applications (1)

Application Number Title Priority Date Filing Date
IT26877/74A IT1020412B (it) 1973-09-03 1974-09-03 Procedimento per compensare cari che limitofe in strati sottili di silicio cresciuti per deposizione epitassiale su un substrato

Country Status (15)

Country Link
US (1) US3909307A (it)
JP (1) JPS5931222B2 (it)
AT (1) AT340480B (it)
BE (1) BE819487A (it)
CA (1) CA1044577A (it)
CH (1) CH570044A5 (it)
DE (1) DE2344320C2 (it)
DK (1) DK461074A (it)
FR (1) FR2242777B1 (it)
GB (1) GB1465830A (it)
IE (1) IE39656B1 (it)
IT (1) IT1020412B (it)
LU (1) LU70843A1 (it)
NL (1) NL7410851A (it)
SE (1) SE392782B (it)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5931224B2 (ja) * 1974-02-18 1984-07-31 日本電気株式会社 半導体装置
JPS5716499B2 (it) * 1974-05-27 1982-04-05
FR2380637A1 (fr) * 1977-02-15 1978-09-08 Westinghouse Electric Corp Procede de traitement de circuits integres cmos et circuits obtenus
US4183134A (en) * 1977-02-15 1980-01-15 Westinghouse Electric Corp. High yield processing for silicon-on-sapphire CMOS integrated circuits
US4149906A (en) * 1977-04-29 1979-04-17 International Business Machines Corporation Process for fabrication of merged transistor logic (MTL) cells
JPS5466767A (en) * 1977-11-08 1979-05-29 Fujitsu Ltd Manufacture for sos construction
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
US4330343A (en) * 1979-01-04 1982-05-18 The United States Of America As Represented By The Secretary Of The Navy Refractory passivated ion-implanted GaAs ohmic contacts
US4459159A (en) * 1982-09-29 1984-07-10 Mara William C O Method for making semi-insulating substrate by post-process heating of oxygenated and doped silicon
US4509990A (en) * 1982-11-15 1985-04-09 Hughes Aircraft Company Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
JPS59159563A (ja) * 1983-03-02 1984-09-10 Toshiba Corp 半導体装置の製造方法
US4732867A (en) * 1986-11-03 1988-03-22 General Electric Company Method of forming alignment marks in sapphire
US4766482A (en) * 1986-12-09 1988-08-23 General Electric Company Semiconductor device and method of making the same
US5453153A (en) * 1987-11-13 1995-09-26 Kopin Corporation Zone-melting recrystallization process
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3520741A (en) * 1967-12-18 1970-07-14 Hughes Aircraft Co Method of simultaneous epitaxial growth and ion implantation
US3658586A (en) * 1969-04-11 1972-04-25 Rca Corp Epitaxial silicon on hydrogen magnesium aluminate spinel single crystals
US3582410A (en) * 1969-07-11 1971-06-01 North American Rockwell Process for producing metal base semiconductor devices
US3767483A (en) * 1970-05-11 1973-10-23 Hitachi Ltd Method of making semiconductor devices

Also Published As

Publication number Publication date
DE2344320C2 (de) 1975-06-26
DK461074A (it) 1975-05-05
NL7410851A (nl) 1975-03-05
US3909307A (en) 1975-09-30
AT340480B (de) 1977-12-12
CA1044577A (en) 1978-12-19
ATA640174A (de) 1977-04-15
GB1465830A (en) 1977-03-02
IE39656L (en) 1975-03-03
SE392782B (sv) 1977-04-18
IE39656B1 (en) 1978-12-06
CH570044A5 (it) 1975-11-28
LU70843A1 (it) 1975-01-02
JPS5931222B2 (ja) 1984-07-31
FR2242777A1 (it) 1975-03-28
JPS5056184A (it) 1975-05-16
FR2242777B1 (it) 1979-01-05
BE819487A (fr) 1974-12-31
SE7411020L (it) 1975-03-04
DE2344320B1 (de) 1974-11-07

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