FR2920589B1 - "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure" - Google Patents

"procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"

Info

Publication number
FR2920589B1
FR2920589B1 FR0706180A FR0706180A FR2920589B1 FR 2920589 B1 FR2920589 B1 FR 2920589B1 FR 0706180 A FR0706180 A FR 0706180A FR 0706180 A FR0706180 A FR 0706180A FR 2920589 B1 FR2920589 B1 FR 2920589B1
Authority
FR
France
Prior art keywords
obtaining
layer
nitride material
hybrid substrate
hybrid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0706180A
Other languages
English (en)
French (fr)
Other versions
FR2920589A1 (fr
Inventor
Arnaud Garnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0706180A priority Critical patent/FR2920589B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to KR1020107006972A priority patent/KR20100075877A/ko
Priority to PCT/EP2008/061488 priority patent/WO2009030662A2/en
Priority to CN2008801053329A priority patent/CN101796627B/zh
Priority to EP08803470A priority patent/EP2186127A2/en
Priority to US12/672,819 priority patent/US8093686B2/en
Priority to JP2010523487A priority patent/JP2010537936A/ja
Publication of FR2920589A1 publication Critical patent/FR2920589A1/fr
Application granted granted Critical
Publication of FR2920589B1 publication Critical patent/FR2920589B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
FR0706180A 2007-09-04 2007-09-04 "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure" Active FR2920589B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0706180A FR2920589B1 (fr) 2007-09-04 2007-09-04 "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"
PCT/EP2008/061488 WO2009030662A2 (en) 2007-09-04 2008-09-01 Process for obtaining a hybrid substrate comprising at least one layer of a nitrided material
CN2008801053329A CN101796627B (zh) 2007-09-04 2008-09-01 用于获得包括至少一层氮化物材料的混合衬底的工艺
EP08803470A EP2186127A2 (en) 2007-09-04 2008-09-01 Process for obtaining a hybrid substrate comprising at least one layer of a nitrided material
KR1020107006972A KR20100075877A (ko) 2007-09-04 2008-09-01 적어도 한 층의 질화 물질을 포함하는 하이브리드 기판을 얻는 공정
US12/672,819 US8093686B2 (en) 2007-09-04 2008-09-01 Process for obtaining a hybrid substrate comprising at least one layer of a nitrided material
JP2010523487A JP2010537936A (ja) 2007-09-04 2008-09-01 少なくとも１つの窒化材料層を有するハイブリッド基板の製造法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0706180A FR2920589B1 (fr) 2007-09-04 2007-09-04 "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"

Publications (2)

Publication Number Publication Date
FR2920589A1 FR2920589A1 (fr) 2009-03-06
FR2920589B1 true FR2920589B1 (fr) 2010-12-03

Family

ID=39345309

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0706180A Active FR2920589B1 (fr) 2007-09-04 2007-09-04 "procede d'obtention d'un substrat hybride comprenant au moins une couche d'un materiau nitrure"

Country Status (7)

Country Link
US (1) US8093686B2 (ko)
EP (1) EP2186127A2 (ko)
JP (1) JP2010537936A (ko)
KR (1) KR20100075877A (ko)
CN (1) CN101796627B (ko)
FR (1) FR2920589B1 (ko)
WO (1) WO2009030662A2 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
JP5581619B2 (ja) * 2009-07-07 2014-09-03 株式会社村田製作所 圧電デバイスの製造方法および圧電デバイス
WO2011025149A2 (ko) * 2009-08-26 2011-03-03 서울옵토디바이스주식회사 반도체 기판 제조 방법 및 발광 소자 제조 방법
JP5544875B2 (ja) * 2009-12-25 2014-07-09 住友電気工業株式会社 複合基板
WO2011132654A1 (ja) 2010-04-20 2011-10-27 住友電気工業株式会社 複合基板の製造方法
FR2961948B1 (fr) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Procede de traitement d'une piece en materiau compose
FR2961719B1 (fr) * 2010-06-24 2013-09-27 Soitec Silicon On Insulator Procede de traitement d'une piece en un materiau compose
WO2012033551A1 (en) 2010-09-10 2012-03-15 Versatilis Llc Methods of fabricating optoelectronic devices using layers detached from semiconductor donors and devices made thereby
RU2469433C1 (ru) * 2011-07-13 2012-12-10 Юрий Георгиевич Шретер Способ лазерного отделения эпитаксиальной пленки или слоя эпитаксиальной пленки от ростовой подложки эпитаксиальной полупроводниковой структуры (варианты)
US10304739B2 (en) * 2015-01-16 2019-05-28 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor substrate, semiconductor substrate, method for manufacturing combined semiconductor substrate, combined semiconductor substrate, and semiconductor-joined substrate
WO2017179868A1 (ko) * 2016-04-12 2017-10-19 주식회사 루미스탈 반절연 질화물 반도체층을 포함하는 질화물 반도체 기판 제조 방법 및 이에 의해 제조된 질화물 반도체 기판
KR101951902B1 (ko) * 2016-04-12 2019-02-26 주식회사 루미스탈 복수의 공극을 포함한 질화물 반도체 기판 및 그 제조 방법
KR102001791B1 (ko) * 2018-12-26 2019-07-18 한양대학교 산학협력단 이온 주입을 이용한 질화갈륨 기판 제조 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2809867B1 (fr) 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
FR2816445B1 (fr) * 2000-11-06 2003-07-25 Commissariat Energie Atomique Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible
EP1429381B1 (en) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies A method for manufacturing a material compound
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
EP1519409B1 (en) * 2003-09-26 2008-08-20 S.O.I. Tec Silicon on Insulator Technologies S.A. A method of fabrication of a substrate for an epitaxial growth
WO2006015185A2 (en) * 2004-07-30 2006-02-09 Aonex Technologies, Inc. GaInP/GaAs/Si TRIPLE JUNCTION SOLAR CELL ENABLED BY WAFER BONDING AND LAYER TRANSFER
DE102005003884A1 (de) * 2005-01-24 2006-08-03 Forschungsverbund Berlin E.V. Verfahren zur Herstellung von c-plane orientierten GaN-oder AlxGa1-xN-Substraten
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
WO2006116030A2 (en) * 2005-04-21 2006-11-02 Aonex Technologies, Inc. Bonded intermediate substrate and method of making same
US8334155B2 (en) * 2005-09-27 2012-12-18 Philips Lumileds Lighting Company Llc Substrate for growing a III-V light emitting device
FR2896619B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite a proprietes electriques ameliorees

Also Published As

Publication number Publication date
JP2010537936A (ja) 2010-12-09
US8093686B2 (en) 2012-01-10
EP2186127A2 (en) 2010-05-19
CN101796627B (zh) 2013-03-27
WO2009030662A2 (en) 2009-03-12
WO2009030662A3 (en) 2009-06-25
CN101796627A (zh) 2010-08-04
FR2920589A1 (fr) 2009-03-06
KR20100075877A (ko) 2010-07-05
US20110095400A1 (en) 2011-04-28

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