FR2748157B1 - Dispositif a semiconducteurs comportant une structure silicium sur isolant et procede de fabrication de ce dispositif - Google Patents
Dispositif a semiconducteurs comportant une structure silicium sur isolant et procede de fabrication de ce dispositifInfo
- Publication number
- FR2748157B1 FR2748157B1 FR9700288A FR9700288A FR2748157B1 FR 2748157 B1 FR2748157 B1 FR 2748157B1 FR 9700288 A FR9700288 A FR 9700288A FR 9700288 A FR9700288 A FR 9700288A FR 2748157 B1 FR2748157 B1 FR 2748157B1
- Authority
- FR
- France
- Prior art keywords
- silicon
- manufacturing
- semiconductor device
- insulation structure
- insulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009413 insulation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10258296A JP4027447B2 (ja) | 1996-04-24 | 1996-04-24 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2748157A1 FR2748157A1 (fr) | 1997-10-31 |
FR2748157B1 true FR2748157B1 (fr) | 2000-01-14 |
Family
ID=14331232
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9700288A Expired - Fee Related FR2748157B1 (fr) | 1996-04-24 | 1997-01-14 | Dispositif a semiconducteurs comportant une structure silicium sur isolant et procede de fabrication de ce dispositif |
Country Status (5)
Country | Link |
---|---|
US (3) | US6025629A (fr) |
JP (1) | JP4027447B2 (fr) |
KR (1) | KR100225053B1 (fr) |
DE (1) | DE19642539A1 (fr) |
FR (1) | FR2748157B1 (fr) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4027447B2 (ja) * | 1996-04-24 | 2007-12-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
KR100349366B1 (ko) * | 1999-06-28 | 2002-08-21 | 주식회사 하이닉스반도체 | 에스오아이 소자 및 그의 제조방법 |
JP2002026311A (ja) | 2000-07-04 | 2002-01-25 | Miyazaki Oki Electric Co Ltd | Soi型mos素子およびその製造方法 |
JP3420205B2 (ja) * | 2000-11-20 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
EP1344245B1 (fr) * | 2000-12-21 | 2007-03-14 | Micronas GmbH | Procede pour realiser un corps solide dote d'une microstructure |
JP2003086807A (ja) * | 2001-09-10 | 2003-03-20 | Oki Electric Ind Co Ltd | 電界効果トランジスタの製造方法 |
JP3918741B2 (ja) * | 2002-03-28 | 2007-05-23 | セイコーエプソン株式会社 | 電気光学装置の製造方法、及び半導体装置の製造方法 |
JP2003332580A (ja) * | 2002-05-09 | 2003-11-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US7157774B2 (en) * | 2003-01-31 | 2007-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained silicon-on-insulator transistors with mesa isolation |
US7144767B2 (en) * | 2003-09-23 | 2006-12-05 | International Business Machines Corporation | NFETs using gate induced stress modulation |
JP4572367B2 (ja) * | 2004-03-26 | 2010-11-04 | セイコーエプソン株式会社 | 半導体装置およびその製造方法 |
JP4449076B2 (ja) * | 2004-04-16 | 2010-04-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
FR2872958B1 (fr) * | 2004-07-12 | 2008-05-02 | Commissariat Energie Atomique | Procede de fabrication d'un film mince structure et film mince obtenu par un tel procede |
JP2006093216A (ja) * | 2004-09-21 | 2006-04-06 | Toshiba Corp | 半導体装置 |
US7358571B2 (en) * | 2004-10-20 | 2008-04-15 | Taiwan Semiconductor Manufacturing Company | Isolation spacer for thin SOI devices |
KR100680958B1 (ko) * | 2005-02-23 | 2007-02-09 | 주식회사 하이닉스반도체 | 피모스 트랜지스터의 제조방법 |
JP2007103491A (ja) * | 2005-09-30 | 2007-04-19 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
WO2011043608A2 (fr) * | 2009-10-07 | 2011-04-14 | 주식회사 엘지화학 | Procédé de fabrication d'une batterie lithium-ion polymère, pile de batterie et pile lithium-ion polymère comprenant celle-ci |
WO2011074537A1 (fr) * | 2009-12-14 | 2011-06-23 | シャープ株式会社 | Procédé de fabrication d'un dispositif à transistor à couche mince |
WO2011096387A1 (fr) * | 2010-02-02 | 2011-08-11 | シャープ株式会社 | Dispositif à semi-conducteurs et procédé de fabrication associé |
WO2011149768A2 (fr) * | 2010-05-25 | 2011-12-01 | Ss Sc Ip, Llc | Dispositifs semi-conducteurs auto-alignés à fuite grille-source réduite sous une polarisation inversée, ainsi que procédés de fabrication |
JP2012142560A (ja) * | 2010-12-15 | 2012-07-26 | Canon Inc | 固体撮像装置およびその製造方法ならびにカメラ |
JP5944266B2 (ja) | 2012-08-10 | 2016-07-05 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
PL2882027T3 (pl) * | 2013-05-23 | 2020-09-07 | Lg Chem, Ltd. | Zespół elektrodowy i jednostka rodnikowa dla niego |
KR101776885B1 (ko) * | 2014-09-25 | 2017-09-08 | 주식회사 엘지화학 | 둘 이상의 케이스 부재들을 포함하는 각형 전지셀 |
CN113327914A (zh) * | 2021-05-27 | 2021-08-31 | 武汉新芯集成电路制造有限公司 | 半导体器件及其制造方法 |
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US4466176A (en) * | 1982-08-09 | 1984-08-21 | General Electric Company | Process for manufacturing insulated-gate semiconductor devices with integral shorts |
US4819054A (en) * | 1982-09-29 | 1989-04-04 | Hitachi, Ltd. | Semiconductor IC with dual groove isolation |
US4498227A (en) * | 1983-07-05 | 1985-02-12 | Fairchild Camera & Instrument Corporation | Wafer fabrication by implanting through protective layer |
US4538343A (en) * | 1984-06-15 | 1985-09-03 | Texas Instruments Incorporated | Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking |
JPS62136069A (ja) * | 1985-12-10 | 1987-06-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
US4753896A (en) * | 1986-11-21 | 1988-06-28 | Texas Instruments Incorporated | Sidewall channel stop process |
US4864380A (en) * | 1987-05-12 | 1989-09-05 | General Electric Company | Edgeless CMOS device |
US4786615A (en) * | 1987-08-31 | 1988-11-22 | Motorola Inc. | Method for improved surface planarity in selective epitaxial silicon |
JPH01145831A (ja) * | 1987-12-01 | 1989-06-07 | Citizen Watch Co Ltd | 半導体集積回路とその製造方法 |
US4965213A (en) * | 1988-02-01 | 1990-10-23 | Texas Instruments Incorporated | Silicon-on-insulator transistor with body node to source node connection |
US4946799A (en) * | 1988-07-08 | 1990-08-07 | Texas Instruments, Incorporated | Process for making high performance silicon-on-insulator transistor with body node to source node connection |
US4906587A (en) * | 1988-07-29 | 1990-03-06 | Texas Instruments Incorporated | Making a silicon-on-insulator transistor with selectable body node to source node connection |
US5095348A (en) * | 1989-10-02 | 1992-03-10 | Texas Instruments Incorporated | Semiconductor on insulator transistor |
JP2831745B2 (ja) * | 1989-10-31 | 1998-12-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
US4994406A (en) * | 1989-11-03 | 1991-02-19 | Motorola Inc. | Method of fabricating semiconductor devices having deep and shallow isolation structures |
KR970000533B1 (ko) * | 1990-12-20 | 1997-01-13 | 후지쓰 가부시끼가이샤 | Eprom 및 그 제조방법 |
US5218214A (en) * | 1991-05-17 | 1993-06-08 | United Technologies Corporation | Field oxide termination and gate oxide |
JPH05291242A (ja) | 1992-04-14 | 1993-11-05 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JPH05343509A (ja) * | 1992-06-05 | 1993-12-24 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US5451537A (en) * | 1994-08-12 | 1995-09-19 | Industrial Technology Research Institute | Method of forming a DRAM stack capacitor with ladder storage node |
US6200871B1 (en) * | 1994-08-30 | 2001-03-13 | Texas Instruments Incorporated | High performance self-aligned silicide process for sub-half-micron semiconductor technologies |
US5698902A (en) * | 1994-12-19 | 1997-12-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device having finely configured gate electrodes |
US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
JPH08316223A (ja) * | 1995-05-16 | 1996-11-29 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3504025B2 (ja) * | 1995-06-06 | 2004-03-08 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5700733A (en) * | 1995-06-27 | 1997-12-23 | Micron Technology, Inc. | Semiconductor processing methods of forming field oxide regions on a semiconductor substrate |
KR0176196B1 (ko) * | 1996-02-22 | 1999-04-15 | 김광호 | 반도체 장치의 로코스 소자분리 방법 |
JP4027447B2 (ja) * | 1996-04-24 | 2007-12-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US5714414A (en) * | 1996-08-19 | 1998-02-03 | Micron Technology, Inc. | Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate |
US5922622A (en) * | 1996-09-03 | 1999-07-13 | Vanguard International Semiconductor Corporation | Pattern formation of silicon nitride |
KR100204805B1 (ko) * | 1996-12-28 | 1999-06-15 | 윤종용 | 디엠오에스 트랜지스터 제조방법 |
US5923981A (en) * | 1996-12-31 | 1999-07-13 | Intel Corporation | Cascading transistor gate and method for fabricating the same |
US5930647A (en) * | 1997-02-27 | 1999-07-27 | Micron Technology, Inc. | Methods of forming field oxide and active area regions on a semiconductive substrate |
JPH10242294A (ja) * | 1997-02-27 | 1998-09-11 | Toshiba Microelectron Corp | 半導体装置及びその製造方法 |
US5894059A (en) * | 1997-05-30 | 1999-04-13 | Chartered Semiconductor Manufacturing Company Ltd. | Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect |
US5801082A (en) * | 1997-08-18 | 1998-09-01 | Vanguard International Semiconductor Corporation | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits |
US5940701A (en) * | 1997-12-03 | 1999-08-17 | Vanguard International Semiconductor Corporation | Method for forming a DRAM capacitor with four polysilicon pillars |
US6071793A (en) * | 1998-02-02 | 2000-06-06 | Chartered Semiconductor Manufacturing Ltd. | Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect |
US6005285A (en) * | 1998-12-04 | 1999-12-21 | Advanced Micro Devices, Inc. | Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device |
JP2002026311A (ja) * | 2000-07-04 | 2002-01-25 | Miyazaki Oki Electric Co Ltd | Soi型mos素子およびその製造方法 |
-
1996
- 1996-04-24 JP JP10258296A patent/JP4027447B2/ja not_active Expired - Fee Related
- 1996-10-15 DE DE19642539A patent/DE19642539A1/de not_active Ceased
- 1996-11-12 US US08/746,527 patent/US6025629A/en not_active Expired - Lifetime
-
1997
- 1997-01-14 FR FR9700288A patent/FR2748157B1/fr not_active Expired - Fee Related
- 1997-01-17 KR KR1019970001272A patent/KR100225053B1/ko not_active IP Right Cessation
-
2000
- 2000-01-12 US US09/481,385 patent/US6596615B2/en not_active Expired - Fee Related
-
2003
- 2003-04-28 US US10/423,960 patent/US6818536B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6818536B2 (en) | 2004-11-16 |
JP4027447B2 (ja) | 2007-12-26 |
FR2748157A1 (fr) | 1997-10-31 |
US20020016025A1 (en) | 2002-02-07 |
KR100225053B1 (ko) | 1999-10-15 |
KR970072209A (ko) | 1997-11-07 |
US20030207548A1 (en) | 2003-11-06 |
US6025629A (en) | 2000-02-15 |
JPH09293868A (ja) | 1997-11-11 |
US6596615B2 (en) | 2003-07-22 |
DE19642539A1 (de) | 1997-11-06 |
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FI954241A (fi) | Puolijohdelaitteen valmistusmenetelmä |
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