FR2681178A1 - Dispositif de memoire a semi-conducteur muni d'une electrode de stockage comportant des micro-saignees multiples et/ou des micro-cylindres multiples. - Google Patents

Dispositif de memoire a semi-conducteur muni d'une electrode de stockage comportant des micro-saignees multiples et/ou des micro-cylindres multiples. Download PDF

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Publication number
FR2681178A1
FR2681178A1 FR9210645A FR9210645A FR2681178A1 FR 2681178 A1 FR2681178 A1 FR 2681178A1 FR 9210645 A FR9210645 A FR 9210645A FR 9210645 A FR9210645 A FR 9210645A FR 2681178 A1 FR2681178 A1 FR 2681178A1
Authority
FR
France
Prior art keywords
layer
conduction
electrode
polysilicon
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9210645A
Other languages
English (en)
French (fr)
Other versions
FR2681178B1 (enrdf_load_stackoverflow
Inventor
Chin Dae-Je
Chung Tae-Young
Park Young-Woo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of FR2681178A1 publication Critical patent/FR2681178A1/fr
Application granted granted Critical
Publication of FR2681178B1 publication Critical patent/FR2681178B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/714—Electrodes having non-planar surfaces, e.g. formed by texturisation having horizontal extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
FR9210645A 1991-09-07 1992-09-07 Dispositif de memoire a semi-conducteur muni d'une electrode de stockage comportant des micro-saignees multiples et/ou des micro-cylindres multiples. Granted FR2681178A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR910015626 1991-09-07
KR920005409 1992-03-31

Publications (2)

Publication Number Publication Date
FR2681178A1 true FR2681178A1 (fr) 1993-03-12
FR2681178B1 FR2681178B1 (enrdf_load_stackoverflow) 1997-02-07

Family

ID=26628732

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9210645A Granted FR2681178A1 (fr) 1991-09-07 1992-09-07 Dispositif de memoire a semi-conducteur muni d'une electrode de stockage comportant des micro-saignees multiples et/ou des micro-cylindres multiples.

Country Status (6)

Country Link
JP (1) JP2690434B2 (enrdf_load_stackoverflow)
DE (1) DE4229837C2 (enrdf_load_stackoverflow)
FR (1) FR2681178A1 (enrdf_load_stackoverflow)
GB (1) GB2259406B (enrdf_load_stackoverflow)
IT (1) IT1256130B (enrdf_load_stackoverflow)
TW (1) TW222710B (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9670058B2 (en) 2012-04-02 2017-06-06 Stmicroelectronics (Rousset) Sas Integrated circuit provided with a device for detecting its spatial orientation and/or a modification of this orientation
US10379254B2 (en) 2012-11-16 2019-08-13 Stmicroelectronics (Rousset) Sas Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a projection

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960002097B1 (ko) * 1992-02-28 1996-02-10 삼성전자주식회사 반도체장치의 커패시터 제조방법
US5254503A (en) * 1992-06-02 1993-10-19 International Business Machines Corporation Process of making and using micro mask
JPH0774268A (ja) * 1993-07-07 1995-03-17 Mitsubishi Electric Corp 半導体記憶装置およびその製造方法
US5383088A (en) * 1993-08-09 1995-01-17 International Business Machines Corporation Storage capacitor with a conducting oxide electrode for metal-oxide dielectrics
US5512768A (en) * 1994-03-18 1996-04-30 United Microelectronics Corporation Capacitor for use in DRAM cell using surface oxidized silicon nodules
US5869368A (en) * 1997-09-22 1999-02-09 Yew; Tri-Rung Method to increase capacitance
KR100675275B1 (ko) 2004-12-16 2007-01-26 삼성전자주식회사 반도체 장치 및 이 장치의 패드 배치방법
TWI295822B (en) 2006-03-29 2008-04-11 Advanced Semiconductor Eng Method for forming a passivation layer
US11825645B2 (en) 2020-06-04 2023-11-21 Etron Technology, Inc. Memory cell structure
JP7339319B2 (ja) * 2021-12-03 2023-09-05 ▲ゆ▼創科技股▲ふん▼有限公司 メモリセル構造

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240057A (ja) * 1987-03-27 1988-10-05 Fujitsu Ltd スタツク型キヤパシタ

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01282855A (ja) * 1988-05-09 1989-11-14 Mitsubishi Electric Corp 半導体基板上にキャパシタを形成する方法
JPH03165552A (ja) * 1989-11-24 1991-07-17 Sony Corp スタックトキャパシタ型ｄｒａｍとその製造方法
JPH03166730A (ja) * 1989-11-27 1991-07-18 Seiko Instr Inc 半導体装置の製造方法
DD299990A5 (de) * 1990-02-23 1992-05-14 Dresden Forschzentr Mikroelek Ein-Transistor-Speicherzellenanordnung und Verfahren zu deren Herstellung
US5049517A (en) * 1990-11-07 1991-09-17 Micron Technology, Inc. Method for formation of a stacked capacitor
US5037773A (en) * 1990-11-08 1991-08-06 Micron Technology, Inc. Stacked capacitor doping technique making use of rugged polysilicon
KR930009583B1 (ko) * 1990-11-29 1993-10-07 삼성전자 주식회사 융모모양의 커패시터구조를 가진 반도체 메모리장치의 제조방법
JPH04207066A (ja) * 1990-11-30 1992-07-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
KR930009593B1 (ko) * 1991-01-30 1993-10-07 삼성전자 주식회사 고집적 반도체 메모리장치 및 그 제조방법(HCC Cell)
KR940005288B1 (ko) * 1991-07-11 1994-06-15 금성일렉트론 주식회사 반도체 장치의 제조방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240057A (ja) * 1987-03-27 1988-10-05 Fujitsu Ltd スタツク型キヤパシタ

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 33, no. 9, Février 1991, NEW YORK US pages 436 - 437 'MINI-TRENCHES IN POLYSILICON FOR DRAM STORAGE CAPACITANCE ENHANCEMENT' *
INTERNATIONAL ELECTRON DEVICES MEETING 1990 Décembre 1990, SAN FRANCISCO, CA, USA pages 655 - 658 M. SAKAO ET AL. 'A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs' *
JAPANESE JOURNAL OF APPLIED PHYSICS, SUPPLEMENTS: EXTENDED ABSTRACTS OF THE 21ST CONFERENCE ON SOLID STATE DEVICES AND MATERIALS 1989 1989, TOKYO JA pages 137 - 140 T. MINE ET AL. 'Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs' *
PATENT ABSTRACTS OF JAPAN vol. 13, no. 46 (E-711)(3394) 2 Février 1989 & JP-A-63 240 057 ( FUJITSU LTD ) 5 Octobre 1988 *
PATENT ABSTRACTS OF JAPAN vol. 15, no. 250 (E-108)26 Juin 1991 & JP-A-30 79 072 ( TOSHIBA CORP ) 4 Avril 1991 *
PATENT ABSTRACTS OF JAPAN vol. 15, no. 288 (E-109)22 Juillet 1991 & JP-A-31 01 261 ( SONY CORP ) 26 Avril 1991 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9670058B2 (en) 2012-04-02 2017-06-06 Stmicroelectronics (Rousset) Sas Integrated circuit provided with a device for detecting its spatial orientation and/or a modification of this orientation
US10379254B2 (en) 2012-11-16 2019-08-13 Stmicroelectronics (Rousset) Sas Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a projection
US11536872B2 (en) 2012-11-16 2022-12-27 Stmicroelectronics (Rousset) Sas Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a project
US12360135B2 (en) 2012-11-16 2025-07-15 Stmicroelectronics (Rousset) Sas Method for producing an integrated circuit pointed element comprising etching first and second etchable materials with a particular etchant to form an open crater in a projection

Also Published As

Publication number Publication date
DE4229837C2 (de) 1996-07-11
ITMI922067A0 (it) 1992-09-04
GB2259406A (en) 1993-03-10
DE4229837A1 (de) 1993-03-11
FR2681178B1 (enrdf_load_stackoverflow) 1997-02-07
ITMI922067A1 (it) 1994-03-04
GB9218898D0 (en) 1992-10-21
IT1256130B (it) 1995-11-29
TW222710B (enrdf_load_stackoverflow) 1994-04-21
GB2259406B (en) 1996-05-01
JPH05198745A (ja) 1993-08-06
JP2690434B2 (ja) 1997-12-10

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