FR2681178A1 - Semiconductor memory device fitted with a storage electrode containing multiple micro-clefts and/or multiple micro-cylinders - Google Patents

Abstract

a) Semiconductor memory device fitted with a storage electrode containing multiple micro-clefts and/or multiple micro-cylinders. b) Capacitor characterised in that the first electrode comprises a certain number of micro-clefts and/or micro-cylinders (70) formed on a predetermined surface of the conduction layer. c) Semiconductor memory device fitted with a storage electrode containing multiple micro-clefts and/or multiple micro-cylinders.

Description

"Semiconductor memory device having a storage electrode

  The present invention relates to a capacitor having a first electrode formed in a conductive layer formed on a limited surface of a substrate, a dielectric layer formed on the first surface of the substrate, and a plurality of microstructures. This is a high capacitance capacitor formed in a limited area of a semiconductor substrate and, more particularly provided with a storage capacitor, said semiconductor memory cell comprising a transfer transistor having a source region and a drain region formed on a semiconductor substrate, and a gate electrode placed in the vicinity of the source and drain zones, and a storage capacitor comprising a storage electrode provided with micro-grooves tiples and / or

  multiple micro-cylinders coupled to the source area, a dielectric layer overlying the storage electrode, and a plate electrode overlying the dielectric layer.

  A dynamic random access memory or dynamic random access memory (DRAM) has a number of memory cells each provided with a transfer transistor and a storage capacitor. As a result, the area occupied by the DRAM increases as one increases. the density of the memory cells As such an increase in the area of occupancy causes a decrease in efficiency, it is necessary to increase the storage capacity in the small limited area occupied by the respective storage capacitors, without increasing the surface area. as a function of the increase in the density of the memory cells To meet this requirement, a number of capacitor cell structures such as the stacked capacitor cell and capacitor cell structures have been proposed. The stacked capacitor has been widely proposed for dynamic random access memories (DRAM) of the Megab class t, because of the simplicity of the manufacturing process and the high immunity against software errors compared to the bleed capacitor An approach to meet the above requirement is to increase the surface area of the electrode for storage, or to reduce the effective thickness of the dielectric layer of the capacitor and to use good dielectric substances However, the present invention does not aim at reducing the effective thickness of the dielectric layer or increasing the permittivity, but aims at increasing the

  surface area of the storage electrode.

  A known technique that uses etching of the storage electrode to increase the surface area of this storage electrode is described in the Extended Abstracts of the 2nd Conference on Solid State Devices and Materials (SSDM). This technique comprises the following steps of depositing polysilicon on a selectively oxidized N-type silicon substrate, by low-pressure chemical vapor deposition (LPCVD), to dope the deposited polysilicon by diffusion of using a POC source 13, depositing a mixture of spun glass (SOG) and resistant product on the doped polysilicon, baking the mixing film, selectively etching the SOG in an extended HF solution leaving polysilicon-resistant product particles, dry-etch the polysilicon using particles of dispersed hard product as etching mask, to remove the p articules of resistant product, and to draw the desired pattern on the

  polysilicon to form a storage electrode.

  As a result, the surface area of the storage electrode is increased by using the resistant product particles remaining on the polysilicon surface as an etching mask to form an etched storage electrode. In addition, the area is increased. of the storage electrode surface by controlling the size of the resistant product particles and the etching time of the polysilicon. The size of the resistant product particles can be controlled by the mixing ratio of the resistant product with the SOG, and by

  the thickness of the mixture deposited on the polysilicon.

  However, since this technique requires using the particles in a uniform size and controlling the coating thickness of the mixture as a function of the mixing ratio of the resistant product with the SOG, problems can be encountered when the electrode is to be etched. In addition, another problem arises from the fact that the etching process must be complicated to increase the surface area. Another conventional technique for increasing the surface area of the storage electrode is described in the MEI, 1990, pages 655-656 (or in the SSDM, 1990, pages 873-876 and in the SSDM, 1990, pages 869- 872), this technique using a memory cell comprising a hemispherical grain storage electrode. This technique makes use of the fact that during the deposition of polysilicon by low-pressure chemical vapor deposition, the polysilicon has, under a certain condition, a rough surface comprising on it bumps or grains

  hemispherical silicon In addition, the document

  above indicates that such a rough surface effectively appears in a narrow temperature range (50 C) in the vicinity of a transition temperature of the polysilicon to pass from a non-crystalline state to a crystalloid state, and that the surface area the storage electrode is doubled compared to that of a conventional polysilicon As this technique can be easily controlled using existing equipment in the temperature range of C, the manufacturing process is simple and

  has a reliable repeatability characteristic.

  In fact, the surface area of the storage electrode only doubles compared to that of the conventional storage electrode. As a result, it is difficult to apply this technique to a high density memory device such as a DRAM of several tens or hundreds of megabits, because of the impossibility of considerably increasing the

  storage capacity in a small limited area.

  The present invention therefore aims to create a storage capacitor which has a high storage capacity in a limited surface area. Another object of the present invention is to create a storage capacitor that has a larger storage electrode surface area.

in a limited surface area.

  Yet another object of the present invention is to provide a storage capacitor which has greater storage capacity in a small area of limited area obtained by a process of storage.

simple manufacture.

  Yet another object of the present invention is to provide a storage capacitor that achieves high reliability and storage capacity in a small area of limited area. Another object of the present invention is to create a storage capacitor which makes it possible to obtain a high storage capacity and a reliable repeatability characteristic in a small

limited surface area.

  For this purpose, the present invention relates, in a first aspect thereof, to a capacitor comprising a first electrode made in a conduction layer formed on a limited surface of a substrate, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer, capacitor characterized in that the first electrode comprises a number of microsisses and / or microcylinders formed on a predetermined surface of the conduction layer. According to another characteristic of the invention, the conduction layer is a polysilicon layer. According to another aspect of the present invention, this relates to a semiconductor memory cell comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a field oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode in contact with the source area, said first electrode covering a predetermined portion of the first conductive layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, a memory cell characterized in that a certain number of microsuneas and / or

  microcylinders are formed on the first electrode.

  According to another characteristic of the invention, the microsaignées and / or the microcylinders are hemispherical in their parts.

background.

  According to yet another aspect of the present invention, this relates to a capacitor formed in a limited surface of a substrate, having a first electrode formed in a conduction layer formed on an insulating layer, a dielectric layer formed on the first electrode , and a second electrode formed on the dielectric layer, capacitor characterized in that: the first electrode comprises a certain number of microsisses and / or microcylinders of the conduction layer, this conduction layer being in contact with the insulating layer in the bottom portions of microsunes and / or microcylinders; and a thin conduction layer covers the conduction layer inside and outside

  microsunes and / or microcylinders.

  According to another characteristic of the invention, the thin conduction layer is polysilicon. According to another characteristic of the invention, the microsunes and / or the microcylinders have a structure in the form of

  screw hole passing through the conduction layer.

  According to yet another aspect of the present invention, this relates to a semiconductor memory cell comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a second conduction layer in contact with the drain zone, this second conduction layer extending over the first insulating layer, a second insulating layer covering the second conduction layer to isolate this second conduction layer, an oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode formed in a conduction layer and coming into contact with the source area, said first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, semiconductor memory cell characterized in that the first electrode comprises a number of microsisses and / or microcylinders of the conduction layer, this conduction layer is in contact with the insulating layer in the bottom portions of microsunes and / or microcylinders; and a thin conduction layer covering the conduction layer inside and outside

  microsunes and / or microcylinders.

  According to another characteristic of the invention, the first conduction layer and the second conduction layer constitute

  respectively a word line and a bit line.

  According to another characteristic of the invention, the microsunes and / or the microcylinders have a structure in the form of

  screw hole passing through the conduction layer.

  According to another characteristic of the invention, the thin conduction layer is polysilicon. According to another characteristic of the invention, the second insulating layer comprises a

flat surface.

  According to yet another aspect of the present invention, this relates to a semiconductor memory cell comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and an insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a field oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode made in a conduction layer and coming into contact with the source area, this first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, semiconductor memory cell characterized by the first electrode comprises a certain number of micro-coils and / or microcylinders of the conduction layer, this conduction layer being in contact with the insulating layer in the bottom portions of the micro-coatings and / or microcylinders; and a thin conduction layer covering the conduction layer inside and outside

  microsunes and / or microcylinders.

  According to another characteristic of the invention, the microsunes and / or the microcylinders have a structure in the form of

  screw hole passing through the conduction layer.

  According to another characteristic of the invention, the thin conduction layer is polysilicon. According to still another aspect of the present invention, this relates to a method of manufacturing a storage electrode comprising a certain number of microsuneas and / or microcylinders, characterized in that it comprises the various steps of: forming grains on a surface of the storage electrode; forming an etching mask layer on the sidewalls of the respective grains; and performing anisotropic etching using the etch mask layer as a mask. According to yet another feature of the invention, this method further comprises the step of removing the cutting edges of the microsaignées and / or microcylinders after the step

anisotropic etching.

  According to still another aspect of the present invention, this relates to a method of manufacturing a storage electrode comprising a certain number of microsuneas and / or microcylinders, characterized in that it comprises the various steps of: flattening a surface of an insulating layer on which the storage electrode is to be formed; forming grains on a surface of the storage electrode; forming an etching mask layer on the sidewalls of the respective grains; performing anisotropic etching by masking the etch mask layer to form screw-hole holes passing through the storage electrode to expose the insulating layer through these holes; and form a thin polysilicon conduction layer covering the inside and the outside of the

holes in the form of screw holes.

  According to yet another aspect of the present invention, this relates to a method of manufacturing a storage capacitor for use in a semiconductor memory device, using a polysilicon layer having a number of grains. hemispherical process, characterized in that it comprises the various steps of: forming an etching mask layer on the upper surfaces of the hemispherical grains; draw a pattern on the polysilicon layer; perform an anisotropic etching using the etch mask layer as a mask and remove the etch mask layer for

to form a storage electrode.

  According to yet another feature of the invention, the above method further comprises a step of oxidizing the upper surfaces of the hemispherical grains to form thereon the

mask layer of engraving.

  According to yet another feature of the invention, the above method further comprises a step of subjecting the polysilicon layer between the two layers to anisotropic etching.

hemispherical grains.

  According to yet another characteristic of the invention, the above method further comprises the various steps of: forming a dielectric layer on the storage electrode; and form a plate electrode on the layer

dielectric.

  According to yet another aspect of the present invention, it relates to a method of manufacturing a first storage electrode in a semiconductor memory device comprising a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a second conduction layer in contact with the drain zone, this second conduction layer extending over the first insulating layer, a second insulating layer covering the second conduction layer to isolate this second conduction layer, an oxide layer formed on the substrate, this field oxide layer being placed in the vicinity of the source zone, the first electrode being constituted by a conduction layer in contact with the source zone, this first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, characterized in that it comprises the various steps of: forming a polysilicon layer in contact with the source area, this polysilicon layer having a number of grains s hemispherical on its surface and covering the second insulating layer; forming an etching mask layer on the upper surfaces of the hemispherical grains; draw a pattern on the polysilicon layer; perform an anisotropic etching using as mask the etch mask layer and

  remove this layer of etching mask.

  According to still another characteristic of the invention, the process above comprises, in addition, a step of oxidation of the upper surfaces of the hemispherical grains to form thereon the

mask layer of engraving.

  According to yet another characteristic of the invention, the method above comprises, in addition, a step of subjecting the polysilicon layer between the two layers to anisotropic etching.

hemispherical grains.

  According to yet another aspect of the present invention, this relates to a method for manufacturing a storage capacitor electrode of a storage capacitor on a flattened insulating layer formed on a semiconductor substrate comprising an active zone, characterized in that it comprises the various steps of: forming on the insulating layer a layer of polysilicon in contact with the active area, this polysilicon layer having a number of hemispherical grains spaced from each other by a predetermined distance; forming an Si N layer on the polysilicon layer; deposit a layer of flattened spinning glass on the Si N layer; subjecting the spinning glass to a retrograde to expose the Si N layer formed on the upper surfaces of the hemispherical grains; remove the exposed Si N layer to expose the upper surfaces of the hemispherical grains; oxidizing the upper surfaces of the hemispherical grains to form thereon an etching mask layer; subjecting the polysilicon layer to anisotropic etching using the etch mask layer as a mask; and

  remove this layer of etching mask.

  According to yet another characteristic of the invention, the method above is characterized in that it further comprises a step of subjecting the layer of anisotropic etching to

  polysilicon located between the hemispherical grains.

  According to yet another aspect of the present invention, this relates to a method for manufacturing a storage capacitor electrode of a storage capacitor on a flattened insulating layer formed on a semiconductor substrate comprising an active zone, characterized in that it comprises the various steps of: forming successively on the insulating layer flattened a first insulating interlayer, a first insulating layer and a second insulating layer; forming a contact hole through the insulating interlayer, the first insulating layer and the second insulating layer, thereby exposing the active area through this hole; forming on the second insulating layer a layer of polysilicon in contact with the active area, said polysilicon layer having a number of hemispherical grains; subjecting the polysilicon layer to etching to draw a pattern; forming on the semiconductor substrate an insulating layer overlying the polysilicon layer and subjecting said insulating layer to retrogravure so as to form an etch mask pattern with the remaining portions of the insulating layer; and subjecting the polysilicon layer to etching using the mask pattern as a mask

engraving.

  According to another characteristic of the invention, the first insulating layer is

nitride.

  According to yet another feature of the invention, the above method further comprises a step of forming the etch mask pattern between the hemispherical grains and the sidewalls of the pattern of the polysilicon layer. According to another aspect, finally, of the present invention, this relates to a method for manufacturing a storage capacitor electrode of a storage capacitor on a flattened insulating layer formed on a semiconductor substrate comprising an active zone, characterized in that it comprises the various steps of: forming successively on the insulating layer flattened a first insulating interlayer, a first insulating layer and a second insulating layer; forming a contact hole through the insulating interlayer, the first insulating layer and the second insulating layer so as to expose the active area through this hole; forming on the second insulating layer a layer of polysilicon in contact with the active area, said polysilicon layer having a number of hemispherical grains; forming a third insulating layer on the polysilicon layer; etching the polysilicon layer and the third insulating layer to form a pattern; etching the predetermined portions of the third insulating layer carrying the pattern, so as to form a first etching mask pattern constituted by the third insulating layer; subjecting the polysilicon layer to an etching of predetermined thickness using as mask the first mask pattern; depositing a fourth insulating layer over the entire surface of the semiconductor substrate; subjecting said fourth insulating layer to retrogravure so as to form a second etch mask pattern with the remaining portions of the fourth insulating layer; and subjecting the polysilicon layer to etching using as mask the second pattern of

engraving mask.

  According to yet another characteristic of the invention, the first etching mask pattern has a smaller size, of a predetermined width, than the polysilicon layer carrying

  the pattern, along its circumference.

  According to another characteristic finally of the invention, the second etching mask pattern is formed between the hemispherical grains and on the sidewalls of the polysilicon layer carrying

the reason.

  The invention will be described in detail below with respect to preferred embodiments with reference to the accompanying drawings in which the same parts are identified by the same references and in which: Figure 1 shows a plan view of a dynamic random access memory (DRAM) cell according to the present invention; Figure 2 shows a sectional view along the line 2-2 of Figure 1; FIGS. 3A to 3C show examples of explanatory diagrams of a manufacturing process of the structure of FIG. 2; Fig. 4A is an enlarged diagram for illustrating an embodiment of a rounded portion 100 of Fig. 3B; FIGS. 4B and 4C are examples of explanatory diagrams of a manufacturing process of a storage capacitor in the case where hemispherical grains are formed continuously as shown in FIG. 4A; Fig. 5A is an enlarged diagram for illustrating another embodiment of the rounded portion 100 of Fig. 3B; FIGS. 5B and 5C are examples of explanatory diagrams of a production process of a storage capacitor in the case where the hemispherical grains are separated from each other by a distance such as that represented in FIG. AT; Fig. 6 is a plan view of another embodiment of a DRAM memory cell according to the present invention; Fig. 7 is a sectional view taken along the line 3-3 of Fig. 6; FIGS. 8A to 8B show examples of explanatory diagrams of a manufacturing process of the structure of FIG. 7; Fig. 9A is an enlarged diagram for illustrating an embodiment of a rounded portion 500 of Fig. 8C; FIGS. 9B and 9C are illustrative diagrams of a process for manufacturing a storage capacitor in the case where hemispherical grains are formed continuously as shown in FIG. 9A; Fig. 10A is an enlarged diagram for illustrating another embodiment of the rounded portion 500 of Fig. 8C; FIGS. 1 OB and 1 OC are examples of explanatory diagrams of a production process of a storage capacitor in the case where the hemispherical grains are separated from each other by a distance such as that indicated in FIG. FIGS. 11A to 11D show further examples of explanatory diagrams of a manufacturing process of the structure of FIG. 7; FIG. 12A is an enlarged diagram for illustrating a rounded portion such as that shown in FIG. 11 B; FIGS. 12B to 12I are examples of explanatory diagrams of a production process of a storage capacitor in the case where the hemispherical grains are separated from each other by a distance such as that represented in FIG. 12 AT; FIGS. 13A to 13F show other examples of explanatory diagrams of a manufacturing process of a storage capacitor according to the present invention; FIGS. 14A to 14H show other examples of explanatory diagrams of a manufacturing process of a storage capacitor according to the present invention; and FIG. 15 is a plan view for illustrating the etching patterns used in FIG. 14C. Referring to FIGS. 1 and 2, a polished oxide layer 12 for defining an area of

  memory cells, is formed on a semi-

  P-type conductor 10 The semiconductor substrate may be a P-type source area A transfer transistor comprising an N-type source area 16 adjacent to the field oxide layer 12, a drain zone 20 of the type N separated from the source zone 16 by an N-type passage zone 18, and a gate electrode 24 disposed on a gate oxide layer 22 over the passage zone 18 and in the vicinity of the source and drain 16 and, is formed in an active zone 14 placed on a main surface of the semiconductor substrate 10

  surrounded by the field oxide layer 12.

  The gate electrode 24 is connected to a word line 26 A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent active area is formed on the field oxide layer 12 L gate electrode 24 is isolated from word line 28 by an insulating oxide layer 30 Insulating oxide layer 30 includes an opening 32 for exposing a portion of source area 16 A first electrode of an electrode storage 36 comes into contact with the source area 16 in a source contact area 34, through the aperture 32, and defines the storage capacitor area 38 by extending over the adjacent gate electrode 24 and on the line of

words 28.

  According to the feature of the present invention, the upper portion of the storage electrode 36 has a number of microsisses or microcylinders so as to increase the surface area of the electrode of

  storage, as will be described in more detail below.

  A dielectric layer 40 is formed on the surface of the storage electrode 36 and a plate electrode layer 42 is formed on the dielectric layer 40. As a result, the storage capacitor 44 includes the storage electrode 36, the Dielectric layer 40 and plate electrode layer 42 A protective layer 46 is formed on a second electrode of the plate electrode 42 and an exposed portion of the insulating oxide layer 30. opening adjacent to the drain region 50 of the transfer transistor and intended to expose a zone Ne strongly

  doped 48 extending over the surface of the semiconductor substrate.

  A bit line 52 made of a conductive material comes into contact with the N + area 48 at a contact area 54 of the bit line, through the aperture 50, and intersects the lines words 26, 28 extending over the protective layer 46 in the form of a strip A second protective layer (not described) is deposited on the line of

bits 52.

  As described above, a DRAM memory cell according to the present invention comprises a transistor and a capacitor. The capacitor is a stacked capacitor having a storage electrode provided with multiple micro-bubbles in an area of 0.4 x 1.2 pim 2 occupied. However, it will be appreciated that the present invention is not limited to expanding the surface of the storage electrode. Referring to FIGS. 3A to 3C, 4A to 4C, and 5A and 5C, there will be described in detail a process for manufacturing the DRAM memory cell according to the invention. However, as the operation of the cell of DRAM memory is well known to the

  technical description, its detailed description will not be

  reprise. Referring to Figure 3A, this shows a pair of transfer transistors formed on the semiconductor substrate. Although it is well known, the fabrication process of the transistors will be described briefly for reference. Substrate 10 is a P-type source having a concentration of 45 x 1016 atoms / cm 3 formed on a P-type silicon chip having a crystal surface <1.0>, and a concentration of 1 x 1015 atoms. / cm 3 The field oxide layer 12 of 3000 of thickness 1 A = 10-10 m is formed on a

  part of the substrate 10 to define the active zone 14.

  Then, the 150 A thick gate oxide layer 22 is formed on the semiconductor substrate in the active area 14 by conventional dry O 2 oxidation, and a phosphorus doped polysilicon layer is deposited on the semiconductor substrate for forming the gate electrode 24 After the deposition of the polysilicon, the gate electrode 24 or word line 26, and the word line 28 are drawn by conventional photoengraving. According to the drawing formation process, the gate oxide layer located elsewhere than in the lower part of the gate electrode 24 and word lines 26, 28, is removed to expose the substrate placed in the active zone 14. Then, a dose of 1, 6 x 1013 ions / cm of phosphorus ion is implanted under 60 Ke V to form the source and drain zones 16, 20 After the implantation of the phosphorus ions, an insulating layer 30 of SiO 2 of 2700 t thick is deposited uniformly by chemical vapor deposition low pressure at about 8200 C to isolate the gate electrode 24, the word lines 26, 28 and the zones

  source and ion-implanted drain 18, 20.

  Referring to Fig. 3B, after forming the insulating oxide layer 30, the aperture 32 for exposing a portion of the surface of the source area 16 is formed through the insulating oxide layer 30 by the conventional photoengraving method After removing the photoresist used to form the aperture 32, a layer of polysilicon 56 having a thickness of 2500 having a number of hemispherical grains on its surface is formed on the substrate in contact with the area Source contact 34 through opening 32 Polysilicon having such a surface structure can be deposited by low pressure chemical vapor deposition using Si H 4 (20%) supplemented with helium at 5500 C under atmospheric pressure. 1 bar (see IEEE Trans, on Electron Devices, Vol. ED-36, No. 2, pages 351-353, 1989, or SSDM, pages 873-876, 1990) Alternatively, the polysilicon layer 56 can be made by depositing a diaper of polysilicon about 1 oo o thick in conventional temperature conditions (greater than 600 ° C) to deposit the polysilicon, and then forming on the polysilicon surface, a polysilicon layer of about 1500 d thickness having a number of hemispherical grains on its surface It is preferred that the diameter or height of the hemispherical grains be from about 0.07 to 0.15 micrometers (PM). After formation of the polysilicon layer 56, an arsenic ion dose of 3 × 10 15 ions / cm 2 is implanted in 100 Ke V to dope the polysilicon layer 56 Although the polysilicon layer 56 can be doped with impurities of phosphorus, it is however preferable to carry out the doping with arsenic impurities so as to form a good microsonde structure on the polysilicon strain 56 A SiO 2 mask layer 58 of thickness 300 is then deposited on the doped polysilicon layer 56, by a conventional chemical vapor deposition A high permittivity dielectric substance such as Si 3 N 4 or T 2 to 05 can be used for the mask layer 58 However, in view of the etching process used to to form the microsaignées, it is preferable to use a dielectric substance having a selectivity

  high polysilicon / dielectric substance.

  After deposition of the mask layer 58, a patterning process of the desired pattern is carried out to define the storage capacitor zone 38, this operation being performed by the conventional photogravure process. As a result, the drawn polysilicon layer 56 is formed. microsunes such as those shown in Figure 3B, and the

  comic mask layer 58 of Si O 2.

  In the following, with reference to FIGS. 4A-4C and 5A-5C, an etching process for forming microsubes according to the present invention will be described in detail. FIGS. 4A and 5A are enlarged diagrams for to illustrate different embodiments of a rounded portion 100 described respectively in Figure 3 B. Figure 5 A shows the arrangement of the grains in the case where the distance S between the hemispherical grains is greater than twice the thickness X of the mask layer 58 of Si O 2 (ie Sk 2 X), and FIG. 4 A represents the arrangement of

  grains in the case where the distance S is zero.

  In practice, if the polysilicon layer 56 is deposited by low-pressure chemical vapor deposition in a temperature range within which the polysilicon layer 56 passes from the non-crystalloid state to the crystalloid state, the distance S between the grains becomes a mixture of the states corresponding to the case S = O and the case S> 2 X Thus, it will be noted that it is possible to obtain at the same time the grain arrangements represented in FIGS.

5 A.

  Referring to FIG. 4A, an Si O 2 retrogravure process used to form a side wall for LDD MOSFET (MOSFET with Slightly Doped Drain) is used on the polysilicon oxide layer 58, in order to stop the etching at the thickness X (= 300) When depositing the layer 58 of Si O 2, as this layer of Si O 2 is deposited in a greater thickness in the recesses between the polysilicon grains, the result of the retrogravure process is such that the etching mask 62 remains and the upper portions 66 of the grains are exposed as indicated in FIG. 4 B. Next, anisoptropic etching is carried out, the selectivity of the polysilicon / SiO 2 being of 40, so as to form 0.2 μm thick grooves Such etching is performed using LAM Co Model No "Rainbow 4400" at a power of 200 watts at an atmospheric pressure of 350 millibar, with use of a gaseous mixture of HBR (hydro-bromide): C 12 = 40 SCCM: 120 SCCM As a result, cylindrical intermediate-l-shaped grooves are formed in the polysilicon as shown in FIG. 4C, and hemispherical portions 64 corresponding to the exposed grains 66 are formed in the bottom surfaces of the grooves, which thus further increases the surface area of the storage electrode 36 After formation of these microsaignées, a layer of Si O 3 N is formed 4 about 70 thick on the surface of the storage electrode by the conventional chemical vapor deposition method, and a dielectric layer 40 of structure NO (or structure ONO is deposited if it is added a layer of SiO 2 naturally oxidized) of about 20 Si O 2 thickness obtained by hot oxidation of the surface of the Si 3 N 4 layer. Next, a doped polysilicon layer is formed on the dielectric layer 40 by the classical technique and the layer of doped polysilicon is drawn by the technique of photoengraving

  conventional for forming the plate electrode 42.

  In the case of FIGS. 5A to 5C, after retrogravure of the mask layer 58, an etching mask layer 62 is formed on the sidewalls of the respective grains 60, as shown in FIG. 5B, and the upper portions 66 of the grains 60 and the surface portions 68 of the polysilicon layer 56 disposed between the grains are exposed. Sub-micron etching is then carried out, thereby forming the microcylinder storage electrode 36. In this case also, the hemispherical portions 64 which correspond to the shape of the exposed upper portions 66, are formed in the bottom surface of the cylinders 70. However, the bottom surfaces 80 of the Microcylinders 70 are etched deeper than the hemispherical portions 64. As a result, the manufacture of the micro-coils or microcylinders can be carried out by the self-etching process. without using the photoresist, which simplifies the manufacturing process. In the case where the structure of FIG. 4A and the structure of FIG. 5A are mixed, it is possible to obtain a certain number of microcylinders and poles comprising a certain number of

  microsuned, after anisotropic etching.

  Then, the dielectric layer 40 of structure N-O or structure O-N-O, and the plate electrode 42, are formed on the surface of the electrode

  storage 36 according to a predetermined process.

  The fabrication process of the stacked capacitor in which the SiO 2 etching mask layer 62 is disposed on the upper surface of the storage electrode 36 has been described. However, since the etch mask layer 62 can not play the As a function of the dielectric layer, it is preferable to remove the etch mask layer 62. This etch mask layer 62 of SiO 2 may be removed in an extended HF solution after

anisotropic etching process.

  In general, after the anisotropic etching, sharp edges remain in the engraved edge portions. Cutting edges may also be formed around other parts than the edge portions etched by the anisotropic etching. The existence of these cutting edges prevents formation. the thin dielectric layer 40 covering the storage electrode 36, and furthermore causes a decrease in

  the breakdown voltage of the storage capacitor.

  A process can be used to round the cutting edges before forming the dielectric layer 40 and after removing the etch mask layer 62 (in the case of a stacked capacitor without the etch mask layer 62). an Si O 2 layer approximately 10 thick on the storage electrode 36 by immersing the substrate in a solution consisting of a mixture of HCL: H 202: H 20 = 1: 1: 6, at a temperature of 600 C to 800 C The cutting edges are then removed by removing, by the extended HF solution, the oxide layer formed during the chemical oxidation process. The embodiment according to the present invention forms a 2,500-thick layer of polysilicon 56 having the hemispherical grains, and

  engraves the grooves at the depth of 2000.

  However, it should be noted that the present invention is not limited to these numerical values. By increasing the thickness of the polysilicon layer 56 and by etching the grooves more deeply according to the selectivity of the polysilicon / dielectric substance, it is possible to increase the

  surface area of the storage electrode 36.

  Referring again to FIG. 3C, this represents the electrode plate 42 described above. The following process is a casting resumption process for depositing the protective layer

  such as a layer of VBPS (Boro-Phospho-

  Silicate) or VPS on the substrate 10 so as to flatten the device Next, the aperture 50 is formed by the conventional technique as shown in FIG. 2, and an N + area 48 is formed through the aperture 50. bit line 52 in

  aluminum is formed in contact with the zone N + 48.

  In the embodiment according to the present invention, the bit line 52 extends over the transfer transistor and the stacked capacitor 44, while the

  gate of the transfer transistor is polysilicon.

  However, it will be appreciated that the present invention is not limited to such a structure. Furthermore, the polysilicon forming the first electrode can be

  replaced by recrystallized silicon.

  It is also possible to use the present invention to form a groove in a semiconductor substrate and then to form a

  condenser stacked in the groove.

  In addition, if a storage capacitor with a high storage capacity is required in a limited area on an insulated substrate, the capacitor can be made by forming a multiple microsonde storage electrode on the substrate.

  isolated, forming a dielectric layer on this

  ci and then finally forming a plate electrode on

the dielectric layer.

  Examples have been described of the storage electrode structure and the process of

  manufacture thereof according to the present invention.

  However, different embodiments can be obtained without departing from the scope of the present invention. Reference will now be made to various possible embodiments of the present invention.

EXAMPLE 1

  Referring to FIGS. 6 and 7, these represent another embodiment of a DRAM memory cell according to the present invention, in which a field oxide layer 12 for defining the memory cell area, is formed on a P-type semiconductor substrate 10. The semiconductor substrate 10 may be a P-type source area A transfer transistor comprising an N-type source area 16 adjacent to the field oxide layer 12 , an N-type drain zone 20 separated from the source zone 16 by a passage zone 18 N, a gate oxide layer 22 formed on the passage zone 18, and a gate electrode 24 disposed on the layer gate oxide 22 in the vicinity of the source and drain regions 16 and 20 is formed in an active zone 14 placed on a main surface of the semiconductor substrate 10 and

  surrounded by the field oxide layer 12.

  The gate electrode 24 is connected to a word line 26 A word line 28 connected to a gate electrode of a transfer transistor formed in an adjacent active area is formed on the field oxide layer 12 L gate electrode 24 is isolated from the word line 28 by a first insulating layer 30 The first insulating layer 30 includes an opening 135 through which the drain region of the transfer transistor comes into contact with a bit line 150 An opening 125 is formed in the first insulating layer 30 and in a second insulating layer 190 covering the bit line 150 The surface of the second insulating layer 190 is flattened A storage electrode 200 comes into contact with the source area 16 in a source contact 18, through the aperture 125, and defines the storage capacitor zone extending over the adjacent gate electrode 24 and the line

of words 28.

  According to the feature of the present invention, an upper portion of the storage electrode 200 has a number of microsisses or microcylinders so as to increase the surface area of this electrode.

  storage, as will be described in more detail below.

  A dielectric layer 40 is formed on the surface of the storage electrode 200 and a plate electrode layer 400 is formed on the dielectric layer 40. Such a DRAM memory cell is an application of a DASH structure diagonally active stack capacitor with strongly stacked storage node) in which a bit line is formed below the storage capacitor The DASH structure is very well described in the MEI 1988, pages 596-599 In a DRAM memory cell having the DASH structure, as one can conceive an expansion of the storage capacitor in the horizontal direction without limitation of the rule of the bit line design, one can easily increase the storage capacity of the capacitor by a simple process, compared to the case of a DRAM memory cell in which the storage capacitor is formed below the bit line. it very largely the storage electrode 200 defining the storage capacitor zone, as long as this electrode does not come into contact with the electrode of storage

  storage of a neighboring storage capacitor.

  Reference will now be made to FIGS. 8A to 8D, 9A to 9C and 10A to 10C to describe a manufacturing process of the DRAM memory cell of FIG. 7. Referring to FIG. discloses a process for manufacturing a pair of transfer transistors and the bit line 150. The process, before the formation of the bit line 150, is the same as the process described with reference to FIG. bit line 150 is formed on the first insulating layer 30, it is preferable to flatten the surface of this first insulating layer using a resumption of casting process such as the VBPS process. Then, a part of the first insulating layer 30 formed on the drain zone 30 is removed by the conventional photoengraving process so as to form the opening 135 through which the drain region 20 of the transfer transistor is connected to the bit line 150 in

aluminum.

  Referring to FIG. 8B, after forming the bit line 150, a second insulating layer 190 of VBPS or VPS is deposited with a thickness of about 5000 on the substrate, then respreaded to flatten the surface. The second layer insulator 190 is generally constituted by a silicon oxide or by stacked layers of silicon oxide and silicon nitride. In both cases, the surface flattening process must be carried out after the deposition of the second insulating layer. , the flattening process can be carried out by depositing a layer of silicon oxide on the substrate, depositing thereon particles of resistant product, and then etching it with a controlled etching rate of the particles of

  resistant product and silicon oxide layer.

  Referring to FIG. 8C, as the formation and flattening of the second insulating layer 190 is completed, the aperture 125 for exposing a portion of the surface of the source area 16 is formed through the second layer insulating 190 and the first insulating layer 30 by the conventional photoengraving process After removing the photoresist used to form the aperture 125, the 2,500-thick polysilicon layer 56 having hemispherical grains on its surface, is formed on the second insulating layer 190 so as to come into contact with the surface of the source zone 16, as described with reference to FIG. 3B. After the formation of the polysilicon layer 56, the implantation of the arsenic ions for doping the polysilicon layer, as described in FIG. 3B. Then, a mask layer 250 of Si O 2 is deposited on the doped polysilicon layer 56, with a thickness of approximately 300 μm. at 500 by the conventional chemical vapor deposition process A high permittivity dielectric substance such as Si 3 N 4 or Ta 205 can be used for the mask layer 58. However, in view of the etching process for forming the microsoluées, It is preferable to use a dielectric substance having a high selectivity of the polysilicon / dielectric substance. After the deposition of the mask layer 250, a patterning process of the desired pattern is carried out to define the capacitor zone of the

  storage by the process of conventional photoengraving.

  A microsuction formation process according to the present invention will be described in detail below with reference to Figs. 9A and 10A, which are enlarged diagrams for illustrating different embodiments of a rounded portion 500 described respectively in FIG. FIG. 10A shows the arrangement of the grains in the case where the distance S between the hemispherical grains is greater than twice the thickness X of the mask layer 250 of SiO 2 (that is to say Sk 2 X), and Figure 9 A represents the arrangement of

  grains in the case where the distance S is zero.

  Referring to FIG. 9A, an Si O 2 retrogravure process is used to form a sidewall for the fabrication of a conventional LDD MOSFET (Light Doped Drain MOSFET) on the SiO 2 oxide layer. polysilicon 250, so as to stop the etching at the thickness X (= 300 to 500 k) of the SiO 2 layer 250. This process is the same as the process of FIG. 4B. If O 2, as this layer of Si O 2 is deposited in a greater thickness in the recesses between the polysilicon grains 221, the result of the retrogravure process is such that the etching mask 251 remains in the recesses and that the parts upper 222 grains 221 are exposed. Referring now to FIG. 9B, anisotropic etching is carried out, the selectivity of the polysilicon / SiO 2 being 40, in order to completely eliminate the layer of polysilicon 56 of 2500 of thickness so as to expose the second layer.

  insulation 190 other than in the part situated

  This etching is performed using LAM Co Model No "Rainbow 4400", at a power of 200 watts and at an atmospheric pressure of 350 millibars, with

  use of a mixture of HBR gas (hydro-

  bromide): c 12 = 40 SCCM: 120 SCCM As a result, the microsunes 230 having a screw hole structure and passing through the polysilicon layer 56 are formed. It will be appreciated that this embodiment is different from the process of FIG. 4 C in that the depth of the grooves of FIG. 4C is 0.2 micrometers while the depth of the

  holes of this embodiment is 2500.

  After having formed the micro-shaped holes in the form of a screw hole 230, a layer of doped thin polysilicon 230 is uniformly deposited on the inside and the outside of the microsaignées 230 by deposition of low-pressure chemical vapor at the deposition rate of 20 to minute in the Si H 4 decomposition gas, at a temperature above 6000 C for which the polysilicon is formed Since the effective thickness of the thin polysilicon layer 240 must be less than half the diameter (0.07 to 0.15 micrometer) of the hemispherical grain 221 to ensure the sufficient surface area of the storage capacitor, it is preferable that the thickness of the

  thin polysilicon layer 240 is 300 to 700 k.

  A patterning process is performed on the thin polysilicon layer 240 formed over the entire surface of the substrate by the conventional photoengraving process so as to define the surface of the storage capacitor and form the storage electrode 200. subsequently, the storage electrode 200 comprising the polysilicon layer 56 and the thin polysilicon layer 240, includes the microshares

multiples 230.

  Referring now to FIG. 9C, after forming the storage electrode 200, a layer of Si 3 N 4 about 70 thick is formed on the surface of the polysilicon layer 240 (or storage electrode 200) by the conventional chemical vapor deposition method, and there is deposited thereon a dielectric layer 40 of structure NO (or of structure 0-NO if an Si O 2 layer is added thereto) 20 k SiO 2 thickness obtained by hot oxidation of the surface of the Si 3 N 4 layer. Next, the doped polysilicon layer 400 is formed on the dielectric layer 40 to complete the fabrication of the capacitor. 8 Meanwhile, Figures 10A to 10C show another embodiment of the invention.

  storage capacitor according to the present invention.

  In this case, after retrogravure of the mask layer 250, an etch mask layer 251 is formed on the sidewalls 225 of the respective grains 221, as shown in FIG. 10A, and the upper portions 222 are exposed. grains 221 and the surface portions 226 of the polysilicon layer 56 disposed between the grains 221. Subsequently, micrometer-sized etching is performed on the polysilicon layer 56 to expose the second insulating layer 190, and the thin polysilicon layer 240 on the entire surface of the substrate Next, the pattern of the storage electrode 200 is drawn as shown in FIG. 1 OB. In addition, the dielectric layer and the plate electrode 400 are successively formed on the same surface. electrode

storage 200.

  It will be noted, for a specialist in the subject, that even in the case where the distances between the hemispherical grains are not uniform, the storage capacitor can be produced by the above process according to the present invention. It will further be noted that it is not necessary to carry out a precise control of the etching depth to form the microsaignées, because one forms the thin polysilicon layer 240 intended to constitute the storage electrode 200 after having completely removed the polysilicon 56 elsewhere than in the parts below the etch mask layers 251 with a high selectivity of the

polysilicon / silicon oxide.

  In the foregoing, consider an example in which the storage electrode comprises silicon oxide used as an etching mask. However, since the etch mask layer 251 does not play the role of the dielectric layer nor can it increase the surface area of the storage capacitor, it is preferable to remove the etch mask layer 251 by etching anisotropic and by plunging the electrode into the

extended HF solution.

  Although the embodiment described with reference to FIG. 7 represents a DRAM memory cell having the DASH structure in which the bit line is formed below the storage capacitor, the present invention is not limited to a For example, this embodiment may be applied to the DRAM memory cell of FIG. 2 In this case, before depositing the polysilicon layer 56 serving as the storage electrode 36, the insulating layer 30 formed must be flattened. below the layer of

polysilicon 56.

EXAMPLE 2

  An alternative embodiment of the present invention will now be described with reference to FIGS. 1A to 11D and 12A to 12I. First, with reference to FIG. second insulating layer 190, the 2500 k thick polysilicon layer 56 comprising the hemispherical grains on its surface, so that they come into contact with the source zone 16 through the opening 125, then the implantation is carried out Next, with reference to FIG. 11B, a layer of Si N 330 approximately 20 to 500 k thick is deposited on the polysilicon layer 56 by the low pressure chemical vapor deposition method. conventional, and depositing a layer of spinning glass 340 about 2000 k thick on the Si N layer 330 As the thickness of the spinning glass layer 340 is much greater than the height of the grains hemispherical, the rough surface of the polysilicon layer 56 is complete completely covered by the

spinning glass layer 340.

  Fig. 12A is an enlarged diagram for illustrating the rounded portion of Fig. 11B. In Fig. 12B, after having deposited and flattened the spinning glass layer 340, this layer 340 is demoted or dry-etched to expose the upper portions 331 of the hemispherical grains 221 whose surfaces are covered with the layer of Si N 330 The exposure of the layer of Si N 330 can be accurately controlled by the duration and extent of the etching in FIG. 12C, the exposed Si N layer 331 is removed by dry etching using LAM Co Model No "Rainbow 4400", or by wet etching using phosphoric acid (H 3 PO 4). completely withdraws the remaining spinning glass layer 342, as shown in FIG. 12D, by dipping the substrate into an extended etching solution for about one minute. Referring to FIG. 12E, the upper portions of the hemispherical grains 221 of the exposed polysilicon layer 56 are oxidized to form an oxide layer 231 of 100 to 1000 of thickness. This oxidation process can be carried out using Dry 02 or by dipping the substrate in a solution of a mixture of HCL: H 202: H 2 O = 1: 1: 6 at a temperature of 80 CA at this time, a thin oxide layer 232 is also formed on the Si N 330 layer, but this oxide layer can be easily removed by dipping the substrate into an extended etching solution for about 10 seconds. The oxide layer 231 is used as an etch mask to form after the oxidation process, the Si N 330 layer remaining on the hemispherical grains 221 and on the polysilicon layer 56 is removed by immersing the substrate in a solution of H 3 PO 4 as indicated in FIG. Referring again FIG. 11C, after having formed the etching mask 231 of the oxide layer, the pattern is drawn on the polysilicon layer 56 by the conventional photogravure process, so as to form the storage electrode. in the design of the above pattern, that since the polysilicon layer 56 is formed on the bit line 150, expansion of the surface area of the storage capacitor can be achieved without limitation of the rule

of the line of bits.

  Referring now to FIG. 12G, the anisotropic etching is carried out, the polysilicon / Si 2 O selectivity being 40, on the polysilicon layer 56 to the thickness of 0.2 micrometer, using the layer The etching mask 231 is etched using the LAM Co Model No. "Rainbow 4400", at a power of 200 watts and at an atmospheric pressure of 350 millibars, using a gas mixture of HBR (hydro-bromide): C 12 = 4 OSCCM: 12 Bc M C As a result, microsunes 224 are formed having the rounded portions which correspond to the shape of the grains in the lower parts, as shown in FIG. In such a structure, it is possible to improve the coverage characteristics of the steps of the dielectric layer formed on this structure, compared with the other structures. Now, as shown in FIG. 12H, the etching mask layer 231, which can not serve as a dielectric layer, is removed to complete the fabrication of the storage electrode 201. It will be noted that the surface of the storage electrode 201 from which the etching mask layer 231 has been removed, is well rounded and no longer comprises the cutting parts. Thus, a good quality dielectric layer is deposited so as to avoid the unwanted reduction in the breakdown voltage of the capacitor.

storage.

  Next, a layer of Si 3 N 4 about 70 thick is formed on the surface of the storage electrode 201 by the conventional chemical vapor deposition method, and a dielectric layer is deposited thereon. 40 of structure NO (or structure ON-O) if we add a layer of SiO 2 naturally oxidized) 20 thick Si O 2 obtained by hot oxidation of the surface of the Si layer 3 N 4 The layer 400 of doped polysilicon is then formed on the dielectric layer 40 to complete the fabrication of the storage capacitor shown in FIG. 12 I. Next, a protective layer 46 such as a layer of VBPS (Boron Glass) Phospho-Silicate) or VPS is deposited on the substrate 10, and a casting recovery process is carried out to flatten the device. As a result, the DRAM memory cell shown in FIG. embodiment above, the thickness of the polysilicon layer 220 As storage electrode, is 2500, and the depth of the grooves is 2000 k However, it should be noted that the present invention is not limited to these numerical values by increasing the thickness of the polysilicon layer 56 and By etching the grooves more deeply according to the selectivity of the polysilicon / silicon oxide, the surface area of the storage electrode 201 must be further increased. Of course, the embodiment according to the present invention can be applied to a storage electrode in which distance between grains

hemispherical is nil.

EXAMPLE 3

  Reference is still made to FIGS. 13A to 13F, 14A to 14H and 15 to represent another form of

  embodiment of the present invention.

  First, with reference to FIG. 13A, a gate electrode 24 and a word line 28 are formed on a semiconductor substrate 10 of a first type of conduction, in the same manner as in the case of FIG. FIG. 3A Then, a first insulating interlayer 600 such as a VBPS layer or an oxide layer is deposited over the entire surface of the substrate 10, and the resulting structure is flattened. A first insulating layer 610 of 500 to 1000 of thickness such that a nitride layer, and a second insulating layer 620 1000 to 2000 A thick such as an oxide layer, are deposited successively on the first insulating interlayer 600 The first layer insulator 610 of nitride is used as an etch stop layer in the

process that must follow.

  FIG. 13B shows a process for forming a first contact hole CH 1 and a first conductive layer 56 made of polysilicon. A photoresist pattern of the desired shape is produced on the second insulating layer 620 by the following process which consists in covering the photoresist and exposing / drawing the photoresistor Using the photoresist pattern, the first insulating layer 610, the second insulating layer 620 and the first insulating interlayer 600 are etched to form the first contact hole CH 1 which connects the storage electrode used as the first electrode of the storage capacitor,

  at the source area 16 of the transfer transistor.

  After having removed the photoresist pattern, a layer of doped polysilicon 56 having a thickness of 2000 to 6000 having hemispherical grains on its surface is deposited on the entire surface of the substrate 10. In FIG. 13B, the grains are connected to the adjacent grains, that is to say that the distance S between the grains is zero as indicated in FIGS. 4A and 9A. However, the present invention can also be applied to a storage electrode in which the grains are separated from one another by a certain distance, as indicated in the forms of

previous realization.

  FIG. 13C shows a process for forming a pattern on the photosilicon layer and on a third insulating layer 630. Firstly, a photoresist pattern of the desired shape is produced on the first polysilicon conduction layer 56 by successive operations of covering the photoresistor and exposing / drawing the photoresistor Using the photoresist pattern, the first polysilicon conduction layer 56 is etched to form the pattern 56 'of the polysilicon layer having the hemispherical grains on its surface By successive operations, the photoresist pattern is removed and the third insulating layer 630 of an OHT (High Temperature Oxide) of 300 to 1000 o of thickness is deposited over the entire surface of the film.

substrate 10.

  FIG. 13D shows an etching process of the third insulating layer 630. Back-etching is performed on the substrate 10 to expose the upper portions of the grains of the polysilicon pattern 56. As a result, the third insulating layer 630 remains between the grains. , the remaining third insulating layer 630 'is on

  the side walls of the polysilicon pattern 56 '.

  Fig. 13E shows a process of forming the storage electrode. Using the remaining third insulating layer 630 'as a mask, the photosilicon pattern 56' is etched to form a storage electrode 202. As a result, the storage electrode 202 is provided with microsunes or microcylinders formed in areas of the photosilicon pattern 56 'which are not covered by the remaining third insulating layer 630'. Furthermore, during the etching process of the storage electrode, the wall portions In this case, the etching of the polysilicon unit 56 'is carried out by a gaseous mixture of Hbr or C 12 having a negative pressure.

  high polysilicon / oxide etch selectivity.

  Fig. 13F shows a storage capacitor forming process After the process of Fig. 13E, the remaining third insulating layer 630 'used as a mask is removed by the wet etching process using an acid etching solution extended or extended HF solution Then, the dielectric layer 40 of structure ONO (Oxide-Nitride-Oxide) or of structure NO, is deposited on the entire surface of the exposed storage electrode 202. A second layer of polysilicon conduction doped on the dielectric layer 40, and the pattern is drawn on this layer to form the plate electrode 400 As a result, this completes the process of forming a storage capacitor consisting of the storage electrode 202, of the layer

  dielectric 40 and plate electrode 400.

  Next, a bit line is formed by exposing the upper part of the drain zone 20 (not shown). The bit line can be formed before forming the first conduction layer of the electrode.

storage 202.

  Reference is still made to FIGS. 14A to 14H to represent another embodiment according to

the present invention.

  The process of FIG. 14A is the same as the process of FIG. 13AA. FIG. 13B successively forms the first contact hole CH 1, the polysilicon layer 56 and the third insulating layer 640, as described in FIG. FIG. 13B Then, in FIG. 14C, a photoresist pattern 700 of desired shape is formed on the third insulating layer 640 by a process consisting successively in covering, exposing and photograding the photoresistor Next, using the photoresist pattern as a mask the third insulating layer 640 and the polysilicon layer 56 are etched to form a polysilicon pattern 56a as shown in the drawing. The third insulating layer 640 is also etched along the polysilicon pattern 56a. wet etching using an extended acid etching solution or an extended HF solution, so as to form a pattern 640a of the third insulating layer. In this case, the etching depth used to form the pattern 640a of the third insulating layer,

  corresponds to a thickness of about 500 to 1000.

  Reference will now be made to FIG. 15 to more clearly describe zone A of FIG. 14C. The pattern 56a of the polysilicon layer and the pattern 700 of the photoresistor have the same size. The pattern 640a of the third insulating layer presents a smaller size, of a predetermined width, than the pattern 56a of the polysilicon layer along its circumference In FIG. 14D, the photoresist pattern 700 of FIG. 14C is removed and the pattern is etched 56 a of the polysilicon layer using the pattern 640 a of the third insulating layer as a mask, so as to form the nipples B along the circumference of the pattern 56 a of the polysilicon layer in FIG. the pattern 640a of the third insulating layer, and depositing a high temperature oxide film constituting a fourth insulating layer 650 of 500 to 1000 k of thickness, over the entire surface of the substrate 10 A process of removing the reason for e the third insulating layer before depositing the

  fourth insulating layer, is unimportant.

  Then, in FIG. 14F, a back-engraving is performed on the substrate 10 on which the fourth insulating layer 650 is formed, so that the pattern 650a of the fourth insulating layer remains between the grains and on the side walls of the pattern 56 It will be appreciated that a spacer 651 made of the remaining fourth insulating layer is formed on the nipples B. The spacer 651 is used to form microcylinders along the sidewalls of the polysilicon. storage electrode in this last process. Now, in FIG. 14G, the pattern 56a of the polysilicon layer is etched to a thickness of about 4000 by using the pattern 650a of the fourth insulating layer as a mask, so as to complete the structure of the electrode storage 204 including

  microsunes and / or multiple microcylinders.

Next, in FIG. 14H, the pattern 650a of the remaining fourth insulating layer and the spacer 651 are removed. Finally, the dielectric layer 40 is deposited on the storage electrode 204 and the polysilicon doped on the layer

  dielectric 40 to form the plate electrode 400.

  This allows to complete the process of

  manufacture of the storage capacitor.

  Although we have represented and described

  On top of different structures of a storage capacitor according to the present invention, it will be apparent to one skilled in the art that various modifications are possible without departing from the scope of the present invention. For example, the present invention can be used to form a groove in a semiconductor substrate and then for

  then form a capacitor stacked in the groove.

  In addition, in the case where a capacitor with high storage capacitance is to be used in a limited area of an insulated substrate, this requirement can be met by forming a storage electrode with multiple micro-bubbles in accordance with the present invention. by forming a dielectric layer on this storage electrode, and forming a

  plate electrode on the dielectric layer.

  As can be seen from the

  description above, a storage capacitor

  according to the present invention has a storage electrode having a larger area in a limited area of surface, which thus allows to increase the storage capacity Moreover, as microsuneas and / or microcylinders are formed with good uniformity, this makes it possible to obtain a capacitor of very high reliability. Finally, it will be noted that the process according to the present invention is

comparatively simple.

Claims (8)

1) Capacitor comprising a first electrode made in a conduction layer formed on a limited surface of a substrate, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer, capacitor characterized in that the first electrode comprises a number of microsisses and / or microcylinders formed on a predetermined surface of the conduction layer. ) Capacitor according to claim 1, characterized in that the conduction layer is a polysilicon layer. A semiconductor memory cell comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a field oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode in contact with the source area, said first electrode covering a predetermined portion of the first conductive layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, a memory cell characterized in that a certain number of microsuneas and / or microcylinders are formed on the first electrode. ) Semiconductor memory cell according to claim 3, characterized in that the microsaignées and / or the microcylinders are hemispherical in their bottom portions. A capacitor formed in a limited surface of a substrate, having a first electrode formed in a conduction layer formed on an insulating layer, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer, capacitor characterized by the first electrode comprises a certain number of micro-coils and / or microcylinders of the conduction layer, this conduction layer being in contact with the insulating layer in the bottom portions of the micro-coatings and / or microcylinders; and a thin conduction layer covers the conduction layer inside and outside the microsunes and / or microcylinders.   6) Capacitor according to claim 5, characterized in that the thin conduction layer is in polysilicon.   ) Capacitor according to claim 5, characterized in that the microsaignées and / or the microcylinders have a structure in the form of   screw hole passing through the conduction layer.   80) A semiconductor memory cell comprising a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a second conduction layer in contact with the drain zone, this second conduction layer extending over the first insulating layer, a second insulating layer covering the second conduction layer to isolate this second conduction layer, an oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode formed in a conduction layer and coming into contact with the source area, said first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, semiconductor memory cell characterized in that the first electrode comprises a certain number of microsisses and / or microcylinders of the conduction layer, this conduction layer and in contact with the insulating layer in the bottom portions of the microsunes and / or microcylinders; and a thin conduction layer covering the conduction layer inside and outside   microsunes and / or microcylinders.   9 ') semiconductor memory cell according to claim 8, characterized in that the first conduction layer and the second conduction layer respectively constitute a line of words and a line of bits.   10) semiconductor memory cell according to claim 8, characterized in that the microsaignées and / or microcylinders have a screw hole structure passing through the conduction layer.   11) semiconductor memory cell according to claim 8, characterized in that the   Thin conduction layer is polysilicon.   12) semiconductor memory cell according to claim 8, characterized in that the   second insulating layer has a flattened surface.   13) Semiconductor memory cell comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a 3-pass region formed between the source and drain regions, and an insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a field oxide layer formed on the substrate, said field oxide layer being placed in the vicinity of the source area, a first electrode made in a conduction layer and coming into contact with the source area, this first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer overlying the first electrode, and a second electrode overlying the dielectric layer, a semiconductor memory cell characterized by the first electrode comprises a certain number of micro-coils and / or microcylinders of the conduction layer, this conduction layer being in contact with the insulating layer in the bottom portions of the micro-coatings and / or microcylinders; and a thin conduction layer covering the conduction layer inside and outside   microsunes and / or microcylinders.   140) semiconductor memory cell according to claim 13, characterized in that the microsaignées and / or the microcylinders have a screw hole structure passing through the conduction layer.   15) semiconductor memory cell according to claim 13, characterized in that the   Thin conduction layer is polysilicon.   16) A method of manufacturing a storage electrode comprising a certain number of microsaignées and / or microcylinders, characterized in that it comprises the various steps of: forming grains on a surface of the storage electrode; forming an etching mask layer on the sidewalls of the respective grains; and carry out an anisotropic etching in   using the mask of the etching mask as a mask.   Method according to claim 16, characterized in that it further comprises the step of removing the cutting edges of the microsunes and / or microcylinders after the step anisotropic etching.   ) A method of manufacturing a storage electrode having a number of microsunes and / or microcylinders, characterized in that it comprises the various steps of: flattening a surface of an insulating layer on which must be formed l storage electrode; forming grains on a surface of the storage electrode; forming an etching mask layer on the sidewalls of the respective grains; performing anisotropic etching by masking the etch mask layer to form screw-hole holes passing through the storage electrode to expose the insulating layer through these holes; and form a thin polysilicon conduction layer covering the inside and the outside of the holes in the form of screw holes.   A method of manufacturing a storage capacitor for use in a semiconductor memory device, using a polysilicon layer having a number of hemispherical grains, characterized in that it comprises the various steps of forming an etching mask layer on the upper surfaces of the hemispherical grains; draw a pattern on the polysilicon layer; perform an anisotropic etching using the etch mask layer as a mask and remove the etch mask layer for to form a storage electrode.   20) The method of claim 19, characterized in that it further comprises a step of oxidation of the upper surfaces of the hemispherical grains to form thereon the layer of engraving mask.   210) The method of claim 19, characterized in that it further comprises a step of subject to anisotropic etching the polysilicon layer between the hemispherical grains. E) Method according to claim 19, characterized in that it further comprises the various steps of: forming a dielectric layer on the storage electrode; and forming a plate electrode on the dielectric layer. 230) A method of manufacturing a first storage electrode in a semiconductor memory device comprising: a transfer transistor comprising; a source zone and a drain region of a second conduction type formed on a semiconductor substrate of a first conduction type, a first conduction layer placed in the vicinity of the source and drain zones and isolated, by a gate oxide layer, a passage region formed between the source and drain regions, and a first insulating layer overlying the first conduction layer to isolate the first conduction layer, and a storage capacitor comprising; a second conduction layer in contact with the drain zone, this second conduction layer extending over the first insulating layer, a second insulating layer covering the second conduction layer to isolate this second conduction layer, an oxide layer formed on the substrate, this field oxide layer being placed in the vicinity of the source zone, the first electrode being constituted by a conduction layer in contact with the source zone, this first electrode covering a predetermined portion of the first conduction layer and extending over the field oxide layer, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer, characterized in that it comprises the various steps of: forming a polysilicon layer in contact with the source area, this polysilicon layer having a number of grains s hemispherical on its surface and covering the second insulating layer; forming an etching mask layer on the upper surfaces of the hemispherical grains; draw a pattern on the polysilicon layer; perform an anisotropic etching using as mask the etch mask layer and   remove this layer of etching mask.   240) The method of claim 23, characterized in that it further comprises a step of oxidation of the upper surfaces of the hemispherical grains to form thereon the layer of engraving mask.   250) Method according to claim 23, characterized in that it further comprises a step of subjecting the polysilicon layer between the grains to anisotropic etching. hemispherical.   26-) Method of manufacturing a storage electrode of a storage capacitor on a   flattened insulating layer formed on a semi-   conductor comprising an active zone, characterized in that it comprises the various steps of: forming on the insulating layer a polysilicon layer in contact with the active zone, this polysilicon layer comprising a number of hemispherical grains spaced apart others by a predetermined distance; forming an Si N layer on the polysilicon layer; deposit a layer of flattened spinning glass on the Si N layer; subjecting the spinning glass to a retrograde to expose the Si N layer formed on the upper surfaces of the hemispherical grains; remove the exposed Si N layer to expose the upper surfaces of the hemispherical grains; oxidizing the upper surfaces of the hemispherical grains to form thereon an etching mask layer; subjecting the polysilicon layer to anisotropic etching using the etch mask layer as a mask; and   remove this layer of etching mask.   270) Method according to claim 26, characterized in that it further comprises a step of subject to anisotropic etching the polysilicon layer between the hemispherical grains. 280) Method of manufacturing a storage electrode of a storage capacitor on a   flattened insulating layer formed on a semi-   conductor comprising an active zone, characterized in that it comprises the various steps of: forming successively on the insulating layer flattened a first insulating interlayer, a first insulating layer and a second insulating layer; forming a contact hole through the insulating interlayer, the first insulating layer and the second insulating layer, thereby exposing the active area through this hole; forming on the second insulating layer a layer of polysilicon in contact with the active area, said polysilicon layer having a number of hemispherical grains; subjecting the polysilicon layer to etching to draw a pattern; forming on the semiconductor substrate an insulating layer overlying the polysilicon layer and subjecting said insulating layer to retrogravure so as to form an etch mask pattern with the remaining portions of the insulating layer; and subjecting the polysilicon layer to etching using the mask pattern as a mask engraving.   290) Method according to claim 28, characterized in that the first insulating layer is in nitride.   300) The method of claim 28, characterized in that it further comprises a step of forming the etching mask pattern between the hemispherical grains and on the walls   side of the pattern of the polysilicon layer.   310) Method of manufacturing a storage electrode of a storage capacitor on a   flattened insulating layer formed on a semi-   conductor comprising an active zone, characterized in that it comprises the various steps of: forming successively on the insulating layer flattened a first insulating interlayer, a first insulating layer and a second insulating layer; forming a contact hole through the insulating interlayer, the first insulating layer and the second insulating layer so as to expose the active area through this hole; forming on the second insulating layer a layer of polysilicon in contact with the active area, said polysilicon layer having a number of hemispherical grains; forming a third insulating layer on the polysilicon layer; etching the polysilicon layer and the third insulating layer to form a pattern; etching the predetermined portions of the third insulating layer carrying the pattern, so as to form a first etching mask pattern constituted by the third insulating layer; subjecting the polysilicon layer to an etching of predetermined thickness using as mask the first mask pattern; depositing a fourth insulating layer over the entire surface of the semiconductor substrate; subjecting said fourth insulating layer to retrogravure so as to form a second etch mask pattern with the remaining portions of the fourth insulating layer; and subjecting the polysilicon layer to etching using as mask the second pattern of engraving mask.   320) Method according to claim 31, characterized in that the first etching mask pattern has a smaller size, of a predetermined width, than the polysilicon layer carrying   the pattern, along its circumference.   330) Method according to claim 31, characterized in that the second etching mask pattern is formed between the hemispherical grains and on the sidewalls of the polysilicon layer bearing the pattern.