JP7339319B2 - memory cell structure - Google Patents

Description

The invention relates to a memory cell structure according to claim 1 .

One of the most important volatile memory integrated circuits is DRAM (Dynamic Random Access Memory) using 1T1C memory cells, which is the best cost main memory and/or buffer memory for computing and communication applications. Besides providing performance capabilities, it also serves as the best driver for technology scaling down to maintain Moore's Law by shrinking the minimum feature size on silicon from a few micrometers down to as little as 20 nanometers. came. Recently, logic technology that continues to use embedded SRAM (static random access memory) as a scaling down driver has claimed to bring manufacturing to the near 5 nanometer leading edge technology node achievement. By comparison, the best claim for the technology node of DRAM is still above 10-12 nanometers. The main problems are very challenging design rules, scaled access transistor (i.e. 1T) design and three-dimensional design, such as stacked capacitors or very deep trench capacitors on parts of the access transistor and isolation regions. Even with storage capacitors (ie, 1C), the structure of 1T1C memory cells is very difficult to scale further.

The difficulties with 1T1C memory cells, which are well-known problems even under the huge amount of money and R&D investment in technology, design and equipment, are elaborated here. To name a few examples of difficulties: (1) access transistor structures suffer from inevitable more severe current leakage problems that degrade 1T1C memory cell storage functions, e.g., shortening DRAM refresh times; The complexity of placing wordlines, bitlines and storage capacitors over geometric and topographic structures, and connections to gates, sources and drains of access transistors is exacerbated for scaling down ( 3) trench capacitors suffer from excessive depth-to-aperture size aspect ratios, nearly stopping at the 14 nm node; and that there is little space for contact space between the storage capacitor and the source of the access transistor after twisting to. In addition, the space allowed for the bitline contact to the drain of the access transistor has become very small, yet must struggle to maintain self-alignment, and (5) leakage current problems. Deterioration requires increasing capacitance and continuing to increase capacitor heights to have larger capacitance areas, unless a much higher-k dielectric insulator material for storage capacitance can be found ( 6) Without a technology breakthrough to solve the above problems, it will be increasingly difficult to meet all the increasing demands for better reliability, quality and resilience of DRAM chips, which are increasingly demanding higher density/capacity and performance. and so on.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory cell structure with a denser structure, smaller area, lower leakage current, higher capacitance, and the like.

This is achieved by a memory cell structure according to claim 1 . Dependent claims relate to corresponding further developments and improvements.

As will be more clearly seen from the detailed description that follows, the claimed memory cell structure includes a silicon substrate, a transistor, and a capacitor. A silicon substrate has a silicon surface. A transistor is coupled to the silicon surface, the transistor including a gate structure, a first conductive region, and a second conductive region. A capacitor is electrically coupled to the second conductive region of the transistor, the capacitor completely covering the transistor.

According to another aspect of the invention, a memory cell structure includes a silicon substrate, a transistor and a capacitor. A silicon substrate has a silicon surface. A transistor is coupled to the silicon surface, the transistor including a gate structure, a first conductive region, and a second conductive region. A capacitor has a storage electrode, the capacitor overlies the transistor and the storage electrode is electrically coupled to the second conductive region of the transistor. The capacitor includes a capacitor rim within which the transistor is disposed.

According to another aspect of the invention, the storage electrode has a perimeter within which the transistor is disposed.

According to another aspect of the invention, the capacitor further includes a counter electrode overlying the transistor.

According to another aspect of the invention, the memory cell structure further includes a bitline electrically coupled to the first conductive region of the transistor, the bitline below the silicon surface.

According to another aspect of the invention, the memory cell structure further includes a bitline electrically coupled to the first conductive region of the transistor through a bridge contact, the bridge contact below the silicon surface. a first sidewall of the bridge contact aligned with an edge of the bit line, the bridge contact having a top and a bottom, the top of the bridge contact abutting the silicon substrate, and the bottom of the bridge contact a first isolation. separated from the silicon substrate by a layer.

According to another aspect of the invention, a capacitor includes a first protruding region, a second protruding region, and a connection region, the connection region overlying the gate structure of the transistor and the first protruding region. The region and the second protruding region are connected and the transistor is confined between the first protruding region and the second protruding region.

According to another aspect of the invention, the transistor further includes a first spacer overlying the first side of the gate structure and overlying the silicon surface, and a first spacer overlying the second side of the gate structure and overlying the silicon surface. a second spacer overlying the silicon surface, the second protruding region of the capacitor extending upwardly from the silicon surface and abutting the second spacer; It abuts one spacer and extends upwardly from the isolation region on the silicon surface.

According to another aspect of the invention, the memory cell structure includes a silicon substrate, a transistor and a capacitor. A silicon substrate has a silicon surface. A transistor is coupled to the silicon surface, the transistor including a gate structure, a first conductive region, and a second conductive region. A capacitor is electrically coupled to the second conductive region of the transistor, the capacitor completely covering the transistor.

According to another aspect of the invention, a capacitor includes a storage electrode that is vertically stacked over a top surface of a transistor with a first protruding region and a second protruding region. a connection region connecting the first protruding region and the second protruding region, the second protruding region connecting to the second conductive region of the transistor.

According to another aspect of the invention, the transistor is clamped with the first protruding region and the second protruding region.

According to another aspect of the invention, the memory cell structure further comprises a counter electrode, a plurality of first transistors, a plurality of first storage electrodes respectively corresponding to the plurality of first transistors; a counter electrode overlying the plurality of first transistors and the plurality of first storage electrodes, and the counter electrode coupled to the first voltage source.

According to another aspect of the invention, the memory cell structure further includes a bitline electrically coupled to the first conductive region of the transistor, the bitline below the silicon surface, It is electrically coupled to the first conductive region of the transistor through a bridge contact.

According to another aspect of the invention, the bridge contact is below the silicon surface and the first sidewall of the bridge contact is aligned with the edge of the bitline.

According to another aspect of the invention, the bridge contact includes an upper portion and a lower portion, wherein the upper portion of the bridge contact abuts the silicon substrate and the lower portion of the bridge contact is separated from the silicon substrate by a first isolation layer.

According to another aspect of the invention, the transistor further includes a first spacer and a second spacer, the first spacer overlying the first side of the gate structure and overlying the silicon surface; A second spacer overlies the second side of the gate structure and overlies the silicon surface. A second protruding region of the storage electrode extends upwardly from the silicon surface and abuts the second spacer, and a first protruding region of the storage electrode abuts the second spacer and on the silicon surface. Extending upward from a certain isolation region.

According to another aspect of the invention, the top surface of the first projecting area is rectangular shaped and the top surface of the second projecting area is another rectangular shape.

According to another aspect of the invention, a memory cell structure includes a cell region and an inner region within the cell region. The memory cell structure includes transistors and capacitors. A transistor is in the inner region. A capacitor is within the cell area, the capacitor includes a plurality of protruding regions and a connection region, the connection region overlying the transistor and connecting the plurality of protruding regions.

According to another aspect of the invention, the cell area is rectangular shaped and the top surface of one protruding area is another rectangular shaped.

According to another aspect of the invention, a transistor includes a gate structure, a cap isolation layer over the gate structure, a first conductive region, and a second conductive region, wherein the plurality of protruding regions extends upwardly and downwardly from the top surface of the cap isolation layer.

According to another aspect of the present invention, a second protruding region of the plurality of protruding regions extends upward and downward from the top surface of the cap isolation layer, and the second protruding region is the Connect to the second conductive region.

According to another aspect of the invention, the plurality of protruding regions confine the transistor.

According to another aspect of the invention, a memory cell structure includes a silicon substrate, a transistor and a capacitor. A silicon substrate has a silicon surface. A transistor is coupled to a silicon surface and includes a gate structure, a cap isolation layer over the gate structure, a first conductive region, and a second conductive region. A capacitor is electrically coupled to the second conductive region of the transistor, the capacitor overlying the transistor and having a capacitor outer edge that is rectangular in shape.

According to another aspect of the invention, the transistor is positioned within the capacitor perimeter.

According to another aspect of the invention, the capacitor further includes a storage electrode overlying the first protruding region, the second protruding region, and the cap isolation layer and the first protruding region. a connecting region connecting the region and the second protruding region, the first protruding region and the second protruding region extending upwardly and downwardly from the top surface of the cap isolation layer.

According to another aspect of the present invention, the first protruding region extends upward from the top surface of the cap separation layer to a position higher than the connection region, and downward from the top surface of the cap separation layer, It extends to an isolation region on the silicon surface.

According to another aspect of the invention, the second protruding region extends upward from the top surface of the cap isolation layer to another position higher than the connection region and downward from the top surface of the cap isolation layer. extends to the silicon surface.

According to another aspect of the invention, a memory cell structure includes a counter electrode, a plurality of first transistors, and a plurality of first storage electrodes. a plurality of first storage electrodes respectively corresponding to the plurality of first transistors; a counter electrode covering the plurality of first transistors and the plurality of first storage electrodes; the counter electrode having a first voltage; combined with the source.

The invention will be further described by way of example with reference to the accompanying drawings.
4 is a flow chart illustrating a method of fabricating a DRAM cell (1T1C cell) array according to one embodiment of the present invention; 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. 1B-1J are diagrams illustrating FIG. 1A. [0014] FIG. 4 shows a top view and a cross-sectional view along the X direction after pad nitride and pad oxide layers are deposited and STI is formed; FIG. 10 illustrates depositing and etching back a nitride 1 layer to form nitride 1 spacers, and depositing SOD and photoresist layers; FIG. 10 illustrates etching away the top edge nitride 1 spacers and SOD not covered by the photoresist layer; FIG. 4 shows stripping the photoresist layer and SOD and depositing an oxide 1 layer; FIG. 4 shows that a metal layer is deposited in the trench and planarized by CMP technique; FIG. 3 shows a photoresist layer being deposited; FIG. 10 illustrates that the metal layer corresponding to the edge of the active region is etched; FIG. 12 shows the photoresist layer removed and the metal layer etched to form an underground bitline; FIG. 10 illustrates that an oxide bilayer is deposited in the trench; FIG. 4 shows that oxide trilayer, nitride bilayer and photoresist are deposited and then unwanted portions of oxide trilayer, nitride bilayer and photoresist are removed. FIG. 11 shows the photoresist layer, the pad nitride layer and the pad oxide layer are removed; A high-k insulator layer is formed as the gate dielectric layer of the access transistor, creating a U-shaped recess, and the gate material is deposited and then etched back to form the word line and gate structures of the access transistor. It is a figure which shows that. FIG. 4 shows that a nitride trilayer and an oxide quadruple layer are deposited and then the nitride trilayer and oxide quadruple layer are polished; FIG. 4 shows that the nitride bi-layer and oxide tri-layer are etched away; FIG. 4 shows pad nitride layer 206 is removed, CVD-STI-oxide2 is etched back, and 4 layers of nitride, 5 layers of oxide, and 1 layer of polysilicon are deposited and etched. FIG. 11 shows that SOD is deposited and polished, a portion of the polysilicon 1 layer is etched on top, and a cap oxide 1 layer is deposited and planarized. FIG. 18 shows that the SOD is etched away and a nitride 5 layer 1802 is deposited. FIG. 4 shows SOD deposited, photoresist deposited, and SOD removed corresponding to the area reserved for the source region; FIG. 11 shows that the exposed nitride 5 layer and pad oxide layer in the center of the source region are etched away and silicon material corresponding to the center of the source region is drilled out to create a hole ⅓. FIG. 10 shows thermally grown oxide 7 layers in hole 1/3. FIG. 11 shows another SOD layer deposited and etched back; A photoresist is deposited to cover the area corresponding to the source region and expose the area reserved for the drain region, and the exposed SOD, the exposed nitride 5 layer, and the exposed nitride layer underneath. FIG. 11 shows the pad oxide layer and silicon material removed to create hole 1/2; FIG. 11 shows the photoresist removed and an oxide 8 layer thermally grown to produce oxide 8 spacers; FIG. 10 is a diagram showing a cross-sectional view of the DRAM cell array along the Y2 direction showing a cross section of a hole 1/2; FIG. 11 shows that the bottom edge nitride 1 spacer inside the hole 1/2 is etched. FIG. 4 shows that the nitride 5 layer is removed; FIG. 12 shows a metal layer deposited and etched back to leave a tungsten plug inside the hole 1/2 and a nitride 6 layer deposited and etched; FIG. 11 shows that a portion of the top of the tungsten plug below the HSS is etched back; FIG. 10 shows that a tungsten plug is connected to the UGBL; FIG. 11 shows that the top of the oxide 8 layer is removed; Fig. 10 shows an n+ in-situ doped silicon layer grown laterally to form an n+ silicon drain collar; FIG. 11 shows thermally grown oxide 9 layer locally on top of the n+ silicon drain collar. FIG. 11 shows that the oxide 9 layer is etched back and the polysilicon a layer is deposited and etched back; FIG. 11 shows the nitride 6 spacers are removed and the polysilicon b layer is deposited and etched back; FIG. 4 shows that all SOD and nitride 5 layers are removed; Fig. 2 shows a top view of the structure of the HCoT cell array; FIG. 12 shows a metal layer deposited and part of the metal layer etched back to form a W buffer wall; FIG. 10 shows that the cap oxide 1 layer, polysilicon 1 spacer, and pad oxide layers are removed to expose the HSS corresponding to the source and drain regions. FIG. 11 shows that an elevated source electrode EH-1S and an elevated drain electrode EH-1D are grown; FIG. 4 shows a post-RTA (Rapid Thermal Anneal) step to form a better electrical connection between the elevated source electrode EH-1S (or elevated drain electrode EH-1D) and the channel region of the transistor; is. FIG. 10 shows oxide 5 spacers etched and oxide a layer thermally grown and etched; FIG. 11 shows that an elevated source electrode EH-2S and an elevated drain electrode EH-2D are grown; FIG. 4 shows that a thick SOD-1 layer is deposited and etched back; FIG. 11 shows that the WBW is etched away; FIG. 3 shows a nitride a-layer deposited and etched using an anisotropic etching technique; FIG. 11 shows that the polysilicon a layer and the polysilicon b layer are removed, and the bottom portion of a portion of the elevated drain electrode EH-1D is removed; FIG. 4 shows that the oxide bb layer is thermally grown; FIG. 4 shows that the nitride a-spacer and SOD-1 layer are removed; FIG. 4 shows that one layer of high-k dielectric insulator is formed; FIG. 4 shows that a metal layer is deposited and etched back; FIG. 11 shows that the high-k dielectric insulator 1 metal layer above the oxide 4 layer is removed and then the oxide 4 layer is etched away. FIG. 11 shows that the top of the nitride 3 layer is removed and that the top of the nitride 4 spacer is also removed. FIG. 4 shows that LGS-2S and LGS-2D are grown laterally; FIG. 3 shows that a nitride cc layer is deposited and the LGS-2D, LGS-2S and nitride cc layers are polished by CMP technique; FIG. 10 illustrates that MCEPW-1 is removed; FIG. 11 shows twin-tower storage electrodes for storage capacitors are grown by using exposed LGS-2D and exposed LGS-2S as seeds. FIG. 4 shows that the oxide d-layer is thermally grown and anisotropically etched; Fig. 3 shows an n+ in-situ doped silicon layer grown laterally and vertically; FIG. 11 shows that the oxide d-spacers are removed; FIG. 3 shows high-k dielectric insulator 1 is removed and high-k dielectric insulator 2 is formed. Fig. 3 shows that a metal layer is deposited and polished by a CMP technique; FIG. 11 MCEPW-2 is etched back and the high-k dielectric insulator 2 above STSEC-1 is etched away. By seeding the exposed silicon material above STSEC-1, the upper n+ in-situ doped silicon tower as the storage electrode of the storage capacitor is grown, the high-k dielectric insulator 2 is etched, and high Fig. 3 shows that a -k dielectric insulator 3 is formed; FIG. 4 illustrates that a photoresist is formed; FIG. 4 shows that the high-k dielectric insulator 3 on the exposed edge regions of MCEPW-2 is etched away. FIG. 11 illustrates that the photoresist is removed; FIG. 4 shows a metal layer deposited to complete the counter electrode plate of the storage capacitor; Fig. 3 shows the schematic structure of the new HCoT cell; FIG. 3 shows a simplified top view of an HCoT cell;

Please refer to FIGS. 1A-1F, FIG. 1A is a flowchart illustrating a method for fabricating an HCoT cell array according to one embodiment of the present invention.
Step 10: Start.
Step 15: Based on a substrate (eg, p-type silicon substrate), define the active area of the DRAM cell array and form shallow trench isolation (STI).
Step 20: Form asymmetric spacers along the sidewalls of the active area.
Step 25: Form underground conductive lines (eg, bit lines, etc.) between the asymmetric spacers and under the horizontal silicon surface (HSS).
Step 30: Form the word lines and the gates of the access transistors of the DRAM cell array.
Step 35: Defining drain regions (ie, first conductive regions) and source regions (ie, second conductive regions) of access transistors of the DRAM cell array.
Step 40: Form connections between the underground bitlines and the drain regions of the access transistors.
Step 45: Form drain and source regions.
Step 50: Form a capacitor tower over the access transistor.
Step 55: End.

See FIGS. 1B and 2. FIG. Step 15 may include:
Step 102: Deposit a pad oxide layer 204 and a pad nitride layer 206 on the horizontal silicon surface (hereinafter "HSS") 208 of the substrate.
Step 104 : Defining the active area of the DRAM cell array and removing a portion of the substrate material (eg, silicon material, etc.) corresponding to the horizontal silicon surface 208 outside the active area to create a trench 210 .
Step 106 : Deposit an oxide layer 214 in trenches 210 and etch back oxide layer 214 to form shallow trench isolation (STI) below horizontal silicon surface 208 .

See FIG. 1C and FIGS. 3-5. Step 20 may include:
Step 108: A nitride 1 layer is deposited and etched back to form nitride 1 spacers (FIG. 3).
Step 110: A spin-on dielectric (SOD) 304 is deposited in the trenches 210 and planarized by a chemical mechanical polishing (CMP) technique (FIG. 3).
Step 112: A photoresist layer 306 is deposited over the SOD 304 and pad nitride layer 206 (FIG. 3).
Step 114: The top edge nitride 1 spacer and SOD 304 not covered by the photoresist layer 306 are etched away (FIG. 4).
Step 116: The photoresist layer 306 and SOD 304 are stripped and an Oxide 1 layer 502 is grown, such as by thermal growth (FIG. 5).

See Figure ID and Figures 6-10. Step 25 may include:
Step 118: A metal layer 602 is deposited in the trench 210 and planarized by CMP technique (FIG. 6).
Step 120: A photoresist layer 702 is deposited and patterned (FIG. 7).
Step 122: The metal layer 602 corresponding to the edges of the active area is etched to form a plurality of conductive lines (FIG. 8).
Step 124: The photoresist layer 702 is removed and the metal layer 602 (multiple conductive lines) is etched back to form underground bit lines (UGBL) 902 or underground conductive lines (FIG. 9).
Step 126: Oxide 2 layer 1002 is deposited in trench 210 and planarized by CMP technique (FIG. 10).

See FIG. 1E and FIGS. 11-15. Step 30 may include:
Step 128: A thick oxide trilayer 1102, a thick nitride bilayer 1104, and a patterned photoresist layer 1106 are deposited, and then unwanted portions of the oxide trilayer 1102 and nitride bilayer 1104 are etched or removed. (Fig. 11).
Step 130: The patterned photoresist layer 1106, pad nitride layer 206, and pad oxide layer 204 may be removed to expose the HSS (Fig. 12).
Step 132: The exposed HSS is etched to create a U-shaped recess, a high-k dielectric layer 1304 is formed, a gate material 1306 (such as tungsten) is deposited and then etched back. , form the gate structures of the word lines and access transistors (FIG. 13). Such an access transistor may be called a U transistor.
Step 134: Deposit nitride 3 layer 1402, then etch back, followed by oxide 4 layer 1404, then etch back or planarize oxide 4 layer 1404 (FIG. 14).
Step 136: Etch away Nitride 2 layer 1104 and Oxide 3 layer 1102 (FIG. 15).

See FIGS. 1F and 16-22. Step 35 may include:
Step 138 : Remove pad nitride layer 206 and etch back CVD-STI-oxide 2 to the top of pad oxide layer 204 .
Step 140: Deposit and anisotropically etch Nitride 4 layer 1602, Oxide 5 layer 1604, and Polysilicon 1 layer 1606 respectively (FIG. 16).
Step 142: Deposit spin-on dielectric (SOD) 1702, then CMP, etch the top of polysilicon 1 layer 1606, and deposit cap oxide 1 layer 1704, then CMP (FIG. 17).
Step 144: Remove SOD 1702, then deposit nitride 5 layer 1802 (FIG. 18).
Step 146: Deposit SOD 1902, then CMP, deposit photoresist 1904, then etch back undesired SOD 1902 (FIG. 19).
Step 148: Etch away the silicon material corresponding to the exposed nitride 5 layer 1802, pad oxide layer 204, and HSS-1/3 to create hole 1/3 (FIG. 20).
Step 150: Remove photoresist 1904 and thermally grow oxide 7 layer 2102 (FIG. 21).
Step 152: Deposit another SOD layer 2202 on oxide 7 layer 2102 and then etch back another SOD layer 2202 (FIG. 22).

See Figure 1G and Figures 23-33. Step 40 may include:
Step 154: Deposit photoresist 2302, remove exposed SOD 1902, exposed nitride 5 layer 1802, and exposed pad oxide layer 204, then drill and remove silicon material corresponding to HSS-1/2. to generate hole 1/2 (Fig. 23).
Step 156: Remove photoresist 2302 and thermally grow oxide 8 layer 2402 (FIGS. 24 and 25).
Step 158: Remove the bottom edge nitride 1 spacers to expose the sidewalls of the underground bitlines and remove the nitride 5 layer 1802 (FIGS. 26 and 27).
Step 160: Deposit a metal layer 2802 in the holes 1/2 to contact the sidewalls of the UGBL, then deposit and etch back a nitride 6 layer 2804 to create nitride 6 spacers (FIG. 28).
Step 162: Etch back the top of metal layer 2802 (FIGS. 29 and 30).
Step 164: Etch back the top of oxide 8 layer 2402 to reveal silicon material corresponding to hole 1/2 (FIG. 31).
Step 166: Based on the exposed silicon material, laterally grow an n+ in-situ doped silicon layer 3202 to contact the drain region and the tungsten plug (FIG. 32).
Step 168: Thermally grow oxide 9 layer 3302 over n+ in-situ doped silicon layer 3202 (FIG. 33).

See FIG. 1H and FIGS. 34-42. Step 45 may include:
Step 170: Etch back oxide 9 layer 3302, deposit and etch back polysilicon a layer 3402 (FIG. 34).
Step 171: Remove nitride 6 spacers, deposit and etch back polysilicon b layer 3502 (FIG. 35).
Step 172: Remove all SOD and nitride 5 layer 1802 (FIG. 36).
Step 173: Deposit and etch back a metal layer (eg, tungsten) 3802 (FIG. 38).
Step 174: Etch away cap oxide 1 layer 1704, polysilicon 1 spacers, and pad oxide layer 204 (FIG. 39).
Step 175: Grow both the elevated source electrode EH-1S and the elevated drain electrode EH-1D by using selective epitaxy silicon growth technique (FIG. 40).
Step 176: Etch away oxide 5 spacers, thermally grow and etch oxide a layer 4102 (FIG. 41).
Step 177: Grow an elevated source electrode EH-2S and an elevated drain electrode EH-2D by using the exposed silicon surfaces of the elevated source electrode EH-1S and the elevated drain electrode EH-1D ( Figure 42).

See Figures 1I, 1J and Figures 43-67. Step 50 may include:
Step 178: Deposit and etch back SOD-1 layer 4302 (FIG. 43).
Step 179: Etch away the W buffer wall (WBW) (FIG. 44).
Step 180: Deposit and etch nitride a-layer 4502 (FIG. 45).
Step 181: Remove the polysilicon a layer 3402 and the polysilicon b layer 3502, and etch the partial bottom of the elevated drain electrode EH-1D by using an isotropic etching technique (FIG. 46).
Step 182: Thermally grow oxide bb layer 4702 (FIG. 47).
Step 183: Remove nitride spacers and SOD-1 layer 4302 by using isotropic etching technique (FIG. 48).
Step 184: Form high-k dielectric insulator 1 layer 4902 (FIG. 49).
Step 185: Deposit and etch back metal layer 5002 to produce MCEPW-1 (FIG. 50).
Step 186: Remove high-k dielectric insulator 1 4902 over oxide 4 layer 1404 and etch away oxide 4 layer 1404 (FIG. 51).
Step 187: Etch nitride 3 layer 1402 and nitride 4 spacers (FIG. 52).
Step 188: Laterally grow n+ in-situ doped silicon material over the nitride tri layer 1402 by using the exposed silicon sidewalls of the EH-2 electrode (FIG. 53).
Step 189: Deposit nitride cc layer 5402 (FIG. 54).
Step 190: Remove MCEPW-1 (FIG. 55).
Step 191: Perform selective epitaxy silicon growth to create twin-tower storage electrodes by using exposed LGS-2D and exposed LGS-2S as seeds (FIG. 56).
Step 192: Thermally grow and anisotropically etch oxide d layer 5702 and remove nitride cc layer 5402 (FIG. 57).
Step 193: Grow a higher concentration n+ in-situ doped silicon layer laterally and vertically from the exposed silicon regions of both LGS-2D and LGS-2S by using selective epitaxy silicon growth techniques (FIG. 58). .
Step 194: Remove oxide d spacers (FIG. 59).
Step 195: Remove high-k dielectric insulator 1 4902 to form high-k dielectric insulator 2 6002 (FIG. 60).
Step 196: Deposit a metal layer (eg, tungsten) 6102 and then polish the metal layer 6102 using CMP technique (Fig. 61).
Step 197: Etch back MCEPW-2, then etch away high-k dielectric insulator 2 6002 on top of STSEC-1 (FIG. 62).
Step 198: Grow higher heavily n+ in-situ doped silicon tower 6301 and etch high-k Dielectric Insulator 2 6002 to form high-k Dielectric Insulator 3 6302 (FIG. 63).
Step 199: Form photoresist 6402 (FIG. 64).
Step 200: Etch away the high-k Dielectric Insulator 3 6302 over the exposed edge areas of MCEPW-2 (FIG. 65).
Step 201: Remove photoresist 6402 (FIG. 66).
Step 202: Deposit and etch back a thick metal layer 6702 to complete the HCoT cell (Fig. 67).

A possible material for the metal layers used in the aforementioned process steps (eg, such as those shown in FIG. 6 for the underground bitlines and in FIG. 13 for the wordlines, electrodes, and/or counter electrodes of capacitors) is tungsten. However, due to the susceptibility of the tungsten material to oxide or oxidation processes, it is better to cover the tungsten layer with another TiN layer or a suitable layer. This invention does not describe a detailed protection process for the tungsten layer, but assumes that the metal layers, including the tungsten layer, are well handled to avoid oxidation directly thereon. Of course, there are several metal layers that are suitable for use in underground bitlines and wordlines, rather than being limited to specific types of metal materials that are not well suited for integration processes.

A detailed description of the manufacturing method described above follows. Start with a p-type silicon wafer (ie, p-type substrate 202). At step 102, as shown in FIG. 2(a), a horizontal surface 208 (i.e., if the substrate is a silicon substrate, a horizontal silicon surface (HSS) or an original silicon surface (OSS)). ), hereinafter using a horizontal silicon surface or HSS as an example), a pad oxide layer 204 is formed, and then a pad nitride layer 206 is deposited over the pad oxide layer 204 .

At step 104, the active area of the DRAM cell array can be defined by photolithographic masking techniques, and as shown in FIG. A horizontal silicon surface 208 corresponding to 206 and outside the active area pattern is exposed accordingly. Since the horizontal silicon surface 208 outside the active area pattern is exposed, the portion of the silicon material corresponding to the horizontal silicon surface 208 outside the active area pattern is removed by an anisotropic etching technique to form a trench (or canal). A canal)) 210 can be created, for example, the trench 210 can be 250 nm deep below the HSS.

At step 106, an oxide layer 214 is deposited to completely fill the trench 210, and then the oxide layer 214 is etched back such that the STI inside the trench 210 is formed below the HSS. 2(b) is a top view corresponding to FIG. 2(a), and FIG. 2(a) is a cross-sectional view along the X direction shown in FIG. 2(b). Further, as shown in FIG. 2(a), for example, the STI has a thickness of about 50 nm and the top surface of the STI is below the HSS when trench 210 is 250 nm deep below the HSS. It is about 200 nm deep.

At step 108, a nitride 1 layer is deposited to create nitride 1 spacers along the opposite edges (i.e., top and bottom edges) of trench 210, as shown in FIG. It is etched back by anisotropic etching. At step 110, SOD 304 is deposited over the STI into the trench 210 to fill the trench 210, as shown in FIG. 3(a). The SOD 304 is then planarized by a CMP technique so that the top surface of the SOD 304 is level with the top surface of the pad nitride layer 206 .

In step 112, the bottom edge nitride 1 spacers of the nitride 1 spacers along the bottom edge of trench 210 are removed by photoresist layer 306 by utilizing photolithographic mask techniques, as shown in FIG. 3(a). Of the nitride 1 spacers, the top edge nitride 1 spacer along the top edge of trench 210 is unprotected. That is, after the photoresist layer 306 is deposited over the SOD 304 and the pad nitride layer 206, the portion of the photoresist layer 306 over the top nitride 1 spacer is removed while the bottom nitride 1 spacer is removed. Portions of the top photoresist layer 306 are preserved so that the bottom nitride 1-spacer can be protected while the top nitride 1-spacer can be removed later. 3(b) is a top view corresponding to FIG. 3(a), and FIG. 3(a) is a cross-sectional view along the Y-direction cutting line shown in FIG. 3(b). At step 114, the top edge nitride 1 spacer and SOD 304 not covered by the photoresist layer 306 are etched away by an etching process, as shown in FIG.

At step 116, both the photoresist layer 306 and the SOD 304 are stripped, as shown in FIG. 5, where the SOD 304 has a much higher etch rate than the thermal oxide and some deposited oxides. have. Next, an Oxide 1 layer 502 is thermally grown to form an Oxide 1 spacer covering the top edge of the trench 210 , where the Oxide 1 layer 502 is not grown over the pad nitride layer 206 . , STI only has a much thinner oxide layer added on top of it (referred to as oxide 1/STI layer 504). As shown in FIG. 5, step 116 results in asymmetric spacers (bottom nitride 1 spacer and oxide 1 spacer) on the two symmetrical edges (top and bottom) of trench 210, respectively. For example, the thickness of the oxide 1 spacer is 4 nm and the thickness of the bottom nitride 1 spacer is 3 nm. In other words, asymmetric spacers are formed along the sidewalls of the active area. The structure of the asymmetric spacers (shown in FIG. 5) and the related processes described above are key inventions of the present invention, and the asymmetric spacers on two symmetrical edges of a trench or canal. a canal; ASoSE).

At step 118, as shown in FIG. 6, a metal layer 602 (or a conductive material that must withstand subsequent processing conditions) is deposited to completely fill the trenches 210 and cover the top surface of the metal layer 602. It is planarized by a CMP technique to make it even and flat with the top surface of pad nitride layer 206 (shown in FIG. 6). Also, in one embodiment of the present invention, the metal layer 602 may be tungsten, abbreviated as W.

At step 120, cover both the bottom nitride 1 spacers and oxide 1 spacers, but leave two of the bottom nitride 1 spacers and oxide 1 spacers corresponding to the edges of the active area, as shown in FIG. A photoresist layer 702 is deposited exposing one edge.

At step 122, metal layer 602 corresponding to the edges of the active region is removed to expose the top of oxide 1/STI layer 504 to form a plurality of conductive lines (ie, metal layer 602), as shown in FIG. Etch until separated.

At step 124, after the photoresist layer 702 is removed, the metal layer 602 is formed to form a conductive line or underground bit line (UGBL) 902, as shown in FIG. 9(a). The trench 210 is etched back leaving only a reasonable thickness inside, where the top surface of the underground bitline 902 is well below the HSS (e.g., the thickness of the underground bitline 902 is about 40 nm). is). Also, as shown in FIG. 9(a), the underground bitline 902 is above the STI and both sidewalls of the underground bitline 902 are formed by asymmetric spacers, i.e., bottom nitride 1 spacer and oxide 1 spacer. Each bounded by a spacer. FIG. 9(a) is a cross-sectional view along the Y direction shown in FIG. 9(b).

At step 126, an oxide 2 layer 1002 (referred to as CVD-STI-oxide2) is deposited over the underground bitlines 902, as shown in FIG. and the oxide bi layer 1002 is then polished to ensure that it is flush with the top surface of the pad nitride layer 206, Cover both the bottom edge nitride 1 spacer and the oxide 1 spacer. As shown in FIG. 10, step 126 fills and bounds the underground bitlines 902 (ie, interconnect lines) with all insulators (ie, isolation regions) inside trenches 210 . (and later the underground bit line 902 will be connected to the drain of the access transistor of the DRAM cell array), which is called the insulator surrounded underground bit line (UGBL). UGBL is another key invention of the present invention.

The following description introduces how to form both the access transistors and word lines of a DRAM cell (1T1C cell) array, where the word lines are self-aligned to all associated gates of the access transistors. The structures are connected together so that both the gate structure and the wordline are connected as a solid metal, for example tungsten (W).

At step 128, first a thick oxide 3 layer 1102, a thick nitride 2 layer 1104 and a patterned photoresist 1106 are deposited as shown in FIG. 11(a). Unwanted portions of oxide tri layer 1102 and nitride bi layer 1104 are then removed by using etching techniques. The transistor/word line pattern will be defined by the tri-oxide layer 1102 and bi-nitride layer 1104 composite layer, which is the composite layer for the active region. It consists of multiple stripes oriented perpendicular to the direction. Thus, longitudinal (Y-direction) stripes (oxide trilayer 1102 and nitride bilayer 1104) defining the access transistors and word lines are formed, as shown in FIGS. 11(a) and 11(b). , the active regions are located at the cross-point squares between the longitudinal stripes. FIG. 11(a) is a cross-sectional view along the X direction shown in FIG. 11(b).

As shown in FIG. 11(b), the top view is a fabric-like layer with longitudinal stripes of oxide tri-layer 1102 and nitride bi-layer 1104 on pad nitride layer 206 and pad oxide layer 204. It reveals a checkerboard pattern, with both the active area and the STI in the horizontal direction (ie, the X direction shown in FIG. 11(b)). The active area allows access transistors to be manufactured by a kind of self-aligning technique. Such a checkerboard fabric proposal for creating a self-aligned structure that fabricates the gate structure and wordline of the access transistor in one processing step is another important invention of the present invention.

At step 130, the photoresist layer 1106 is left intact so that the pad nitride layer 206 is etched but the pad oxide layer 204 is retained, as shown in FIG. As shown in 12(b), both the photoresist layer 1106 and the pad oxide layer 204 are removed. As a result, horizontal silicon surfaces 208 (ie, HSS) are exposed at the locations of the cross-point squares (shown in FIG. 12(b)) corresponding to the active areas.

At step 132, as shown in FIG. 13, the exposed HSS at the cross-point square location is etched by an anisotropic etching technique to form a recess (e.g., U-shaped, etc.), where the U-shaped The recess is for the U-shaped channel 1302 of the access transistor, for example, the vertical depth of the U-shaped recess can be about 60 nm from HSS. Since this U-shaped recess of the access transistor is exposed, after subsequent high-k metal gate structure formation, the channel 1302 of the U-shaped recess can be doped for the desired threshold voltage of the access transistor. A doping design can be achieved with a somewhat better designed boron (p-type dopant) concentration. A suitable high-k insulator layer 1304 is formed as the gate dielectric layer of the access transistor, the top surface of the two edges of the high-k insulator layer 1304 being higher than the HSS. Then select a suitable gate material 1306 that is suitable for the conductance of the word line and that can achieve the targeted work function performance of the access transistor to have a lower threshold voltage (Select a suitable gate material 1306 The goal of doing so is to lower the boosted wordline voltage level as low as possible while ensuring that a sufficient amount of charge is restored in the capacitor while supporting faster charge transfer for signal sensing. is to provide enough device drive to do so).

Gate material 1306 is thick enough to fill the U-shaped recess (shown in FIG. 13) between two adjacent longitudinal stripes (oxide tri-layer 1102 and nitride bi-layer 1104). The gate material 1306 is then etched back to result in longitudinal (Y-direction) word lines sandwiched between two adjacent longitudinal stripes (oxide tri-layer 1102 and nitride bi-layer 1104). For example, the gate material 1306 can be tungsten (W) which, when having a suitable channel doping concentration, forms a high-k metal gate structure that allows for the desired lower threshold voltage design of access transistors.

The newly proposed access transistor with U-shaped channel 1302 (hereafter referred to as U-transistor) differs from the recessed transistor commonly used in state-of-the-art buried wordline designs. The U-transistor is bounded on both sides by its body by CVD-STI-oxide2 along the Y-direction (ie, channel width direction) and a U-shaped channel 1302 whose channel length corresponds to the drain of the U-transistor. , the bottom length of the U-shaped channel 1302, and the depth of another edge of the U-shaped channel 1302 on the side corresponding to the source of the U transistor. For example, if the vertical depth of the U-shaped recess is about 60 nm and the U opening of the U-shaped recess is about 7 nm along the X direction (i.e., channel length direction), then the total channel length of the U transistor is about 127 nm. be. In contrast, the channel length of a recessed transistor must be more dependent on how deeply the gate material of the recessed transistor is recessed and how deeply the source and drain junctions of the recessed transistor are formed. must.

Due to the difference in structure between the U transistor and the recessed transistor, the channel length of the U transistor is much better controlled, especially when the channel length of the U transistor does not depend on the height of the gate of the U transistor. can In addition, as will be explained later on how to complete the drain and source of the U transistor, since the HSS is fixed, the small variability in the device design parameters as will become more clearly apparent will allow the U transistor are much more controllable in the respective drain and source dopant concentration profiles. In addition, simultaneously forming the gate structure and the wordline of the U transistor longitudinally by self-alignment between two adjacent longitudinal stripes (the oxide trilayer 1102 and the nitride bilayer 1104) allows the wordline to Not below HSS and wordlines not below HSS present design and performance parameters that are significantly different than the commonly used buried wordlines. In addition, the wordline (i.e., gate material 1306) level is composed of composite layers (oxide trilayer 1102 and nitride bilayer 1104) by using an etchback technique (shown in FIG. 13). ) is designed to be lower than the height of The structural design of the gate structure of the U transistor, which is self-aligned with the word line, is another key invention of the present invention.

At step 134, as shown in FIG. 14, a nitride tri-layer 1402 (i.e., a dielectric cap) is deposited followed by an oxide quad-layer 1404, where the nitride tri-layer 1402 and oxide 4-layer 1404 are deposited. The four layers 1404 are stacked with a total thickness large enough to fill the space between two adjacent longitudinal stripes (oxide three layer 1102 and nitride two layer 1104). Oxide 4 layer 1404 and nitride 3 layer 1402 are then deposited to form a composite stack of oxide 4 layer 1404 and nitride 3 layer 1402 directly above the word lines (i.e., gate material 1306). , is etched back (or polished back) flush with the top surface of nitride 2 layer 1104 .

At step 136, the nitride 2 layer 1104 is etched away by an anisotropic etching technique, leaving the oxide 4 layer 1404/nitride 3 layer 1402 above the word lines, as shown in FIG. Oxide tri layer 1102 is then also etched away by an anisotropic etch to expose pad nitride layer 206 . The gate structure (e.g., oxide 4 layer 1404/nitride 3 layer 1402/gate material 1306, etc.) extends longitudinally (i.e., in the Y direction) to both the gate and word line of the U transistor within the U-shaped recess. achieved.

At step 138, the pad nitride layer 206 is removed everywhere leaving the pad oxide layer 204, as shown in FIG. CVD-STI-oxide 2 (ie, oxide 2 layer 1002 ) is etched back flush with the top surface of pad oxide layer 204 .

At step 140, as shown in FIG. 16, a nitride 4 layer 1602 is deposited and etched by an anisotropic etching technique to produce nitride 4 spacers with a well-designed preferred thickness. An oxide 5 layer 1604 is then deposited and etched by an anisotropic etching technique to create oxide 5 spacers. A polysilicon 1 layer 1606 (intrinsic and undoped) is then deposited over the entire surface and etched by an anisotropic etching technique to create polysilicon 1 spacers , and word lines (eg, word lines) on the polysilicon 1 spacers. line-1, word line-2, word line-3) . So, in summary, the polysilicon 1 spacers are outside the oxide 5 spacers, the oxide 5 spacers are outside the nitride 4 spacers, and all of the above spacers are part of the gate structure (e.g. oxide 4 layer 1404/ nitride tri layer 1402/gate material 1306, etc.).

As shown in FIGS. 16 and 17, for convenience and clarity in describing the DRAM cell array having wordlines and bitlines, the centrally located wordline is labeled word line-1 (corresponding to access transistor AQ1). and label the word line to the left of word line-1 as word line-2 (corresponding to access transistor AQ2 to the left of access transistor AQ1), still covered by pad oxide layer 204; A drain region (drain-1 and drain-2) between word line-1 and word line-2 is reserved for the drain of access transistor AQ1 and the drain of access transistor AQ2. The word line to the right of word line-1 is labeled word line-3 (corresponding to access transistor AQ3 to the right of access transistor AQ1), word line still covered by pad oxide layer 204; The source regions (source-1 and source-3) between -1 and word line-3 are reserved for the source of access transistor AQ1 and the source of right access transistor AQ3.

At step 142, SOD 1702 is deposited as shown in FIG. 17, the SOD 1702 being thick enough to fill the spaces between the word lines (corresponding to the drain and source regions) and then by CMP techniques. , SOD 1702 are polished to a level flush with the top surface of oxide 4 layer 1404 . A portion of the upper portion of polysilicon 1 layer 1606 is then etched by an anisotropic etching technique. A cap oxide 1 layer 1704 is then deposited to fill the voids above the polysilicon 1 spacers and then planarized by a CMP technique to be flush with the top surface of the oxide 4 layer 1404. .

At step 144, SOD 1702 is etched away, as shown in FIG. 18, where SOD 1702 has an etch rate much higher than the etch rate of deposited or thermally grown oxide layers and their oxidation. things are well kept. A nitride 5 layer 1802 is then deposited over the entire surface shown in FIG.

At step 146, SOD 1902 is deposited with a thickness sufficient to fill the spaces between all the wordlines, as shown in FIG. polished to Then, on the planar surface, cover the regions reserved for the drain regions (ie, drain-1 and drain-2) and the regions reserved for the source regions (ie, source-1 and source-3). Photoresist 1904 is deposited to expose the . The SOD 1902 corresponding to the areas reserved for the source regions are then removed by using the nitride 5 layer 1802 surrounding all the wordlines as a self-align mask. Once the desired pattern has been transferred to SOD 1902, all unwanted photoresist is removed, thus leaving SOD 1902 planarized as shown in FIG.

At step 148, the exposed nitride 5 layer 1802 and pad oxide layer 204 in the center of the source region between the two word lines (word line-1 and word line-3) are removed as shown in FIG. It is etched away to expose the HSS. Since the exposed HSS is located between source-1 of access transistor AQ1 and source-3 of access transistor AQ3, the exposed HSS between source-1 and source-3 is called HSS-1/3. can call As shown in FIG. 20, HSS-1/2 between word line 1 and word line 2 is for drain-1 (ie, the drain of access transistor AQ1) and drain-2 (ie, the drain of access transistor AQ2). It will be used as a place and also as a place for connecting the access transistors AQ1, AQ2 vertically to the UGBL. Further, on the other right side of word line-1, HSS-1/3 between word line-1 and word line-3 is source-1 (ie the source of access transistor AQ1) and source-3 (ie , source of access transistor AQ3), source-1 and source-3 are isolated and cannot be connected. 20, since source-1 and source-3 will later be connected to additional cell storage nodes CSN1, CSN3 (not shown in FIG. 20), respectively.

Furthermore, in summary, although this photolithographic mask technique is used to overlay it on HSS-1/2, the mask utilized by this photolithographic mask technique is not the critical mask, but its functional mask. is only possible to process HSS-1/3 separately from processing on HSS-1/2. SOD 1902 is deposited in a thickness sufficient to provide a smooth surface topology, as described above, and then photoresist 1904 acts as a masking material to protect SOD 1902 overlying the drain region but exposing the source region. deposited on Also, the reason for using SOD is that SOD has a very high etching rate so that it can be removed without damaging other materials present, and SOD is resistant to thermal processes other than photoresist. be.

As shown in FIG. 20, the silicon material under HSS-1/3 (corresponding to the center of the source region) is excavated by an anisotropic etching technique to remove two opposite sides (not shown in FIG. 20). ), surrounded by the bottom edge nitride 1 spacer and oxide 1 spacer, and surrounded by the silicon substrate 202 on the other two opposite sides (hole-1/3).

Then, in step 150, the photoresist 1904 is removed and an oxide 7 layer 2102 is thermally grown to fill the hole ⅓, as shown in FIG. Oxide 7 layer 2102 is grown partially over cap oxide 1 layer 1704 and not elsewhere because there is no oxide growth over nitride 5 layer 1802 . The oxide-7 layer 2102 that fills the hole ⅓ is called the oxide-7 plug and has a smooth surface flush with the top surface of the pad oxide layer 204 .

At step 152, another SOD layer 2202 is deposited, as shown in FIG. 22, sufficient to fill the void above the oxide 7 layer 2102 in hole-1/3. The top material of this further SOD layer 2202 is removed by CMP techniques until the top surface of this further SOD layer 2202 is flush with the top surface of the nitride 5 layer 1802. .

At step 154, photoresist 2302 is deposited to cover the area corresponding to the source region and to expose the area reserved for the drain region, as shown in FIG. The mask used in step 154 is not a critical mask and its only function is to allow processing of HSS-1/2 separately from processing on HSS-1/3. . The exposed SOD 1902, the exposed nitride 5 layer 1802, and the underlying exposed pad oxide layer 204 are then removed to expose the HSS (ie, HSS-1/2). The silicon material corresponding to HSS-1/2 is then excavated and removed by anisotropic etching to create hole-1/2. The hole 1/2 is physically surrounded on two opposite sides by the silicon substrate 202 respectively, on the third side by the bottom edge nitride 1 spacer, and on the fourth side by the oxide 1 spacer. surrounded by Both the third and fourth sides are further bounded on the outside by CVD-STI-oxide2 (not shown in FIG. 23).

At step 156, the photoresist 2302 is removed and three of the four sidewalls of the hole 1/2 are removed, except for the third sidewall which is covered by the bottom edge nitride 1 spacer, as shown in FIG. An oxide 8 layer 2402 is thermally grown to create an oxide 8 spacer covering the two sidewalls and the bottom of the hole 1/2. In addition, Oxide 8 layer 2402 is partially grown over Cap Oxide 1 layer 1704 . FIG. 25 is a diagram showing a cross-sectional view of the DRAM cell array along the Y2 direction extending perpendicular to the X direction along the center of the hole 1/2, and as shown in FIG. Sandwiched by STI-oxide2, bitline (UGBL), oxide 1 spacer, and bottom edge nitride 1 spacer.

At step 158, the bottom edge nitride 1 spacer on the third sidewall in hole 1/2 is removed by an isotropic etch technique along with nitride 5 layer 1802, as shown in FIGS. is removed at the same time (since the bottom edge nitride 1 spacer is very thin, as shown in FIG. 27, this isotropic etching technique should not damage other structures above the HSS and hole 1 It should also not remove the oxide 8 layer 2402 within /2).

At step 160, a metal layer (e.g., tungsten) 2802 thick enough to fill the hole 1/2 is deposited, as shown in FIG. It is etched back by an anisotropic etching technique to leave a Tungsten plug in hole 1/2. The tungsten plug is connected to the UGBL through an opening in the third sidewall of hole 1/2 that was originally covered by the bottom edge nitride 1 spacer. A nitride 6 layer 2804 is then deposited and etched by an anisotropic etching technique to create nitride 6 spacers surrounding the polysilicon 1 spacers corresponding to the reserved drain regions.

At step 162, the top portion of the tungsten plug under the HSS is etched back, as shown in FIG. As shown in FIG. 30, a tungsten plug is connected to the UGBL from the sidewall of the tungsten plug to the sidewall of the UGBL in hole 1/2.

At step 164, as shown in FIG. 31, the top of oxide 8 layer 2402 is removed through an anisotropic etching technique by a well-designed amount, thus having a height less than the height of the tungsten plug. An oxide 8 spacer is provided. A portion of cap oxide 1 layer 1704 may be etched as well, as shown in FIG.

At step 166, laterally from the two exposed silicon edges (over and adjacent to the oxide-8 layer 2402 and the tungsten plug) is removed by using a selective epitaxy silicon growth (SEG) technique, as shown in FIG. An n+ in-situ doped silicon layer 3202 is grown in the direction thus as drain-1 and drain-2 of access transistors AQ1, AQ2, respectively, and as a conductive bridge (ie, bridge contact) between the UGBL and access transistors AQ1, AQ2. , provides a necklace-shaped conductive n+ silicon drain (referred to as the n+ silicon drain collar) that connects to the HSS on either side of the hole 1/2.

At step 168, an oxide 9 layer 3302 with a well-designed thickness is thermally grown locally on the n+ silicon drain collar to cap the HSS-1/2, as shown in FIG. (and such Oxide 9 layer 3302 may cover cap Oxide 1 layer 1704). The above connection method of making an underline bridge contact between UGBL and drain-1 (drain-2) is another important invention of the present invention, drain-1 and drain-2 are oxide Capped n+ drain.

At step 170, a portion of the Oxide 9 layer 3302 covering the n+ silicon drain collar can be etched back to a thickness equal to the height of the pad oxide 204 and a cap as shown in FIG. The Oxide 9 layer 3302 covering the Oxide 1 layer 1704 is etched away. A thick intrinsic polysilicon a-layer 3402 is then deposited in the open space above the oxide 9 layer 3302 over the hole 1/2 and the polysilicon a-layer 3402 is etched back.

At step 171, the nitride 6 spacer (nitride 6 layer 2804) is removed by an isotropic etching technique, as shown in FIG. Deposit intrinsic polysilicon b-layer 3502 and then etch back polysilicon b-layer 3502 using an anisotropic etch technique to leave a residue that fills the voids immediately adjacent to polysilicon a-layer 3402 and polysilicon a-layer 3402. Both the silicon a layer 3402 and the polysilicon b layer 3502 form approximately the same thickness.

At step 172, all SOD (ie, SOD layer 1902 and another SOD layer 2202) are removed and nitride 5 layer 1802 is removed by an isotropic etching technique, as shown in FIG. FIG. 37 also shows a top view of the structure of the HCoT cell array up to this stage, in particular word lines (word line-1, word line-2, word line-3), underground bit lines (UGBL), access transistors. The geometric arrangement of the source regions (source-1 and source-3) of AQ1 and AQ3 and the drain regions (drain-1 and drain-2) of access transistors AQ1 and AQ2 are shown.

At step 173, a metal layer (e.g., tungsten) 3802 is deposited and a portion of metal layer 3802 is etched back to form a W-Buffer-Wall (WBW), as shown in FIG. .

At step 174, the cap oxide 1 layer 1704 over the polysilicon 1 spacers is removed, as shown in FIG. The polysilicon 1 spacers are then etched away, and the pad oxide layer 204 under the polysilicon 1 spacers is removed, thus removing the HSS corresponding to the source and drain regions (seed HSS regions for the source and drain regions, SHARS) are each exposed.

At step 175, the enhanced source electrode EH-1S and the enhanced drain electrode EH- are formed using selective epitaxy silicon growth techniques by using the exposed HSS (SHAR) as seeds as shown in FIG. Both 1D are grown vertically on top of HSS, respectively. Elevated source electrode EH-1S and elevated drain electrode EH-1D are grown gradually and well by using exposed HSS (SHAR) as seeds, so polycrystalline or amorphous silicon material instead of pure silicon material. Both the elevated source electrode EH-1S and the elevated drain electrode EH-1D are surrounded by the WBW and oxide 5 spacers on the left and right sidewalls along the X direction. Although the other two sidewalls along the Y direction are wide open, CVD-STI-oxide2 cannot provide a seed function to grow selective epitaxial silicon on top, so this selective epitaxial silicon growth should result in having some laterally overgrown pure silicon material that could stop at the edge of the CVD-STI-oxide2 and cause connection between adjacent electrodes. Further, after the elevated source electrode EH-1S and the elevated drain electrode EH-1D are grown, the elevated source electrode EH-1S or the elevated drain electrode EH-1D is grown with respect to the channel region of the transistor. NLDD (n+ lightly doped) under the elevated source electrode EH-1S or the elevated drain electrode EH-1D using an optional RTA (Rapid Thermal Annealing) step to have a better electrical connection. drain) 4012 can be formed.

A new process design to achieve the elevated source electrode EH-1S and the elevated drain electrode EH-1D is described as follows: (1) the elevated source electrode EH- by selective epitaxy silicon growth technique; By using SHAR as seeds to grow 1S and elevated drain electrodes EH-1D, it is important to design a suitable in-situ n-type doping concentration during silicon growth and use a rapid temperature annealing process. to the appropriate interfacial conductance of the channel region of the access transistor (this includes the silicon surface directly under the gate dielectric, the HSS under the 4 nitride/5 oxide spacers, and the elevated source electrode EH-1S or the elevated drain electrode). (including the conductance of the electrodes EH-1D, respectively) and lower leakage currents, especially for gate-induced drain leakage (GIDL), drain-induced barrier lowering (DIBL), subthreshold leakage due to short-channel effects, and junction leakage. to achieve.

(2) As shown in FIG. 40, the elevated source electrode EH-1S and the elevated drain electrode EH-1D are the final EH-1+2 electrodes (ie, the elevated source electrode EH-1+2S and the elevated drain electrode EH-1D). is grown to a specified height lower than the height of the drain electrode (EH-1+2D). At step 176, as shown in FIG. 41, the oxide 5-spacer is first etched by an isotropic etch technique between the nitride 4-spacer and the elevated drain electrode EH-1D (and the nitride 4-spacer). A seam (between the spacer and the elevated source electrode EH-1S) is left. Next, the elevated drain electrode EH-1D (or the elevated source electrode EH-1S) is covered with three sidewalls except the last fourth sidewall bounded by WBW and its top surface (oxidized). (referred to as the material a cap layer), an oxide a layer 4102 is thermally grown. The purpose of performing a careful step-wise source electrode formation process as described below is to ensure that the thermal oxide a-layer has a very high quality silicon dioxide-silicon electrode bond, resulting in high performance oxidation. to ensure that the top surface of the source electrode EH-1S (or the top surface of the drain electrode EH-1D) with a material-silicon interface is achieved (no doubt from a selective epitaxy silicon growth process). , instead an amorphous or low quality silicon material is obtained, which cannot provide sufficient on-current when the access transistor is turned on or has reduced carrier mobility when the access transistor is turned off. (There is a suspicion that it may have degraded the quality of the silicon source electrode, which would have introduced an additional amount of defects that could have increased leakage in the process). The cap portion of the oxide a-layer 4102 is then etched by an anisotropic etching technique to form a thin film between the nitride 4-spacer and the source electrode EH-1S (or between the nitride 4-spacer and the drain electrode EH-1D). ) is left behind.

(3) At step 177, perform a second selective epitaxial silicon growth by using the exposed silicon surfaces of the source electrode EH-1S and the drain electrode EH-1D as high quality silicon seeds, as shown in FIG. to grow an elevated source electrode EH-2S and an elevated drain electrode EH-2D, respectively. During the second selective epitaxial silicon growth, between the elevated source electrode EH-2S (or the elevated drain electrode EH-2D) and the storage electrode of the subsequently fabricated stacked storage capacitor (SSC). It is possible to achieve a well-designed higher in-situ n+ doping concentration in the enhanced source electrode EH-2S and the enhanced drain electrode EH-2D to prepare for the low resistance connection of can. A combination of the elevated source electrode EH-1S and the elevated source electrode EH-2S is called an elevated source electrode EH-1+2S (similarly, the elevated drain electrode EH-1D and the elevated drain electrode The combination with EH-2D is called elevated drain electrode EH-1+2D). Furthermore, taking the elevated source electrode EH-1+2S as an example, as shown in FIG. high quality n+ doped silicon material directly abutting the nitride 4 spacer at , the opposite sidewall abutting the WBW, and the other two sidewalls being wide open in the Y direction along the longitudinal wordlines. have. The height of the elevated source electrode EH-1+2S (height of the elevated drain electrode EH-1+2D) is often designed to be less than the height of the nitride 4-spacer.

At step 178, a thick SOD-1 layer 4302 is deposited over the surfaces of the elevated drain electrode EH-2D and the elevated source electrode EH-2S, respectively, as shown in FIG. to etch back.

At step 179, the WBW is etched away over the entire wafer surface, as shown in FIG.

At step 180, a nitride a-layer 4502 is deposited and etched by using an anisotropic etching technique to form an elevated source electrode EH-1+2S and an elevated drain electrode EH-, as shown in FIG. Nitride a spacers are formed surrounding all sidewalls of each 1+2D. The difference is that the nitride a spacer surrounding the elevated source electrode EH-1+2S (the elevated drain electrode EH-1+2D) is placed on top of the polysilicon a layer 3402 and the polysilicon b layer 3502 acting like a mattress layer. (However, on the sides of the elevated source electrode EH-1+2S (the elevated drain electrode EH-1+2D) are such polysilicon a-layers 3402 and polysilicon a-layers 3402 acting like mattress layers. b layer 3502 does not exist).

In step 181, as shown in FIG. 46, an anisotropic silicon etching technique is first used to remove the polysilicon a layer 3402 (at this time, for example, the elevated drain electrode EH-2D and the elevated source electrode). The rest of the silicon area, such as electrode EH-2S, is well protected by the SOD-1 layer 4302 and the nitride a spacer, respectively). Polysilicon b layer 3402 and polysilicon b layer 3502 are then removed using an isotropic etching technique due to seams (or like voids) caused by buffer spaces due to the thicknesses occupied by polysilicon a layer 3402 and polysilicon b layer 3502 . Etch away layer 3502 and a portion of the bottom of the elevated drain electrode EH-1D. Note that (1) the remaining bottom of the elevated drain electrode EH-1D maintains the strength to hold the top of the elevated drain electrode EH-1D due to high-quality silicon bonding strength; and (2) the nitride a-spacers have their feet standing on the CVD-STI-oxide 2 (ie oxide 2 layer 1002) and strong adhesion of the nitride a-spacers by chemical bonding; and surrounds the EH-1+2 electrode, the nitride a spacer is not completely suspended above the air. The end result aimed at creating this new process design is to expose the HSS under the elevated drain electrode EH-1D.

At step 182, as shown in FIG. 47, a thermal oxidation process is performed to form a high quality oxide bb on the surface of the exposed HSS shown in FIG. 46 by thermochemical reaction between silicon and silicon dioxide. Growing layer 4702 thus provides oxide isolation that sufficiently isolates the drain region from the bottom of the EH-1+2D electrode that can now be used as part of the storage electrode for the storage capacitor.

At step 183, as shown in FIG. 48, nitridation associated with the EH-1+2 electrodes (ie, the elevated source electrode EH-1+2S and the elevated drain electrode EH-1+2D) is performed using an isotropic etching technique. Material a spacers and SOD-1 layer 4302 are removed. Step 184 then forms a high-k dielectric insulator 1 layer 4902, as shown in FIG.

At step 185, a thick metal layer (eg, tungsten, etc.) 5002 is deposited and the EH-1+2 electrodes (ie, the elevated source electrode EH-1+2S and the elevated drain electrode EH-) are deposited as shown in FIG. 1+2D), but is etched back to leave its remnants well-designed to yield a height similar to that of a nitride 4-spacer. The metal layer 5002 extending over the wafer surface is called metal-counter-electrode-plate&wall-1 (MCEPW-1). MCEPW-1 covers the high-k cap 1 of the high-k dielectric insulator 1 4902 above the EH-1+2 electrode, but covers the top surface of the oxide 4 layer 1404 and nitride 4 spacers of the composite stack. can cover

At step 186, the high-k dielectric insulator 1 4902 on the Oxide 4 layer 1404 is removed by an anisotropic etching technique and then the Oxide 4 layer, the top layer of the composite stack, as shown in FIG. Layer 1404 is etched away without damaging high-k cap 1 and high-k dielectric insulator 1 4902 covered by MCEPW-1. Therefore, there is a canal-like recessed region above the composite stack with nitride 4-spacers on two sides, the nitride 4-spacers having a height above the thickness of the nitride 3-layer 1402, It stands taller like a fence, but has an exposed upper part in the direction facing the canal-shaped recessed area.

At step 187, the top of the well-designed thickness of nitride tri-layer 1402 above the composite stack is removed by an isotropic etching technique, as shown in FIG. At the same time, the nitride 4-spacer is deposited so that the top surface of the remaining nitride 4-spacer and the top surface of the nitride 3-layer 1402 are level with the horizontal planar surfaces of both the nitride 3-layer 1402 and the nitride 4-spacer. is also removed by an isotropic etching technique. Silicon sidewalls on the top of the EH-2 electrode facing the nitride 4-spacer by an isotropic etching technique which caused the height of the nitride 4-spacer to be lowered after the nitride 4-spacer lost its top. is exposed.

At step 188, using the exposed silicon sidewalls of the EH-2 electrodes (ie, the elevated source electrode EH-2S and the elevated drain electrode EH-2D) facing the word line direction, as shown in FIG. laterally grow n+ in-situ doped silicon material over nitride trilayer 1402 using selective epitaxial silicon growth techniques. Taking word line-1 as a reference, there is an elevated source electrode EH-1+2S on one side of word line-1 and an elevated drain electrode EH-1+2D on the other side of word line-1. By controlling the growth time, epitaxial silicon grown laterally from the elevated source electrode EH-2S (referred to as LGS-2S) and epitaxial silicon laterally grown from the elevated drain electrode EH-2D ( LGS-2D) are not allowed to meet each other in the center of word line-1, instead there is a well-designed gap in the horizontal space (or void).

At step 189, a thick high quality nitride cc layer 5402 is deposited as shown in FIG. Leave the nitride cc isolation layer (nitride cc layer 5402) between 2D and LGS-2S to expose both LGS-2D and LGS-2S. At the same time, the tops of both MCEPW-1 and high-k Dielectric Insulator 1 4902 are removed either by CMP technique or etchback, leaving the remaining portions to be the same height as LGS-2D and LGS-2S, respectively. .

At step 190, MCEPW-1 (ie, metal layer 5002) is removed, as shown in FIG.

At step 191, exposed LGS-2D and exposed LGS-2S were seeded (SBSES as Seeding Base for Growing Storage-Electrode Skyscraper) as shown in FIG. SBSES-D and SBSES-S, respectively, using the abbreviations SBSES-D and SBSES-S) to create twin-tower-shaped storage electrodes for storage capacitors, which is shown in the following description of how it is accomplished. Perform growth (here, two twins of electrodes, one highly raised electrode on the drain side, called LGS-2D-Tower, and another raised electrode on the source side, called LGS-2S-Tower). there is a tower).

At step 192, a thin oxide d layer 5702 is thermally grown as shown in FIG. Remove d-layer 5702 to form oxide d-spacers. The nitride cc layer 5402 is removed using an isotropic etching technique to expose the side edges of LGS-2D and LGS-2S, respectively.

At step 193, a new connected silicon layer (called LGS-2DS) is formed from the exposed silicon regions of both LGS-2D and LGS-2S using selective epitaxy silicon growth techniques, as shown in FIG. A higher concentration n+ in-situ doped silicon layer is grown laterally until a is formed. In addition, as shown in FIG. 58, a higher concentration n+ in-situ doped silicon layer is grown vertically from the top surface of the LGS-2D-Tower and LGD-2S-Tower, also using selective epitaxy silicon growth techniques. . As shown in FIG. 58, the horizontal connection regions (which may include LGS-2DS) include one vertical protrusion region (eg, elevated drain electrode EH-1+2D) and the other vertical protrusion region (eg, elevated drain electrode EH-1+2D) of the H capacitor. (positioned source electrode EH-1+2S). The horizontal connecting area need not be joined in the middle of each protruding area, it can be higher or lower.

The oxide d-spacers are then removed in step 194, as shown in FIG. At step 195, isotropic etching techniques are used to remove the high-k dielectric insulator 1 4902 and the high-k dielectric insulator surrounding the grown twin tower storage electrodes, as shown in FIG. 2 6002.

At step 196, deposit a thick metal layer (eg, tungsten) 6102 (MCEPW-2) and then etch back the metal layer 6102 or use CMP techniques to remove the metal layer 6102, as shown in FIG. to produce a planar surface. This is completely surrounded by a high-k dielectric insulator 2 6002 which is completely surrounded on the outside by a counter electrode plate metal layer (ie metal layer 6102) which is bussed to a fixed voltage (eg half VCC). Fig. 3 shows a newly invented HCoT cell with twin tower H-shaped storage electrodes (of a storage capacitor). As shown in FIG. 61, the newly constructed storage capacitor surrounds access transistor AQ1 like a saddle tightly clamped over access transistor AQ1, and the sufficiently extended surface area of the storage electrode allows access rising straight from the HSS at the bottom of the elevated source electrode EH-1S of transistor AQ1 to the top of the signal tower storage electrode (referred to as STSEC-1) of the storage capacitor, surrounding the entire surface area of LGS-2S-Tower; and across all four sidewalls of LGS-2D-Tower down through the other three sidewalls of LGS-2S to the top of oxide bb layer 4702 at the bottom of the elevated drain electrode of access transistor AQ1. . Approximately all four sidewall surfaces surrounding the twin towers are used to create a near maximum dielectric area for making the storage capacitance of the storage capacitor as large as possible.

Also, if the height of the twin-tower storage nodes must be increased further, the process of FIGS. can be done. In addition, the connection area between the two protruding areas of the H capacitor can include multiple horizontal sub-connection areas after repeating the process of FIGS. 62 through 67 several times. Each sub-connection region may connect two protruding regions of the H-capacitor.

At step 197, MCEPW-2 is etched back to a height that is less than the height of the storage electrode (ie, STSEC-1), as shown in FIG. The high-k dielectric insulator 2 6002 above STSEC-1 is then etched away by an anisotropic etching technique, leaving only the high-k dielectric insulator 2 6002 surrounding STSEC-1.

At step 198, selective epitaxial silicon growth techniques are used to seed the exposed silicon material on the top surface of STSEC-1 to form a higher concentration as the storage electrode of the storage capacitor, as shown in FIG. An n+ in-situ doped silicon tower 6301 is grown. Then, etch the high-k dielectric insulator 2 6002 by an isotropic etching technique, and without allowing any possible electrical connection or leakage mechanism from the exposed n+ doped silicon storage electrode to MCEPW-2, the higher A high-k dielectric insulator 3 6302 is formed over all sidewalls and top surface of the heavily n+ in-situ doped silicon tower.

At step 199, photoresist 6402 is formed over all cell array areas except for exposing the edge areas of MCEPW-2, as shown in FIG. Step 200 then etches away the high-k dielectric insulator 3 6302 on the exposed edge regions of MCEPW-2, as shown in FIG. Then, in step 201, the photoresist 6402 is removed as shown in FIG.

At step 202, a thick metal (e.g., tungsten W) layer 6702 is deposited and etched back, as shown in FIG. It wraps around all the sidewalls of the shaped region to form a planar plateau, which is called MCEPW-3. The MCEPW-3 and the existing MCEPW-2, with all their edge regions connected together, can be used as a counter-electrode plate biased to a constant voltage level, such as half VCC, as well as a metal Better heat dissipation can be achieved like a heat sink, and noise can be suppressed or improved with respect to the wordline and access transistor gate structures (because the electric field is distributed more evenly). and distributed and shielded across the capacitor plates). FIG. 67 shows a newly invented HCoT cell whose storage capacitor clamping access transistor has capacitor storage area maximized by H-shaped twin-tower storage electrodes. FIG. 68 shows a schematic diagram of an HCoT cell.

FIG. 69 shows a simplified top view of an HCoT cell (1T1C cell), focusing on the twin tower capacitor storage electrodes connected at the bottom down to the elevated source electrodes of the access transistors. there is The cell area of the HCoT cell is rectangular in shape, the H capacitor includes a capacitor outer edge that is also rectangular in shape, and the access transistor is located within the capacitor outer edge. The capacitor footprint is about the same size as the cell area, except that some isolation tolerance is required to separate adjacent storage electrodes. As far as the inventors are aware, this should be the most efficient design for the ratio of the planar area of the storage capacitor to the planar area of the 1T1C cell.

In summary, the present invention provides a new architecture for DRAM cells that not only reduces the size of the DRAM cell, but also increases the signal-to-noise ratio during DRAM operation. Capacitors overlie and largely surround the access transistors, and both vertically and horizontally locating and connecting these basic microstructure geometries within the DRAM cell. Invented self-aligned technique, this new HCoT cell architecture can ensure the benefit of at least 4-10 square units even though the minimum physical feature size is much smaller than 10 nanometers. The area of the H capacitor can occupy 50% to 70% of the HCoT cell area.

Also, the metal electrodes of the capacitors in this new HCoT cell architecture provide an efficient route for heat dissipation and therefore the temperature of the HCoT cell during operation can be lowered accordingly. The temperature will reduce both leakage current and thermal/operating noise from the capacitor. In addition, the metal electrode also surrounds the wordlines passing through the access transistors, and the combination of such surrounded wordlines with underground bitlines (UGBLs) fabricated below the silicon surface is , the cross-coupling noise between different wordlines/bitlines can be effectively shielded, thus the troublesome pattern sensitivity problem in traditional DRAM cell array operation can be dramatically reduced.

GIDL leakage can also be reduced by well-designed transistor structures, and such reduced GIDL leakage, in combination with the reduced leakage resulting from lower operating temperatures, reduces the signal-to-noise ratio to It can be even higher, and can lead to the possibility of using much smaller sized capacitors in the HCoT cell without adversely affecting the reliability of the stored data.

Besides, the UGBL below the silicon surface of the present invention can flexibly lower the resistivity and capacitance of the bitline, thus reducing the signal sensitivity during charge sharing between the capacitor and the bitline. can be improved, and thus the operating speed of the HCoT cells of the new architecture can be increased as well.

In summary, the HCoT cell of the present invention is illustrated schematically in FIG. 68, which corresponds to FIG. In contrast to state-of-the-art DRAM cell structures, the new HCoT cell structure reveals the following features that help achieve cell sizes on the order of 4 to 10 square units below 10 nanometers: (1) access; (2) a counter electrode plate that contains the access transistor and covers the entire cell array; (3) an underground bit line below the HSS that reduces cell topography; (4) reduces cell leakage. (5) an elevated source electrode with adjustable conductance, self-aligned to the edge of the channel to minimize; straddling, self-aligned storage electrodes; (6) most cell features are scalable with proven materials and processes with sufficient reliability and quality; (7) majority of the disclosed DRAM cells. (to the best of the inventor's knowledge), the cell shape is very effectively kept as a rectangle occupying the planar surface of the silicon die as L (length) x W (width), and this HCoT cell can be used for different memory With the maximum extent of storage capacitor area on this L×W landscape, except that some distance must be reserved for storage electrode isolation between adjacent capacitors of a cell. (8) As described in the embodiment, the storage electrode height is built up stepwise in a desirably good straight tower shape by using multiple technologies and techniques as invented. in cell areas further reduced by device scaling requirements, the ratio of cell height to planar area of the cell, which increases to expand the surface area of the capacitor, is effectively enhanced; (9) protruding features By creating multiple storage electrodes in and connecting them as DRAM capacitor storage nodes, the storage area can be expanded, thus providing a large capacitance within the limited, reduced planar surface area of the cell. can.

Claims (14)

a silicon substrate having a silicon surface;
a transistor coupled to the silicon surface, the transistor having a gate structure, a first conductive region, and a second conductive region;
A capacitor having a storage electrode, said storage electrode electrically coupled to said second conductive region of said transistor , said storage electrode being a lower electrode of said capacitor and of said gate structure of said transistor. a capacitor covering two sides and a top surface ;
A memory cell structure comprising: The storage electrode has a first protruding region, a second protruding region, and is vertically stacked on a top surface of the transistor to connect the first protruding region and the second protruding region. 2. The memory cell structure of claim 1, further comprising a connection region, wherein said second projecting region connects to said second conductive region of said transistor. 3. The memory cell structure of claim 2, further comprising clamping the transistor between the first protruding region and the second protruding region. The memory cell structure further comprises a counter electrode, a plurality of first transistors, and a plurality of first storage electrodes respectively corresponding to the plurality of first transistors, wherein the counter electrode is connected to the 3. The memory cell of claim 2 overlying a plurality of first transistors and said plurality of first storage electrodes, and further characterized in that said counter electrode is coupled to a first voltage source. Structure. The memory cell structure further includes a bitline electrically coupled to the first conductive region of the transistor, the bitline below the silicon surface through a bridge contact. 3. The memory cell structure of claim 2, further characterized by being electrically coupled to said first conductive region of said transistor. 6. The memory cell of claim 5, further characterized in that the bridge contact is below the silicon surface and a first sidewall of the bridge contact is aligned with an edge of the bitline. Structure. wherein said bridge contact has an upper portion and a lower portion, said upper portion of said bridge contact abutting said silicon substrate and said lower portion of said bridge contact being separated from said silicon substrate by a first isolation layer. 7. The memory cell structure of claim 6, further characterized by: The transistor further comprises a first spacer and a second spacer, the first spacer overlying the first side of the gate structure and overlying the silicon surface, and the second spacer. overlies a second side of the gate structure and overlies the silicon surface;
The second protruding region of the storage electrode extends upwardly from the silicon surface and abuts the second spacer, and the first protruding region of the storage electrode abuts the first spacer. abutting and extending upwardly from an isolation region on the silicon surface;
3. The memory cell structure of claim 2, further characterized by: 3. The memory cell of claim 2, further characterized in that the top surface of said first protruding region is rectangular shaped and the top surface of said second protruding region is another rectangular shaped shape. Structure. The transistor has a gate structure, a cap isolation layer over the gate structure, a first conductive region, and a second conductive region, the first of the plurality of projecting regions of the storage electrode. 2. The memory cell structure of claim 1, further comprising protruding regions extending upwardly and downwardly from the top surface of said cap isolation layer. A second protruding region of the plurality of protruding regions of the storage electrode extends upwardly and downwardly from the top surface of the cap isolation layer, the second protruding region extending from the top surface of the transistor. 11. The memory cell structure of Claim 10, further characterized in that it is connected to a second conductive region. The storage electrode includes a first protruding region, a second protruding region, and a connection region that is on a cap isolation layer of the transistor and connects the first protruding region and the second protruding region. and wherein the first protruding region and the second protruding region extend upwardly and downwardly from the top surface of the cap isolation layer. Memory cell structure. The first protruding region extends upward from the top surface of the cap isolation layer to a position higher than the connection region and downward from the top surface of the cap isolation layer onto the silicon surface. 13. The memory cell structure of claim 12, further extending to an isolation region. The second protruding region extends upward from the top surface of the cap isolation layer to another position higher than the connection region and downward from the top surface of the cap isolation layer to the silicon surface. 14. The memory cell structure of claim 13, further characterized by being elongated.