JPH03165552A - Stacked capacitor type dram and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve a stacked capacitor in electrostatic capacity without making a cell large in size by a method wherein a storage node electrode of silicon is formed on an interlaminar insulating film of multilayered structure which contains an etching stopper layer, a side wall of silicon is formed on the side face of the storage node electrode. CONSTITUTION:A field insulating film 2 is formed on a P-type semiconductor substrate 1, a gate insulating film is formed on the surface of the element forming region of the substrate 1, a polycrystalline silicon film 4 and a high melting point metal silicide film 5 are formed to serve as a gate electrode respectively, a side wall 6 is formed on the side walls of gate electrodes 4 and 5, and diffusion layers 7 and 8 are formed. Then, interlaminar insulating layers 9, 10, and 11 of three-layered structure are selectively etched to form a contact hole 12, and a second polycrystalline silicon layer 14 and an SiO2 film 20 are formed. These are selectively etched so as to make the polycrystalline silicon layer 14 serve as a storage node electrode. In succession, a polycrystalline silicon layer 15 is formed and left unremoved only on the side face of the storage node electrode as the side wall of it so as to enhance it in electrostatic capacity.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B0 Summary of the invention C0 Prior art 1 Problems to be solved by the invention E6 Means for solving the problems F1 Effects G. Examples [Figures 1 to 4] a. One embodiment [FIGS. 1 and 2] b. Other embodiments [FIGS. 3 and 4] H1 Effects of the invention (A. Industrial application field) The present invention is a stacked capacitor type DRAM, In particular, a new stacked capacitor type DRA that can increase the capacity of the stacked capacitor per cell area.
Regarding M and its manufacturing method.

(B. Summary of the Invention) In order to increase the capacitance of a stacked capacitor per occupied area of a cell, the present invention forms a sidewall made of silicon on the side surface of a storage node electrode made of silicon, or After forming an alloy layer on the electrode, heat treatment is performed to cause one metal in the alloy layer to segregate at the interface with the base of the alloy layer.The segregated metal is removed and the alloy layer is removed by etching, and the remaining metal is removed. The storage node electrode is etched as a mask to form a columnar shape.

(C, Prior Art) As one type of dynamic RAM, a lower electrode made of polycrystalline silicon and an upper electrode made of polycrystalline silicon are placed opposite to each other on a semiconductor substrate with a dielectric film in between to form a capacitor for storing information. There is a stacked capacitor type that consists of elements, for example, monthly 5eIIlicond
uctor World 1988.2 (Press Journal) pp. 31-36 "4M.

The structure is introduced in ``The Future of 16MDRAM - Stacked Capacitance and Trench Capacitance''. This stacked capacitor type is more resistant to soft errors than the trench capacitor type, in which a groove is dug in the semiconductor substrate and a capacitive element for information storage is formed there. It has the advantage that it can be made small, and development in this regard has been very active, and the results have been introduced, for example, in Japanese Patent Application Laid-Open No. 1-120050.

(D. Problem to be Solved by the Invention) By the way, it is necessary to increase the storage capacity of stacked capacitor type dynamic RAM to 4M bits, 16M bits, and even 64M bits. In order to provide a large storage capacity, it is necessary to reduce the area occupied by each capacitive element. However, because the area occupied by the capacitive element is reduced, the capacitance must not be allowed to decrease accordingly.This is because the capacitive element must have a certain level of static capacitance in order to fulfill its function as a means of storing information in a memory cell. This is because capacity is required.

Therefore, in a stacked capacitor type dynamic RAM, it is required to increase the ratio of capacitance to the area occupied by the memory cell in order to increase the storage capacity. However, the reality is that it is extremely difficult to meet this demand.

This is because the ratio of the area occupied by the storage node electrode to the area occupied by the memory cell is increased (then the ratio of the capacitance of the stacked capacitor to the area occupied by the cell can be increased; This is because increasing the proportion of the area occupied by the node electrode in the memory cell becomes more difficult as the memory cell size becomes smaller.

The present invention has been made to solve these problems, and an object of the present invention is to increase the ratio of the capacitance of the stacked capacitor to the area occupied by the memory cell.

(E. Means for Solving Problems) The stacked capacitor type DRAM of the present invention is characterized in that a sidewall made of silicon is formed on the side surface of a storage node electrode made of silicon.

The method for manufacturing the stacked capacitor type DRAM of the present invention is as follows:
After forming an alloy layer on the storage node electrode, heat treatment is performed to cause the metal of the alloy layer to segregate at the interface with the base of the alloy layer, the segregated metal is removed, the alloy layer is removed by etching, and the remaining metal is masked. According to the stacked capacitor type DRAM of the present invention, a side wall made of a semiconductor is formed on the side surface of the storage node electrode. The surface area of the storage node electrode increases accordingly.

Therefore, the capacitance of the stacked capacitor can be increased without increasing the size of the memristor cell.

According to the manufacturing method of the stacked capacitor type DRj'M of the present invention, the storage node electrode is formed into a columnar shape by etching the metal nodules dotted thereon as a mask, so that the surface area of the storage node electrode is increased. can be done. Therefore, the capacitance of the stacked capacitor can be increased without increasing the cell size.

(G. Embodiment) [FIGS. 1 to 4] Hereinafter, the stacked capacitor type DRAM of the present invention and its manufacturing method will be explained in detail according to the illustrated embodiment.

(A, One Embodiment) [FIGS. 1 and 2] FIG. 1 is a sectional view showing one embodiment of the stacked capacitor type DRAM of the present invention.

In the drawings, 1 is a P-type semiconductor substrate, 2 is a field insulating film formed by selective oxidation of the surface of the semiconductor substrate 1, 3 is a gate insulating film, and 4 is a polygonal layer of the first layer forming the lower layer of the gate electrode. The crystalline silicon layer 5 is a refractory metal silicide layer forming the upper layer of the gate electrode, and the core layer 5 and the polycrystalline silicon layer 4 constitute a polycide gate electrode.

6 is SiOx formed on the side surface of the gate electrode 4.5.
7.8 is an n-type diffusion layer,
Light doping of n-type impurity using gate electrode 4.5 as a mask, and semiconductor using gate electrode 4.5 and sidewall 6 as a mask (in other words, using gate electrode 4.5 after sidewall formation as a mask) It is formed by doping the substrate 1 with n-type impurities.

9 is a 5iO layer, 10 is a SiN counterfeit layer, and 11 is a SiO layer, and these three layers constitute an interlayer insulating layer having a three-layer structure. The SiN layer 10, which is the intermediate layer of the interlayer insulating layer, serves as a stopper for anisotropic etching to form a side wall also made of polycrystalline silicon on the side surface of a storage node electrode made of polycrystalline silicon that will be formed later. It should play a role as a layer (formed).

12.13 are contact holes formed in the interlayer insulating layer 9, 10, 11, the contact hole 12 connects the storage node electrode to the diffusion layer 7, and the contact hole 13 connects the bit line to the diffusion layer 8. It is something that connects.

14 is a storage node electrode made of polycrystalline silicon, and 15 is a sidewall made of polycrystalline silicon formed on the side surface of the storage node electrode 14. Having the sidewall 15 in this way makes this stacked capacitor type D
This is a characteristic of RAM.

The reason why the sidewall 15 made of polycrystalline silicon is formed on the side surface of the storage node electrode 14 is to increase the substantial surface area of the storage node electrode 14, thereby increasing the capacitance of the stacked capacitor. It is.

16 is the storage node electrode 14 and the side wall 15
It is a dielectric film that covers the surface of the film, and is formed in a two-layer or three-layer structure by a SiN film and a 5ift film. A plate electrode 17 is made of polycrystalline silicon and faces the storage node electrode 14 with the dielectric film 16 interposed therebetween to form a stacked capacitor with the storage node electrode 14.

18 is an interlayer insulating film, and 19 is a bit line formed on the interlayer insulating film 18, and is made of aluminum, for example. This bit line 19 is connected to the diffusion layer 8 through the contact hole 13.

According to the present stacked capacitor type DRAM, the sidewall 15 is formed on the side surface of the storage node Y electrode 14, which has a sharp side surface and is formed substantially vertically by anisotropic etching of polycrystalline silicon. Since the surface area of the storage node electrode is substantially increased without unnecessarily expanding the space, the capacitance of the stacked capacitor can be increased accordingly. Since there is no need to unnecessarily widen the storage node electrode, flattening can be achieved by filling the narrow storage node space with a plate electrode made of polycrystalline silicon, and forming upper layer wiring such as bit lines. becomes easier.

FIGS. 2A to 2I are cross-sectional views showing a method for manufacturing the stacked capacitor type DRAM shown in FIG. 1 in order of steps.

(A) A field insulating film 2 is formed by selectively oxidizing a P-type semiconductor substrate 1, a gate insulating film 3 is formed by thermal oxidation on the surface of the element formation region of the semiconductor substrate 1, and a first layer of polycrystalline silicon is formed. A film 4 and a high melting point metal silicide film 5 are sequentially formed, this film 4.5 is patterned to form a gate electrode (word line), and n-type impurities are applied to the surface of the semiconductor substrate 1 using the gate electrode 4.5 as a mask. After dry doping, a side wall 6 made of silicon oxide is formed on the side surface of the gate electrode 4.5, and then an n impurity is ion-implanted to form a diffusion layer 7.8.

Thereafter, interlayer insulating layers 9, 10, and 11 having a three-layer structure are formed. FIG. 2(A) shows the state after the interlayer insulating layer 9.1O111 is formed.

(B) Next, as shown in FIG.
．． A contact hole 12 is formed by selectively etching 10.11.

(C) Next, as shown in Figure (C), a second layer of polycrystalline silicon 14, which will become a storage node electrode, is formed.

(D) Next, as shown in the same figure (D), 20 SiO2 films are formed. The film 20 serves as an etching stop layer that protects the storage node electrode 14 from being etched during RIE, which will be described later, to form the sidewall 15.

(E) Next, as shown in FIG. 3E, the polycrystalline silicon layer 14 and the SiO* film 20 are selectively etched to use the polycrystalline silicon layer 14 as a storage node electrode.

(F) Next, as shown in Figure (F), a polycrystalline silicon layer 15 is formed. This serves as a sidewall for increasing the capacitance of the stacked capacitor.

(G) Next, the polycrystalline silicon layer 15 is etched by RrE as shown in FIG.
The polycrystalline silicon layer 15 is made to remain as a sidewall only on the side surfaces. During this RIE etching, the 5iO- film 20 covers the storage node electrode 14,
The SiN film 10 protects the 5iOt film 9 from being etched. That is, it serves as an etching stop layer.

(H) Next, as shown in (H) of the same figure, the storage node electrode 1
4. Remove the SiO* film 20 on the surface.

(I) Next, a dielectric film 16 is formed as shown in (I) of the same figure.

After that, a polycrystalline silicon layer 17 that will become a plate electrode is formed and patterned, and then an interlayer insulating film 18 is formed.
is formed and selectively etched to form a contact hole 13 for connecting the bit line.
form 9. As a result, a stacked capacitor type DRAM shown in FIG. 1 is produced.

(b. Other Embodiments) [FIGS. 3 and 4] FIGS. 3(A) to 3(I) are cross-sectional views showing the method of manufacturing the stacked capacitor type DRAM of the present invention in the order of steps.

(A) After the formation of the diffusion layer 7, 8, 9, the interlayer insulating film 9 is formed, and the contact hole 12 is formed therein to open the diffusion layer 7, which is a general stacked capacitor type DRAM.
There is no difference from the manufacturing method. In the present stacked capacitor type DRAM manufacturing method, the interlayer insulating film 9 may have a single layer structure, unlike the method for manufacturing the stacked capacitor type DRAM shown in FIG.

By the way, after forming the contact hole 12, a thin polycrystalline silicon layer 21 of several hundred layers is formed by low pressure CVD. This polycrystalline silicon layer 21 has contact holes 12
For example, the 0th order connected to the diffusion layer 7 via the
An insulating film 22 made of 0,000 Stow is formed, and then a polycrystalline silicon layer 23 which becomes a storage node electrode is formed. FIG. 2A shows the state after the polycrystalline silicon layer 23 is formed.

(B) Next, as shown in the same figure (B), a thin film such as Sin! is applied to the surface of the polycrystalline silicon layer 23. Membrane 24 membrane type 4.

(C) Next, as shown in FIG. 2C, aluminum containing several to several tens of percent silicon, that is, an alloy layer 25 of silicon and aluminum is formed on the 5ill film 24.

(D) Next, as shown in FIG. 3D, the alloy layer 25 is selectively etched so that it remains only above the area where the storage node electrode is to be formed.

(E) Next, at a temperature of about 200 to 500°C, see Figure 3 (E
), the silicon in the alloy layer 25 is segregated at the 4 interfaces on the 2 SiO films of the alloy layer 25. 25
a is a segregated silicon nodule. Alloy layer 25
The silicon content exceeds the solid solubility limit, and the silicon that exceeds the solid solubility limit becomes nodules 25a by heat treatment and segregates at the interface.

(F) Next, the alloy layer 15 is etched with an etching solution, such as an acid, which does not attack silicon but attacks aluminum.
etching. Then, as shown in FIG. 3(F), silicon nodules 25a are formed on the surface of the 5iOa film 24 in a region corresponding to the region where the storage node electrode is to be formed.
become scattered.

(G) Next, the Sing film 22 is etched using the silicon nodule 25a as a mask, and the polycrystalline silicon layer 22 is further etched using the remaining portion of the 5iO film 22 as a mask.
3 is anisotropically etched.

During this anisotropic etching, the SiO□ film 22 acts as an etching stopper and prevents the polycrystalline silicon 21 from being etched. However, this S i Om
Film 22 is removed by wet etching. Figure 3 (
G) shows the state after the Si0g film 22 is removed.

By this process, the storage node electrode 2 made of polycrystalline silicon is
3, the columnar bodies stand in a forest. The reason for doing this is to increase the surface area of the storage node electrode 23.

(H) Next, as shown in FIG. 3(H), a thin polycrystalline silicon layer 26 is formed on the surface. The polycrystalline silicon layer 26
are the columnar storage node electrodes 23 that stand insulated from the polycrystalline silicon layer 21 to the SiO□ film 22.
Originally, the 5iOi film 22 was formed to serve as an etching stopper for etching the storage node electrode 23; 1. An edge is formed between the silicon layer 21 and the storage node electrode 23. So, it became necessary to make a connection between them, and the polycrystalline silicon layer 26 is what makes that connection.

(I) After that, as shown in FIG. 3(I), the resist film 2
7, the top of the storage node electrode 23 is masked and the polycrystalline silicon layers 21 and 26 are removed.

After that, a dielectric film is formed, a plate electrode is formed, a five-layer insulating film is formed, a contact hole for a bit contact is formed, and a bit line is formed.

For these, ordinary stacked capacitor type DRA
Since there is no difference from the manufacturing method of M, illustration and description will be omitted.

According to the manufacturing method of this stacked capacitor type DRAM, the storage node electrode is shaped into a series of columnar parts by selective anisotropic etching, so the surface area is significantly increased, and the capacitance of the stacked capacitor relative to the occupied area is reduced. increases significantly.

The mask for selectively anisotropically etching the storage node electrode is to heat-treat the alloy layer so that silicon, which is the first metal constituting it, is segregated at the interface with the base of the alloy layer, and the other The mask is formed by removing the metal aluminum by etching, and the manner in which the first metal nodules are scattered varies depending on the silicon content as shown in Figures 4 (A) and (B). Different as shown. That is, when the silicon content is small, the silicon nodules 25a as shown in FIG.
If the density of is small but the content is large, the same figure (B)
As shown in Figure 2, the density of silicon nodules 2.5a increases.

(H, Effect of the invention) As stated above, the stacked capacitor type D of the present invention
The RAM is characterized in that a storage node electrode made of silicon is formed on an interlayer insulating film having a multilayer structure including an etching stopper layer, and a sidewall made of silicon is formed on the side surface of the storage node electrode. .

Therefore, according to the stacked capacitor type DRAM of the present invention, since the sidewall made of semiconductor is formed on the side surface of the storage node electrode, the surface area of the storage node electrode increases accordingly. Therefore, the capacitance of the stacked capacitor can be increased without increasing the size of the memristor cell.

The method for manufacturing the stacked capacitor type DRAM of the present invention is as follows:
A first metal and a second metal are placed on a storage node electrode made of silicon.
forming an alloy layer that segregates by heat treatment, heat-treating the alloy layer to cause the first metal to segregate at the interface with the base of the alloy layer, and forming a liquid that corrodes the second metal; etching the alloy layer to scatter nodules of a first metal on the storage node electrode, and etching the storage node electrode using the first metal nodule as a mask to form a columnar body. That is.

Therefore, according to the method for manufacturing a stacked capacitor type DRAM of the present invention, the storage node electrode is formed into a columnar body by etching the metal nodules dotted thereon as a mask, so that the surface area of the storage node electrode is reduced. can be increased.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of the stacked capacitor type DRAM of the present invention, and FIGS.
3 and 4 show other embodiments of the present invention. FIGS. 4(A) and 4(B) are cross-sectional views showing the manufacturing method of a capacitor type DRAM in the order of steps, and FIGS. 4(A) and 4(B) are plan views showing differences in the manner in which masks are scattered depending on the metal composition ratio of the alloy layer. Explanation of symbols 9 to 11 10... 14... 15... 23... Interlayer insulating film, - Etching stop layer, - Storage node electrode. - Side wall, - Storage node electrode, 25 - Alloy layer, 25a - First metal nodule. 14 Storage Node Electrode 5 Sidefall No. 1? Figure 4 is a plan view showing the state of the mask forming layer H.

Claims (2)

[Claims] (1) A stacked capacitor characterized in that a storage node electrode made of silicon is formed on an interlayer insulating film having a multilayer structure including an etching stopper layer, and a sidewall made of silicon is formed on the side surface of the storage node electrode. type DRAM (2) An alloy layer made of a first metal and a second metal that segregates by heat treatment is formed on the storage node electrode made of silicon, and the alloy layer is heat treated to form the first metal into the alloy layer. etching the alloy layer with a liquid that corrodes the second metal to scatter nodules of the first metal above the storage node electrode; A method for manufacturing a stacked capacitor type DRAM, characterized in that the storage node electrode is etched as a mask to form a columnar body.