JPH03101261A - Formation of capacity element - Google Patents
Formation of capacity elementInfo
- Publication number
- JPH03101261A JPH03101261A JP1239135A JP23913589A JPH03101261A JP H03101261 A JPH03101261 A JP H03101261A JP 1239135 A JP1239135 A JP 1239135A JP 23913589 A JP23913589 A JP 23913589A JP H03101261 A JPH03101261 A JP H03101261A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- etching
- polycrystalline silicon
- side electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title description 5
- 238000005530 etching Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 8
- 230000000593 degrading effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 30
- 239000003990 capacitor Substances 0.000 abstract description 8
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.
Ａ、産業上の利用分野
Ｂ０発明の概要
Ｃ８従来技術
り１発明が解決しようとする問題点
Ｅ８問題点を解決するための手段
Ｆ１作用
Ｇ、実施例［第１図、第２図］
Ｈ１発明の効果
（Ａ、産業上の利用分野）
本発明は容量素子の形成方法、特にダイナミックＲＡＭ
の記憶用容量素子のように占有面積に対する静電容量の
比が大きな容量素子を形成する方法に関する。A. Industrial field of application B0 Summary of the invention C8 Prior art R1 Problems to be solved by the invention E8 Means for solving the problems F1 Effects G. Examples [Figures 1 and 2] H1 Invention Effects (A, Industrial Application Field) The present invention relates to a method for forming a capacitive element, particularly for a dynamic RAM.
The present invention relates to a method for forming a capacitive element having a large ratio of capacitance to occupied area, such as a storage capacitive element.
（Ｂ、発明の概要）
本発明は、容量素子の形成方法において、容量素子の占
有面積に対する静電容量の比を太き（するため、
下側電極膜の表面の平坦度を劣化させ、該電極膜の表面
部を異方性エツチングしてエツチング残渣を生ぜしめ、
該エツチング残渣をマスクとする異方性エツチングをし
て下側電極膜に深い溝を形成することにより、
下側電極膜の表面積を広くしようとするものである。(B. Summary of the Invention) In a method for forming a capacitive element, the present invention increases the ratio of capacitance to the area occupied by the capacitive element, thereby deteriorating the flatness of the surface of the lower electrode film and The surface of the electrode film is anisotropically etched to produce an etching residue,
The purpose is to widen the surface area of the lower electrode film by forming deep grooves in the lower electrode film by performing anisotropic etching using the etching residue as a mask.
（Ｃ，従来技術）
ダイナミックＲＡＭの一つのタイプとして半導体基板上
において多結晶シリコンからなる下側電極と同じく多結
晶シリコンからなる上側電極とを誘電体膜を挟んで対向
させて情報蓄積用の容量素子を構成した積層容量タイプ
があり、例えば月刊Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ Ｗｏ
ｒｌｄ １９８Ｌ２ （プレスジャーナル社）３１〜
３６頁ｒ４Ｍ、１６ＭＤＲＡＭの行方−積層容量と溝形
容量−」に構造が紹介されている。このような積層容量
タイプは半導体基板に溝を掘ってそこに情報蓄積用の容
量素子を形成した溝形容量に比較してソフトエラーに強
（、半導体基板に形成する拡散層の面積が小さくて済む
という利点を有しており、これについての開発も非常に
盛んに行なわれている。(C, Prior Art) As one type of dynamic RAM, a lower electrode made of polycrystalline silicon and an upper electrode made of polycrystalline silicon are placed opposite to each other on a semiconductor substrate with a dielectric film in between to form a capacitor for storing information. There is a multilayer capacitor type that consists of an element, for example, in the monthly Sem1conductor Wo
rld 198L2 (Press Journal) 31~
The structure is introduced in "The future of 4M, 16MDRAM - Stacked capacitance and trench capacitance" on page 36. This type of multilayer capacitor is more resistant to soft errors than the trench type capacitor, in which a trench is dug in the semiconductor substrate and a capacitive element for information storage is formed there. It has the advantage of being easy to use, and development in this regard is very active.
（Ｄ、発明が解決しようとする問題点）ところで、積層
容量タイプのダイナミックＲＡＭにおいて４Ｍビット、
１６Ｍビットの記憶容量を備えるには各容量素子の占有
面積を小さくすることが必要である。しかし、容量素子
の占有面積を小さくしたために静電容量がそれに伴って
減少することは許されない。というのは容量素子がメモ
リセルの情報蓄積手段としての機能を果たすには、ある
程度以上の静電容量が必要だからである。(D. Problem to be solved by the invention) By the way, in a stacked capacitor type dynamic RAM, 4M bits,
In order to provide a storage capacity of 16 Mbits, it is necessary to reduce the area occupied by each capacitive element. However, because the area occupied by the capacitive element is reduced, it is not allowed that the capacitance decreases accordingly. This is because a capacitive element requires a certain level of capacitance in order to function as an information storage means of a memory cell.
従って、積層容量タイプのダイナミックＲＡＭにおいて
は大記憶容量化のために占有面積に対する静電容量の比
を太き（することが要求されているのである。しかし、
この要求に応えることは非常に難しいのが実情である。Therefore, in a stacked capacitor type dynamic RAM, it is required to increase the ratio of capacitance to occupied area in order to increase storage capacity.However,
The reality is that it is extremely difficult to meet this demand.
本発明はこのような問題点を解決すべく為されたもので
あり、容量素子の占有面積に対する静電容量の比を大き
くすることを目的とする。The present invention has been made to solve these problems, and an object of the present invention is to increase the ratio of capacitance to the area occupied by a capacitive element.
（Ｅ、問題点を解決するための手段）
本発明容量素子の形成方法は上記問題点を解決するため
、下側電極膜の表面の平坦度を劣化させ、該電極膜の表
面部を異方性エツチングしてエツチング残渣を生ぜしめ
、該エツチング残渣をマスクとする異方性エツチングを
して下側電極膜に深い溝を形成することを特徴とする。(E. Means for Solving the Problems) In order to solve the above-mentioned problems, the method for forming a capacitive element of the present invention deteriorates the flatness of the surface of the lower electrode film and makes the surface part of the electrode film anisotropic. The method is characterized in that it performs anisotropic etching to generate an etching residue, and then performs anisotropic etching using the etching residue as a mask to form a deep groove in the lower electrode film.
（Ｆ、作用）
本発明容量素子の形成方法によれば、下側電極膜の表面
の平坦度を悪（したうえで異方性エツチングすることに
より下側電極膜の表面上に小さなエツチング残渣を多数
散在させることができ、そして、そのエツチング残渣を
マスクとして下側電極膜を異方性エツチングすることに
より多数の深い溝を形成することができる。(F, Effect) According to the method for forming a capacitive element of the present invention, by improving the flatness of the surface of the lower electrode film and then performing anisotropic etching, a small etching residue is left on the surface of the lower electrode film. A large number of deep grooves can be formed by anisotropically etching the lower electrode film using the etching residue as a mask.
従って、下側電極膜の表面積を広くすることができ、こ
の下側電極膜の表面に誘電体膜を介して上側電極膜を形
成することにより電極膜の占有面積に比して電極膜対向
面積を著しく広くすることができる。Therefore, the surface area of the lower electrode film can be increased, and by forming the upper electrode film on the surface of the lower electrode film via the dielectric film, the area facing the electrode film is larger than the area occupied by the electrode film. can be made significantly wider.
従って、容量素子の占有面積に対する静電容量の比を大
きくすることができる。Therefore, the ratio of capacitance to the area occupied by the capacitive element can be increased.
（Ｇ、実施例）［第１図、第２図］
以下、本発明容量素子の形成方法を図示実施例に従って
詳細に説明する。(G, Example) [FIGS. 1 and 2] Hereinafter, a method for forming a capacitive element of the present invention will be described in detail according to the illustrated example.
第１図（Ａ）乃至（Ｊ）は本発明容量素子の形成方法の
一つの実施例を工程順に示す断面図である。FIGS. 1A to 1J are cross-sectional views showing one embodiment of the method for forming a capacitive element of the present invention in the order of steps.
（Ａ）Ｐ型半導体基板１を選択酸化することによりフィ
ールド絶縁膜２を形成し、半導体基板１の素子形成領域
表面に加熱酸化によりゲート絶縁膜３を形成し、第１層
目の多結晶シリコン膜４、高融点金属シリサイド膜５を
順次形成し、この膜４．５をバターニングしてゲート電
極（ワード線）とし、シリコン酸化物からなるサイドウ
オール６をゲート電極４．５の側面に形成し、その後、
ｎ型不純物をイオン打込みして拡散層７．８を形成する
（尚、サイドウオール６の形成前にも軽くｎ型不純物を
イオン打込み、即ちライトドープしておくことにより拡
散層７．８と一体の低不純物濃度領域も形成される）。(A) A field insulating film 2 is formed by selectively oxidizing a P-type semiconductor substrate 1, a gate insulating film 3 is formed by thermal oxidation on the surface of the element formation region of the semiconductor substrate 1, and a first layer of polycrystalline silicon is formed. A film 4 and a high melting point metal silicide film 5 are sequentially formed, this film 4.5 is patterned to form a gate electrode (word line), and a sidewall 6 made of silicon oxide is formed on the side surface of the gate electrode 4.5. And then,
A diffusion layer 7.8 is formed by ion-implanting an n-type impurity (before the formation of the sidewall 6, n-type impurity is lightly ion-implanted, i.e., lightly doped, so that it is integrated with the diffusion layer 7.8). A low impurity concentration region is also formed).
次に、眉間絶縁膜９を形成し、これを選択的にエツチン
グすることによりコンタクトホール１０ａ、１０ｂを形
成する。第１図（Ａ）はこのコンタクトホール１０ａ、
１０ｂを形成した後の状態を示す。Next, a glabellar insulating film 9 is formed and selectively etched to form contact holes 10a and 10b. FIG. 1(A) shows this contact hole 10a,
The state after forming 10b is shown.
（Ｂ）次に、第１図（Ｂ）に示すように、数千から１号
数千人程度の膜厚を有する下側電極膜となる多結晶シリ
コン膜１１をＣＶＤ法により形成する。(B) Next, as shown in FIG. 1(B), a polycrystalline silicon film 11 that will become the lower electrode film and has a thickness of about several thousand to several thousand layers is formed by the CVD method.
（Ｃ）次に、上記多結晶シリコン膜１１の表面に薄い高
濃度ＰＳＧ膜１２をＣＶＤ法により形成し、次いで該Ｐ
ＳＧ膜１２表面に薄い（数百人）多結晶シリコン膜１３
を減圧ＣＶＤにより形成する。第１図（Ｃ）は多結晶シ
リコン膜１３形成後の状態を示す、この図から明らかな
ように、多結晶シリコン膜１３は下地が高濃度のＰＳＧ
膜１膜受２るので表面の平坦度が非常に悪く、凹凸が激
しい。(C) Next, a thin high concentration PSG film 12 is formed on the surface of the polycrystalline silicon film 11 by the CVD method, and then the PSG film 12 is formed on the surface of the polycrystalline silicon film 11.
A thin (several hundred) polycrystalline silicon film 13 on the surface of the SG film 12
is formed by low pressure CVD. FIG. 1(C) shows the state after the formation of the polycrystalline silicon film 13. As is clear from this figure, the polycrystalline silicon film 13 has a base made of highly concentrated PSG.
Since there are one film and two film supports, the surface flatness is very poor and there are severe irregularities.
（Ｄ）次に、上記多結晶シリコン膜１３及びその下地の
ＰＳＧ膜１膜受２してエツチング残渣１４．１４、・・
・が点在するようなエツチング条件で異方性エツチング
を行なう、第１図（Ｄ）はこの異方性エツチングの終了
後の状態を示す。(D) Next, the polycrystalline silicon film 13 and the underlying PSG film 1 are etched to form etching residues 14, 14, .
Anisotropic etching is carried out under etching conditions such that * is scattered. FIG. 1(D) shows the state after completion of this anisotropic etching.
（Ｅ）次に、同図（Ｅ）に示すように上記エツチング残
渣１４．１４、・・・をマスクとして多結晶シリコン膜
１１を異方性エツチングすることにより深い溝１５．１
５、・・・を形成する。(E) Next, as shown in Figure (E), the polycrystalline silicon film 11 is anisotropically etched using the etching residues 14.14, . . . as a mask to form deep grooves 15.1.
5,... is formed.
（Ｆ）次に、同図（Ｆ）に示すように第２層目の多結晶
シリコン膜１１上のエツチング残渣１４．１４、・・・
を除去する。第２図はその残渣除去後の状態を示す平面
図である。(F) Next, as shown in the same figure (F), etching residues 14, 14, . . . on the second layer polycrystalline silicon film 11 are removed.
remove. FIG. 2 is a plan view showing the state after the residue has been removed.
（Ｇ）次に、第１図（Ｆ）に示すように多結晶シリコン
膜１１を選択的にエツチングすることによりｎ十型拡散
層７と接続される容量素子の下側電極膜１１ａ、ｎ”型
拡散１１８とビット線（後で形成される）とを中継する
中継電極膜１１ｂを形成する。(G) Next, as shown in FIG. 1(F), by selectively etching the polycrystalline silicon film 11, the lower electrode film 11a, n'' of the capacitive element connected to the n+ type diffusion layer 7 is etched. A relay electrode film 11b is formed to relay between the type diffusion 118 and the bit line (to be formed later).
（Ｈ）次に、同図（Ｈ）に示すように、表面にナイトラ
イド膜及びＳｉＯ□膜からなるＯＮＯ又はＮｏ構造の誘
電体膜１６を形成する。(H) Next, as shown in FIG. 3H, a dielectric film 16 having an ONO or No structure consisting of a nitride film and a SiO□ film is formed on the surface.
（１）次に、同図（Ｉ）に示すように上記誘電体膜１６
を選択的にエツチングすることにより少なくとも上記中
継電極膜１１ｂ表面上の誘電体膜１６を除去する。さも
ないと、中継下側電極膜１１ｂが中継の役割を果たし得
ないからである。(1) Next, as shown in FIG.
By selectively etching, at least the dielectric film 16 on the surface of the relay electrode film 11b is removed. Otherwise, the relay lower electrode film 11b cannot fulfill the role of relay.
（Ｊ）その後、上側電極膜となる第３層目の多結晶シリ
コン膜１７をＣＶＤにより形成し、それを選択的にエツ
チングすることにより上記下側電極膜１１ａと誘電体膜
１６を介して対向して容量素子をつくる上側電極膜１７
ａと、上記中継下側電極膜１１ｂと接する中継上側電極
膜１７ｂを形成する。そして、眉間絶縁膜１８を形成し
、該眉間絶縁膜１８をフォトエツチングすることにより
ビット線取出し用コンタクトホール１９を形成し、その
後、例えばアルミニウムからなるビット線２０を形成す
る。第１図（Ｄ）はビット線２０形成後の状態を示す。(J) Thereafter, a third layer of polycrystalline silicon film 17, which will become the upper electrode film, is formed by CVD and selectively etched to face the lower electrode film 11a with the dielectric film 16 interposed therebetween. Upper electrode film 17 that forms a capacitive element
a, and a relay upper electrode film 17b which is in contact with the relay lower electrode film 11b is formed. Then, a glabellar insulating film 18 is formed, and a contact hole 19 for taking out a bit line is formed by photo-etching the glabellar insulating film 18. Thereafter, a bit line 20 made of, for example, aluminum is formed. FIG. 1(D) shows the state after the bit line 20 is formed.
以上に述べたところから明らかなように、本容量素子の
形成方法は、先ず下側電極膜となる多結晶シリコン膜１
１の表面に膜厚の薄い高濃度ＰＳＧ膜１２を介して薄い
多結晶シリコン膜１３を形成することにより表面の平坦
度を低下させる。そして、表面の平坦度を低下させた状
態の多結晶シリコン膜１１のその表面を適宜なエツチン
グ条件で異方性エツチングすることにより点在せしめた
エツチング残渣１４．１４、・・・をマスクとして多結
晶シリコン膜１１をエツチングすることにより該多結晶
シリコン膜１１に深い溝１５．１５、・・・を形成し、
それによって多結晶シリコン膜１１の表面積を広くする
。そして、この表面積を広（した多結晶シリコン膜１１
を情報蓄積用容量素子の下側電極膜として用い、この下
側電極膜の表面に誘電体膜１６を形成し該誘電体膜１６
を介して上側電極膜１７と対向させるので、占有面積に
対する静電容量の比の大きな容量素子を得ることができ
る。As is clear from the above description, the method for forming this capacitive element begins with forming a polycrystalline silicon film, which will become the lower electrode film.
By forming a thin polycrystalline silicon film 13 on the surface of the substrate 1 via a thin high-concentration PSG film 12, the flatness of the surface is reduced. Then, the surface of the polycrystalline silicon film 11 with reduced surface flatness is anisotropically etched under appropriate etching conditions, and the etching residues 14, 14, . . . By etching the crystalline silicon film 11, deep grooves 15, 15, . . . are formed in the polycrystalline silicon film 11,
This increases the surface area of polycrystalline silicon film 11. Then, the polycrystalline silicon film 11 with this surface area expanded (
is used as a lower electrode film of an information storage capacitor, and a dielectric film 16 is formed on the surface of this lower electrode film.
Since the upper electrode film 17 is opposed to the upper electrode film 17 via the upper electrode film 17, a capacitive element having a large ratio of capacitance to occupied area can be obtained.
尚、本実施例においては、多結晶シリコン膜１１上に膜
厚の薄い高濃度ＰＳＧ膜１２を形成し、該ＰＳＧ膜１膜
上２上い多結晶シリコン膜１３を形成することにより表
面の平坦度を低下せしめている。しかしながら、平坦度
を低下せしめる方法は必ずしもこれに限定されず、例え
ば、多結晶シリコン膜１１上にノンドープの薄いＳｔｏ
ｗ膜を形成し、この膜上に薄い多結晶シリコン膜をデポ
ジションし、その後プレポジションによりリンＰをその
ＳｌＯ□膜に高濃度拡散させるようにしても良い。In this embodiment, a thin high-concentration PSG film 12 is formed on the polycrystalline silicon film 11, and a thick polycrystalline silicon film 13 is formed on the PSG film 1, thereby making the surface flat. It is reducing the level of However, the method of reducing the flatness is not necessarily limited to this. For example, a thin non-doped Sto film is applied on the polycrystalline silicon film 11.
It is also possible to form a W film, deposit a thin polycrystalline silicon film on this film, and then diffuse phosphorus P at a high concentration into the SlO□ film by prepositioning.
（Ｈ，発明の効果）
以上に述べたように、本発明容量素子の形成方法は、基
板上の下側電極膜の表面の平坦度を劣化させ、次いで、
上記電極膜の表面部に対してエツチング残渣が残るよう
に異方性エツチングし、次いで、上記エツチング残渣を
マスクとして上記電極膜を異方性エツチングすることに
より深い溝を形成し、その後、上記下側電極膜表面に誘
電体膜及び該下側電極膜と対向する上側電極膜を形成す
ることを特徴とするものである。(H, Effects of the Invention) As described above, the method for forming a capacitive element of the present invention deteriorates the flatness of the surface of the lower electrode film on the substrate, and then
Anisotropic etching is performed on the surface of the electrode film so that an etching residue remains, and then deep grooves are formed by anisotropically etching the electrode film using the etching residue as a mask. This method is characterized in that a dielectric film and an upper electrode film facing the lower electrode film are formed on the surface of the side electrode film.
従って、本発明容量素子の形成方法によれば、下側電極
膜の表面の平坦度を悪くしたうえで異方性エツチングす
ることにより下側電極膜の表面上に小さなエツチング残
渣を多数散在させることができ、そして、そのエツチン
グ残渣をマスクとして下側電極膜を異方性エツチングす
ることにより多数の深い溝を形成することができる。Therefore, according to the method for forming a capacitive element of the present invention, by performing anisotropic etching after reducing the flatness of the surface of the lower electrode film, many small etching residues are scattered on the surface of the lower electrode film. Then, by anisotropically etching the lower electrode film using the etching residue as a mask, many deep grooves can be formed.
従って、下側電極膜の表面積を広くすることができ、こ
の下側電極膜の表面に誘電体膜を介して上側電極膜を形
成するので、電極膜の占有面積に比して電極膜対向面積
を著しく広くすることができる。Therefore, the surface area of the lower electrode film can be increased, and since the upper electrode film is formed on the surface of the lower electrode film via the dielectric film, the area facing the electrode film is larger than the area occupied by the electrode film. can be made significantly wider.
依って、容量素子の占有面積に対する静電容量の比を大
きくすることができるのである。Therefore, the ratio of capacitance to the area occupied by the capacitive element can be increased.
第１図（Ａ）乃至（Ｊ）は本発明容量素子の形成方法の
一つの実施例を工程順に示す断面図、第２図は溝形成後
の状態を示す平面図である。
符号の説明
１・・・基板、
１１、ｌｌａ・・・ （下側）電極膜、１５・・・深い
溝、
１６・・・誘電体膜、
１７．１７ａ・・・ （上側）電極膜。
１５・・・溝
溝Ｙ／成後の状態を示す平面図
第２図FIGS. 1A to 1J are cross-sectional views showing one embodiment of the method for forming a capacitive element of the present invention in the order of steps, and FIG. 2 is a plan view showing the state after grooves are formed. Explanation of symbols 1... Substrate, 11, lla... (lower side) electrode film, 15... deep groove, 16... dielectric film, 17.17a... (upper side) electrode film. 15...Groove Y/Front view showing the state after formation Figure 2
Claims (1)
残るように異方性エッチング処理を施し、 次いで、上記エッチング残渣をマスクとして上記電極膜
を異方性エッチングすることにより深い溝を形成し、 その後、上記電極膜表面に誘電体膜及び該電極膜と対向
する電極膜を形成する ことを特徴とする容量素子の形成方法(1) Degrading the flatness of the surface of the electrode film on the substrate, then performing anisotropic etching so that etching residue remains on the surface of the electrode film, and then using the etching residue as a mask. A method for forming a capacitive element, comprising forming a deep groove by anisotropically etching the electrode film, and then forming a dielectric film on the surface of the electrode film and an electrode film opposing the electrode film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1239135A JPH03101261A (en) | 1989-09-14 | 1989-09-14 | Formation of capacity element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1239135A JPH03101261A (en) | 1989-09-14 | 1989-09-14 | Formation of capacity element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101261A true JPH03101261A (en) | 1991-04-26 |
Family
ID=17040295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1239135A Pending JPH03101261A (en) | 1989-09-14 | 1989-09-14 | Formation of capacity element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101261A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0543616A2 (en) * | 1991-11-19 | 1993-05-26 | Samsung Electronics Co. Ltd. | A capacitor and method for making a capacitor |
| US5266514A (en) * | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
| JPH0620958A (en) * | 1992-04-10 | 1994-01-28 | Internatl Business Mach Corp <Ibm> | Formation of rough silicon surface and its application |
| JPH0669419A (en) * | 1992-06-02 | 1994-03-11 | Internatl Business Mach Corp <Ibm> | Micromask |
| JPH06140569A (en) * | 1991-11-16 | 1994-05-20 | Samsung Electron Co Ltd | Capacitor of semiconductor device and its manufacture as well as semiconductor device provided with said capacitor and its manufacture |
| JPH06326268A (en) * | 1993-04-20 | 1994-11-25 | Hyundai Electron Ind Co Ltd | Capacitor of dram cell and preparation thereof |
| JPH06342889A (en) * | 1991-08-23 | 1994-12-13 | Samsung Electron Co Ltd | Manufacture of high-integration semiconductor device provided with high-volume capacitor |
| JPH0774320A (en) * | 1993-08-31 | 1995-03-17 | Nec Corp | Manufacture of semiconductor device |
-
1989
- 1989-09-14 JP JP1239135A patent/JPH03101261A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06342889A (en) * | 1991-08-23 | 1994-12-13 | Samsung Electron Co Ltd | Manufacture of high-integration semiconductor device provided with high-volume capacitor |
| JPH06140569A (en) * | 1991-11-16 | 1994-05-20 | Samsung Electron Co Ltd | Capacitor of semiconductor device and its manufacture as well as semiconductor device provided with said capacitor and its manufacture |
| EP0543616A2 (en) * | 1991-11-19 | 1993-05-26 | Samsung Electronics Co. Ltd. | A capacitor and method for making a capacitor |
| US5350707A (en) * | 1991-11-19 | 1994-09-27 | Samsung Electronics Co., Ltd. | Method for making a capacitor having an electrode surface with a plurality of trenches formed therein |
| EP0867927A2 (en) * | 1991-11-19 | 1998-09-30 | Samsung Electronics Co. Ltd. | A capacitor and method for making a capacitor |
| EP0867927A3 (en) * | 1991-11-19 | 1999-03-10 | Samsung Electronics Co. Ltd. | A capacitor and method for making a capacitor |
| JPH0620958A (en) * | 1992-04-10 | 1994-01-28 | Internatl Business Mach Corp <Ibm> | Formation of rough silicon surface and its application |
| JPH0669419A (en) * | 1992-06-02 | 1994-03-11 | Internatl Business Mach Corp <Ibm> | Micromask |
| US5266514A (en) * | 1992-12-21 | 1993-11-30 | Industrial Technology Research Institute | Method for producing a roughened surface capacitor |
| JPH06326268A (en) * | 1993-04-20 | 1994-11-25 | Hyundai Electron Ind Co Ltd | Capacitor of dram cell and preparation thereof |
| JPH0774320A (en) * | 1993-08-31 | 1995-03-17 | Nec Corp | Manufacture of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR900007606B1 (en) | Semiconductor memory | |
| JPH0294471A (en) | Semiconductor storage device and manufacture thereof | |
| JPH01243573A (en) | Semiconductor memory device and its manufacture | |
| JP3222944B2 (en) | Method for manufacturing capacitor of DRAM cell | |
| JPH03101261A (en) | Formation of capacity element | |
| JPS6118167A (en) | Semiconductor device | |
| JPH03165552A (en) | Stacked capacitor type dram and manufacture thereof | |
| JPS6156445A (en) | Semiconductor device | |
| JPH01175756A (en) | Semiconductor device and manufacture thereof | |
| JPS62286269A (en) | Dram cell and manufacture thereof | |
| JP2772375B2 (en) | Semiconductor storage device | |
| JPS6340362A (en) | Semiconductor storage device | |
| JPS6342164A (en) | Manufacture of semiconductor integrated circuit device | |
| JPH1117139A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JP3317736B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2931371B2 (en) | Semiconductor capacitive element and method of manufacturing the same | |
| JP3416929B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3390589B2 (en) | Method for manufacturing semiconductor memory device | |
| JPS61225851A (en) | Semiconductor device and manufacture thereof | |
| JPH0734451B2 (en) | Method for manufacturing semiconductor device | |
| JP2827377B2 (en) | Semiconductor integrated circuit | |
| JPS63197365A (en) | Manufacture of semiconductor device | |
| JPH04264766A (en) | Manufacture of semiconductor device | |
| JPH02267962A (en) | Semiconductor memory cell and its manufacture | |
| KR960012255B1 (en) | Capacitor and manufacturing method thereof |