JP2690434B2 - Capacitor for semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor having a high capacitance formed in a restricted region on a substrate, and more particularly to a source region and a drain region formed on a semiconductor substrate and a gate adjacent to these regions. A transfer transistor composed of an electrode and a storage electrode in contact with the source region, the storage electrode having a large number of microcylinders and a large number of microtrenches, a dielectric layer covering the storage electrode, and a plate electrode covering the dielectric layer. The present invention relates to a memory cell of a semiconductor device having a storage capacitor configured.

[0002]

2. Description of the Related Art Generally, a dynamic NAND access memory (hereinafter referred to as DRAM) has a large number of memory cells each of which is composed of one transfer transistor and one storage capacitor. Therefore, the occupied area of the DRAM increases with the high integration of the memory cell. However, since such an increase in area causes a decrease in yield, it is necessary to realize high integration of memory cells without increasing the area. For that purpose, it is required to increase the capacity without increasing the occupied area of the storage capacitor within the limited narrow area given to the storage capacitor. Various techniques such as a stack capacitor cell and a trench capacitor cell have been proposed as a method for responding to such a demand.

Among them, the stack capacitor cell is widely used in megabit DRAM because it has a simpler manufacturing process than the trench capacitor cell and has higher immunity to soft errors. In the stack capacitor cell, a method of increasing the surface area of the storage electrode, a method of decreasing the thickness of the dielectric film, in order to increase the capacity of the storage capacitor in a limited area,
Alternatively, a method using a dielectric having a high dielectric constant has been proposed.

As a conventional example for increasing the surface area of the storage electrode, the storage electrode is engraved.
ve) technology is “Extended Abstracts of the 21st Con
conference on Solid State Devices and Materials (SS
DM) 1989, pp. 137-140 is disclosed in ". This technique, polycrystalline silicon is deposited by the LPCVD method on a silicon substrate of N-type which is selectively oxidized, and the polycrystalline silicon that is the deposition using a POCl ₃ source diffusion And doped on the doped polycrystalline silicon by spin-on-glass (spin-on-glas).
s: SOG) and a resist are applied, the film of the mixture is baked, and the SOG is etched in an HF solution to leave only resist particles on the polycrystalline silicon, and the dispersed resist particles are used as an etching mask. As a result, the polycrystalline silicon is etched, the resist particles are removed, and the polycrystalline silicon is patterned to form a storage electrode. in short,
By using the resist particles remaining on the polycrystalline silicon as an etching mask to form the engraved storage electrode, the surface area of the storage electrode is increased. At this time, the degree of increase in the surface area of the storage electrode is determined by the size of the resist particles and the etching time of polycrystalline silicon. The size of the resist particles is adjusted by the mixture ratio of the resist and SOG and the thickness of the mixture applied on the polycrystalline silicon. However, in such a method, the use of a resist having a uniform particle size, and the resist and SO
Since it is necessary to adjust the thickness of the mixture to be applied according to the mixing ratio of G, there are problems in terms of reproducibility and reliability when engraving the storage electrode. Furthermore, the complexity of the engraving process to increase the surface area is also a problem.

Meanwhile, as another conventional example for increasing the surface area of the storage electrode, a hemispherical grain (Hemispher grain) is used.
ical-Grein) A memory cell having a storage electrode is
EDM, 1990, pp. 655-656 "(or S
SDM, 1990, pp. 873-876 and SSD
M, 1990, pp. 869-872). This technique takes advantage of the fact that, during deposition of polycrystalline silicon by the LPCVD method, under certain conditions polycrystalline silicon has bumps of silicon or an uneven surface with hemispherical grains. It is disclosed in the paper that the surface of such unevenness appears strongly in a narrow temperature range (5 ° C.) around the transition temperature from amorphous to polycrystal, and the surface area of the storage electrode is increased about twice as much as before. ing. According to this method, the deposition temperature can be sufficiently controlled within the range of 5 ° C. even with the equipment currently used, so that there is an advantage that the manufacturing process becomes easy and highly reliable reproducibility can be obtained. However, since the surface area can be increased only about twice as much as that of the conventional storage electrode, there is a limit in using it for dozens or hundreds of megabit DRAM which requires a high capacity due to a smaller area.

[0006]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a storage capacitor having a higher capacity within a limited area. Also, within the restricted area,
An object of the present invention is to provide a storage capacitor having a storage electrode having a further increased surface area. Further, it is an object of the present invention to provide a storage capacitor having a higher capacity within a limited area by a simpler manufacturing process. It is another object of the present invention to provide a semiconductor memory device having a storage capacitor with high capacity and high reliability within a limited area. Still another object of the present invention is to provide a semiconductor memory device having a storage capacitor having a high capacity and good reproducibility within a limited area.

[0007]

In order to achieve such an object, the present invention provides a memory cell of a semiconductor memory device comprising a transfer transistor and a storage capacitor, wherein the transfer transistor is of a first conductivity type. A source region and a drain region of the second conductivity type formed on the semiconductor substrate, and a first region adjacent to the source region and the drain region and insulated from the channel region between the source region and the drain region through a gate insulating film. A field oxide film is formed on the semiconductor substrate so as to be adjacent to the source region, and the storage capacitor has the first source layer and the first insulating layer for insulating the first conductor layer. And at least a portion of the first conductor layer and at least a portion of the field oxide film. A first electrode surface of a storage capacitor in a memory cell including a first electrode formed to cover the first electrode, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer. Further, there is provided a memory cell characterized in that a large number of microcylinders having a cylindrical shape and a hemispherical convex portion on the bottom surface are formed. In addition, the micro in the first electrode of the storage capacitor
A memory cell in which a large number of micro trenches are formed in a portion other than the cylinder is provided.

Further, in a restricted area on the substrate, the first electrode of the conductor layer extended on the insulating layer, the dielectric layer formed on the first electrode, and the dielectric layer formed on the dielectric layer are formed. A capacitor having a second electrode, wherein the first electrode is provided with a large number of microcylinders having a cylindrical shape and a hemispherical convex portion on the bottom surface. In addition, a capacitor having a large number of micro trenches is provided in a portion other than the micro cylinder in the first electrode of the storage capacitor.

Alternatively, in a memory cell of a semiconductor memory device including a transfer transistor and a storage capacitor, the transfer transistor is a second conductivity type source region and a drain region formed on a first conductivity type semiconductor substrate. A first conductor layer adjacent to the source region and the drain region and insulated from the channel region between the source region and the drain region via a gate insulating film, and a first insulating layer for insulating the first conductor layer A second conductive layer formed on the semiconductor substrate, the field oxide film being formed on the semiconductor substrate so as to be adjacent to the source region, and extending on the first insulating layer. A second insulating layer is formed to insulate the second conductor layer, and the storage capacitor contacts the source region and the first capacitor. A first electrode of a conductor layer formed to overlap at least a part of the body layer and at least a part of the field oxide film, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer In a memory cell constituted by (1) and (2), a plurality of micro-cylinders having a cylindrical shape and a hemispherical convex portion on the bottom surface are formed on the first electrode of the storage capacitor. In addition, in the portion other than the micro cylinder in the first electrode of the storage capacitor,
Provided is a memory cell in which a large number of micro trenches are formed. In these cases, the surface of the second insulating layer is preferably flattened.

In a memory cell of a semiconductor memory device including a transfer transistor and a storage capacitor, the transfer transistor includes a source region and a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type. A first conductor layer adjacent to the source region and the drain region and insulated from the channel region between the source region and the drain region via a gate oxide film, and an insulating layer for insulating the first conductor layer. A field oxide layer is formed on the semiconductor substrate adjacent to the source region, the storage capacitor contacts the source region, and includes at least a portion of the first conductor layer and at least a portion of the field oxide layer. The first electrode of the conductor layer formed so as to overlap the first electrode and the first electrode. In a memory cell including a dielectric layer and a second electrode covering the dielectric layer, the first electrode of the storage capacitor has a first conductor formed by penetrating a number of microcylinders with the insulating layer as a bottom surface. A memory cell comprising a layer and a thin second conductor layer covering the first conductor layer. In addition, the microphone on the first electrode of the storage capacitor
Provided is a memory cell in which a large number of micro- trenchs having the insulating layer as a bottom face are formed to penetrate through a portion other than the cylinder.

Forming an electrode of a capacitor having a microcylinder (and a microtrench) as described above 1
As one manufacturing method, the present invention is a method of forming a storage electrode of a capacitor having a shape having a large number of microcylinders, the method comprising the step of forming a conductor layer having a hemispherical protrusion on the surface as the storage electrode, The step of forming an etching mask layer on each side surface of the hemispherical protrusion so that the top of the protrusion is exposed, and the step of performing anisotropic etching using the etching mask layer as a mask. A method of forming the same is provided. In this case, it is more preferable to further include a step of removing sharp corners of the conductor layer after anisotropic etching.

Alternatively, there is provided a method of forming a storage electrode of a capacitor having a shape having a large number of microcylinders, wherein a step of flattening the surface of an insulating layer formed under the storage electrode, and a large number of hemispherical surfaces. Forming a conductor layer having a protrusion on the insulating layer, forming an etching mask layer on each side surface of the protrusion of the conductor layer, penetrating the conductor layer with the etching mask layer as a mask, A step of performing anisotropic etching until a part of the surface of the insulating layer is exposed, and a step of forming a thin second conductor layer that covers the surface of the conductive layer and the exposed surface of the insulating layer. A featured forming method is provided.

In a method of manufacturing a storage capacitor of a semiconductor memory device using a polycrystalline silicon layer having a large number of hemispherical protrusions, a step of forming an etching mask layer on the top surface of the hemispherical protrusions, Forming the storage electrode by a process including a step of patterning the crystalline silicon layer, a step of anisotropically etching the polycrystalline silicon layer using the etching mask layer as a mask, and a step of removing the etching mask layer. And a manufacturing method characterized by the above. At this time, the etching mask layer may be formed by oxidizing the top surface of the hemispherical projection.

Further, in the semiconductor memory device having a transfer transistor and a storage capacitor, the transfer transistor has a second conductivity type source region and a drain region formed on a first conductivity type semiconductor substrate, and the source region. A first conductor layer adjacent to the region and the drain region and insulated from the channel region between the source region and the drain region via a gate oxide film; and a first insulating layer for insulating the first conductor layer. And a second insulating layer which is in contact with the drain region and extends on the first insulating layer, and a second insulating layer which insulates the second conductive layer, and which is adjacent to the source region. As described above, the field oxide film is formed on the semiconductor substrate, and the storage capacitor is in contact with the source region and has a small amount of the first conductor layer. And a first electrode of a conductor layer formed so as to overlap at least a part of the field oxide film, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer. Forming a polycrystalline silicon layer having a plurality of hemispherical protrusions, the polycrystalline silicon layer being in contact with the source region and extending over the second insulating layer.
A second step of forming an etching mask layer on the top surface of the hemispherical protrusion, a third step of patterning the polycrystalline silicon layer, and the anisotropic etching of the polycrystalline silicon layer using the etching mask layer as a mask. There is provided a manufacturing method characterized in that a first electrode of a storage capacitor is formed by sequentially advancing a fourth step of erosion etching and a fifth step of removing the etching mask layer.

Alternatively, in a method of manufacturing a storage electrode of a storage capacitor on a planarized insulating layer formed on a semiconductor substrate having an active region, a plurality of hemispherical protrusions contacting the active region and having a predetermined interval are provided. Forming a polycrystalline silicon layer having a portion on the insulating layer, forming a SiN layer on the polycrystalline silicon layer, applying SOG on the SiN layer to planarize the SN layer, and
A step of etching OG until a part of the SiN layer formed on the top of the hemispherical protrusion is exposed; removing the SiN layer exposed by this etching to expose the top surface of the hemispherical protrusion; The method comprises the steps of oxidizing the top surface to form an etching mask layer, anisotropically etching the polycrystalline silicon layer using the etching mask layer as a mask, and removing the etching mask layer after the etching. A manufacturing method characterized by the above.

Furthermore, in the method of manufacturing the storage electrode of the storage capacitor on the insulating layer formed on the semiconductor substrate having the active region, the first interlayer insulating film planarized on the semiconductor substrate having the active region, First insulating film and second insulating film are sequentially formed first
And a second step of forming a first contact hole in the first interlayer insulating film, the first insulating film, and the second insulating film to expose the active region, and contacting the active region through the first contact hole. Thus, a third step of forming a polycrystalline silicon layer having a large number of hemispherical protrusions on the second insulating film, and a fourth step of etching the polycrystalline silicon layer to form a predetermined pattern. Forming an insulating film covering the polycrystalline silicon layer on the entire surface of the semiconductor substrate and etching back the insulating film; and etching masks between the hemispherical projections of the polycrystalline silicon layer and the pattern side surface by the remaining insulating film. Forming a pattern to expose the top of the hemispherical protrusion 5th
There is provided a manufacturing method characterized by including a step and a sixth step of etching the polycrystalline silicon layer using the etching mask pattern as a mask.

Further, in the method of manufacturing the storage electrode of the storage capacitor on the insulating layer formed on the semiconductor substrate having the active region, the first interlayer insulating film planarized on the semiconductor substrate having the active region, First insulating film and second insulating film are sequentially formed first
And a second step of forming a first contact hole in the first interlayer insulating film, the first insulating film, and the second insulating film to expose the active region, and contacting the active region through the first contact hole. Thus, a third step of forming a polycrystalline silicon layer having a large number of hemispherical protrusions on the second insulating film, and a fourth step of forming a third insulating film on the polycrystalline silicon layer, A fifth step of etching the polycrystalline silicon layer and the third insulating film to form a pattern, and a patterning of the third insulating film left by etching a part of the patterned third insulating film A sixth step of forming a first etching mask pattern having a plane area smaller than that of the polycrystalline silicon layer, and a seventh step of etching the polycrystalline silicon layer to a predetermined thickness by using the first etching mask pattern as a mask, The eighth step of depositing the fourth insulating film on the entire surface of the body substrate, and the fourth insulating film left by etching back the entire surface of the fourth insulating film, the top of the hemispherical protrusion of the polycrystalline silicon layer A manufacturing method comprising: a ninth step of forming a second etching mask pattern that exposes the film, and a tenth step of etching the polycrystalline silicon layer using the second etching mask pattern as a mask. To do.

[0018]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated description will be omitted. FIG. 1 is an enlarged plan view of a part of a DRAM memory cell array according to the present invention, and FIG. 2 is a sectional view taken along line 2-2 of FIG. 1, showing a section of a memory cell corresponding to 2 bits. Is shown.

A field oxide film 12 defining a memory cell region is formed on a P-type semiconductor substrate 10.
The semiconductor substrate 10 may be a P-type well region. In the active region 14 on the main surface of the semiconductor substrate 10 surrounded by the field oxide film 12, an N-type source region 16 adjacent to the field oxide film 12,
An N-type drain region 20 separated from the source region 16 via an N-channel region 18, and an N-channel region 18
A transfer transistor including the gate electrode 24 on the upper gate oxide film 22 and adjacent to the source region 16 and the drain region 20 is formed. The gate electrode 24 of this transfer transistor is connected to the word line 26.

A word line 28 connected to the gate electrode of the transfer transistor formed in the adjacent active region is formed on the field oxide film 12. The word line 28 and the gate electrode 24 are insulated by the insulating layer 30.

The insulating layer 30 has an opening 32 for exposing a part of the source region 16. The storage electrode 36 (first electrode) contacts the source region 16 at the source contact region 34 through the opening 32 and extends above the adjacent gate electrode 24 and word line 28 to form the storage capacitor region 38. Shaping. The upper portion of the storage electrode 36 has a large number of micro-cylinders (and a large number of micro-trenches), which are characteristic portions of the present invention for increasing the surface area of the storage electrode of the storage capacitor, as described later.

A dielectric layer 40 is formed on the surface of the storage electrode 36, and the plate electrode 4 is further formed thereon.
2 (second electrode) is formed. Therefore, the storage capacitor 44 in the figure is composed of the storage electrode 36, the dielectric layer 40, and the plate electrode 42.

A protective film layer 46 is formed on the plate electrode 42 and the exposed insulating layer 30. The protective film layer 46 is provided with an opening 50 for exposing a heavily doped N ⁺ region 48 adjacent to the drain region 20 of the transfer transistor and extending to the main surface of the semiconductor substrate 10. Then, the bit line 52 made of a conductive material contacts the N ⁺ region 48 at the bit line contact region 54 through the opening 50. In addition, the bit line 52 extends in a strip shape on the protective film layer 46 and crosses the word lines 26 and 28. The bit line 52 is coated with a second protective film layer (not shown).

As described above, the DRAM memory cell according to the preferred embodiment of the present invention is composed of one transistor and one capacitor. This capacitor is a storage capacitor region 3 on the semiconductor substrate 10.
8 is a stack capacitor having a storage electrode having a large number of microcylinder (and microtrench) structures within an area (ie, 0.4 × 1.2 μm ² ) occupied by 8. However, the present invention is not limited to such an increase in storage electrode area.

With reference to FIGS. 3 to 11, the above-mentioned DR
The manufacturing process of the AM memory cell will be described in detail. The usage of such a memory cell is a fact known to those having ordinary knowledge in this technical field, and therefore its explanation is omitted.

FIG. 3 shows a sectional view corresponding to FIG. 2 in which a pair of transfer transistors are formed on the semiconductor substrate 10. Although the manufacturing process of this transistor is well known, it will be briefly described for the time being. The semiconductor substrate 10 has a concentration of 1 × 10 ¹⁵ atoms / cm ³ and has a concentration of 4 to 5 × 10 ¹⁶ atoms / cm ² formed on a P-type silicon wafer having a [100] crystal plane.
Shaped well. A field oxide film 12 having a thickness of about 3000Å is formed on a part of the surface of the semiconductor substrate 10 to define the active region 14 shown in FIG. After that, a gate oxide film 22 shown in FIG. 2 having a thickness of about 150 Å is formed on the semiconductor substrate 10 in the active region 14 by a normal dry O ₂ oxidation method, and a high concentration is used to form a gate electrode. A polycrystalline silicon layer doped with phosphorus is formed on the semiconductor substrate 10. After applying polycrystalline silicon, the gate electrode 24,
Word lines 26, 28 are patterned by conventional photolithography. By this patterning, the gate oxide film 22 excluding the portions below the gate electrode 24 and the word lines 26 and 28 is removed until the surface of the semiconductor substrate 10 in the active region 14 is exposed. Then, in order to form the source region 16 and the drain region 20, phosphorus ion implantation is performed with a dose of 1.6 × 10 ¹³ ions / cm ² and an energy of 60 Kev. After the phosphorus ion implantation, the insulating layer 30 of SiO ₂ is formed by LPCVD at a temperature of about 820 ° C. to insulate the gate electrode 24, the word line 26, the word line 28, the source region 16 and the drain region 20. It is deposited to about 2700Å, and as a result, a silicon oxide film layer having good quality and uniformity can be obtained.

As shown in FIG. 4, the insulating layer 30 is formed as described above, and then the opening 32 exposing a part of the surface of the source region 16 is formed by the conventional photolithography method. Is formed. And the opening 32
After removal of the photoresist used to form
A polycrystalline silicon layer 56 having a number of hemispherical projections and a thickness of about 2500Å is formed on the surface of the semiconductor substrate 10 so as to contact the source region 16 at the source contact region 34 through the opening 32. .

A polycrystalline silicon layer having a large number of hemispherical protrusions on the surface thereof is an LPCV using SiH ₄ (20%) diluted with helium at a temperature of 1 atmosphere and 550 ° C.
It can be formed by the D method (LEEE Trans, on E
lectron Devices. Vol. ED-36, No. 2. pp35
1-353, 1983 or SSDM. pp873 to 87
6. 1990). Alternatively, under the temperature condition (600 ° C. or higher) for depositing normal polycrystalline silicon, about 100
It is also possible to deposit polycrystal silicon by a thickness of 0Å and then form polycrystal silicon having a large number of hemispherical projections on the surface of the polycrystal silicon to have a thickness of about 1500Å. . The diameter or height of the hemispherical projections on the surface of the polycrystalline silicon layer 56 thus formed is about 0.07 to 0.15 μm.

After forming the polycrystalline silicon layer 56, arsenic ion implantation for doping the polycrystalline silicon layer 56 is performed with a dose of 3 × 10 ¹⁵ ions / cm ² and 100 Ke.
done with the energy of v. At this time, the polycrystalline silicon layer 56 may be doped with phosphorus, but arsenic doping is preferable in order to form a good micro-trench and micro-cylinder structure on the polycrystalline silicon layer 56 in a step described later. After this, a mask layer 58 of SiO ₂ is deposited on the doped polycrystalline silicon layer 56 by the conventional CVD method to a thickness of 300 Å. In this embodiment, as the mask layer 58, a dielectric substance having a high dielectric constant such as Si ₃ N ₄ or Ta ₂ O ₅ is used. But,
Considering the etching process for forming micro-trench and micro-cylinder described later, polycrystalline silicon /
It is preferable to use a dielectric material having a higher dielectric material selection ratio.

After depositing the mask layer 58, patterning to define the storage capacitor regions 38 is performed by conventional photolithography, which results in a polycrystalline having a number of patterned protrusions as shown in FIG. Silicon layer 56 and patterned SiO ₂ mask layer 58
Are formed.

Here, the etching process for forming the micro-cylinder and the micro-trench, which is a characteristic part of the present invention, will be described in detail with reference to the attached FIGS. 6 to 8 and 9 to 11. 6 to 11 are enlarged views of the portion 100 surrounded by the dotted line in FIG. Moreover, FIGS.
1 shows the arrangement of the protrusions when the distance S between the hemispherical protrusions is at least twice (2X) the thickness X of the mask layer 58,
6 to 8 show the arrangement of the protrusions when the distance S = 0. In effect, the polycrystalline silicon layer 56 has an LPCV of the above conditions in the temperature range in which the polycrystalline silicon layer 56 changes from an amorphous state to a polycrystalline structure.
When deposited by the D method, the distance S between the protrusions is S =
There are mixed states of 0 and S> 2X.
That is, the arrangement of the protrusions shown in FIG. 6 and the arrangement of the protrusions shown in FIG. 9 appear at the same time.

As can be seen by referring to FIG.
The SiO ₂ etchback process for forming the sidewalls used in the DD MOSFET manufacturing process is performed by adjusting the thickness of the mask layer 58.
X (= 300Å) will be the etching completion time
Thus, it is applied to the mask layer 58. At the time of depositing the mask layer 58, a thicker SiO ₂ layer is deposited on the valley portion between the protrusions of the polycrystalline silicon layer 56, and as a result of the above-mentioned etch back, the etching mask layer 62 is formed as shown in FIG. It remains as shown and only the top 66 of the protrusion is exposed. Thereafter, anisotropic etching with a selection ratio of polycrystalline silicon / SiO ₂ of 40 is performed so as to form a groove having a depth of 0.2 μm.

In the present embodiment, such etching is performed by using, for example, a model name "Rainbow 4400" manufactured by LAM Co. under a pressure of 350 mbar and a power of 200.
Watt, HBR (Hydro-bromide): Cl ₂ = 40S
It was carried out using a mixed gas of CCM: 120SCCM.

As a result, as shown in FIG. 8, a groove having a substantially U-shaped cross section having a cylindrical inner wall is formed in the polycrystalline silicon layer 56. Further, a hemispherical convex portion 64 corresponding to the exposed portion 66 is formed on the bottom surface of the groove, which further increases the surface area of the storage electrode 36 (polycrystalline silicon layer 56).

After forming the micro-cylinder as described above, the surface of the storage electrode 36 is subjected to normal CVD.
By the method, a Si ₃ N ₄ layer having a thickness of about 70Å is formed,
Then, the surface of this Si ₃ N ₄ layer is thermally oxidized to about 20Å
By forming the SiO ₂ layer, the dielectric layer of the NO structure (ONO structure if adding an SiO ₂ layer which is naturally oxidized) 4
Cover 0. Then, a plate electrode 42 is formed by forming a doped polycrystalline silicon layer on the dielectric layer 40 by a normal method and patterning it by a normal photo-etching method.

On the other hand, in the case of FIGS. 9 to 11, when the mask layer 58 is etched back, the etching mask layers 62 are formed on the side walls of the protrusions 60 as shown in FIG. Polycrystalline silicon layer 56 between parts 60
Only a portion 68 of the surface and the top 66 of the protrusion are exposed. Then, the submicron etching as described above is performed, and as a result, the storage electrode 36 having a large number of microcylinders 70 is formed as shown in FIG. In this case as well, similar to FIG. 8, a hemispherical convex portion 64 corresponding to the shape of the exposed top portion 66 is formed on the bottom surface of the microcylinder 70. At this time, the portion where the portion 68 of the surface is etched becomes a micro trench, and the bottom surface 80 thereof is etched deeper than the hemispherical convex portion 64. As described above, the micro-cylinder 70 and the micro-trench can be manufactured by a self-alignment etching process without using a photoresist, and thus a complicated manufacturing process is not required.

It should be noted that, in the mixed arrangement of FIGS. 6 and 9, after the above-described anisotropic etching, a pole having a large number of microcylinders and a large number of microtrenches will be provided. Then, the dielectric layer 40 of the NO layer (ONO layer) and the plate electrode 42 are formed on the surface of the storage electrode 36 by the same process as described above. As can be seen from the above, the microcylinder is a cylindrical cavity obtained by digging by exposing the exposed top portion 66 of each protrusion 60, and the microtrench is
As shown in FIG. 10, the polycrystalline silicon layer 56 between the protrusions 60 is formed.
It is a groove-shaped cavity obtained by digging by exposing the exposed portion 68 of the.

Although the manufacturing process of the stack capacitor having the SiO ₂ etching mask layer 62 deposited on the surface of the storage electrode 36 has been described above, the etching mask layer 62 is effective as the dielectric layer of the capacitor. The etching mask layer 62 is preferably removed because it does not play a role. The SiO ₂ etching mask layer 62 may be removed by using a buffered HF solution after the anisotropic etching process described above.

Generally, in anisotropic etching, the edge portion after etching becomes sharp. In addition to the edge portion, a sharp portion may occur around the portion damaged by etching. The presence of such a sharp portion not only impairs the reliability when forming the thin dielectric layer 40 that covers the storage electrode 36, but also causes the breakdown voltage of the storage capacitor to decrease.

The step of rounding such a sharp portion is
After completion of anisotropic etching, before forming the dielectric layer 40 (in the case of a storage capacitor having the etching mask layer 62) or after removing the etching mask layer 62 and before forming the dielectric layer 40 (etching mask layer 62).
In case of no storage capacitor), can be done. That is, HCl: H ₂ O ₂ : H at a temperature of 60 ° C. to 80 ° C.
_The substrate is dipped in a mixed solution of ₂ O = 1: 1: 6 to form a SiO ₂ film of about 10 Å on the surface of the storage electrode 36. Thereafter, the oxide film formed by such a chemical oxidation process is removed with a buffered HF solution to remove the sharp portion.

In the present embodiment, the polycrystalline silicon layer 56 having hemispherical projections is formed to a thickness of 2500Å, and the groove is formed to a depth of 2000Å by etching. It is not limited to these numerical values. For example, the surface area of the storage electrode 36 can be further increased by making the polycrystalline silicon layer 56 a thicker layer and forming the groove deeper by etching depending on the selection ratio of polycrystalline silicon / dielectric material.

FIGS. 3 to 5 of the above embodiment show the formation of the plate electrode 42 as described above. Here, the subsequent steps will be described. That is, after forming the plate electrode 42, a protective film layer 46 (FIG. 2) such as BPSG (Boro phospho-silicate glass) or PSG is coated on the semiconductor substrate 10, and a reflow process for planarization is performed. After that, an opening 50 (FIG. 2) is formed by a usual method, and the opening 50 (FIG. 2) is formed.
To form an N ⁺ region 48, and then form an aluminum bit line 52 (FIG. 2). Further, according to the above-described embodiment, the bit line 52 extends while overlapping the upper portion of the transfer transistor and the upper portion of the storage capacitor 44, and the gate electrode of the transfer transistor is formed of polycrystalline silicon. However, the present invention is not limited to this. Alternatively, the polycrystalline silicon forming the first electrode may be recrystallized silicon. Furthermore, the present invention is not limited to the stack capacitor as in the above embodiment, but can be applied to the case where a groove is formed in the semiconductor substrate and the storage capacitor is formed in this groove. Alternatively, when a high capacitance capacitor is required in a limited area on the insulating substrate, a storage electrode having a large number of microcylinders and microtrenchs according to the present invention is formed on the insulating substrate, and a dielectric layer is formed thereon. After that, a necessary capacitor can be manufactured by forming a plate electrode, which is the second electrode, thereon.

The structure of the storage electrode according to the present invention and the method of manufacturing the same have been described above by way of one example. However, in addition to the structure and the method of manufacturing the storage electrode, the idea of the present invention is also provided. Other embodiments are possible within the scope of. These and other possible embodiments are described below.

Embodiment 1 (FIGS. 12 to 23): FIG. 12 is an enlarged plan view of a portion of a DRAM memory cell array according to another embodiment of the present invention, and FIG. 13 is taken along line 3-3 of FIG. FIG. 6 is a cross-sectional view of a memory cell corresponding to 2 bits along the line. The same components as those in the above-described embodiment (FIGS. 1 to 11) are designated by the same reference numerals, and duplicated description will be omitted.

As can be seen from FIGS. 12 and 13, a field oxide film 12 is formed on the P-type semiconductor substrate 10 to limit the area of the memory cell. The P-type semiconductor substrate 10 may be a P-type well.

In the active region 14 defined by the field oxide film 12, a source region 16 adjacent to the field oxide film 12, a drain region 20 separated from the source region 16 through an N-type channel region 18, and an N region.
-Gate oxide film 22 formed on the channel region 18
And the source region 16 formed on the gate oxide film 22.
And a gate electrode 24 adjacent to the drain region 20, a transfer transistor of the memory cell is formed.

The gate electrode 24 is connected to the word line 26, and the word line 28 is formed on the field oxide film 12 so as to be connected to the gate electrode of the transfer transistor formed in the adjacent active region. The gate electrode 24 and the word line 28 are
It is insulated by the insulating layer 30.

The first insulating layer 30 has an opening 135, and the drain region 20 of the transfer transistor and the bit line 150 are in contact with each other through the opening 135. Second covering the bit line 150
The insulating layer 190 and the first insulating layer 30 include the source region 16
Has an opening 125 for exposing a part of it. The surface of the second insulating layer 190 is flattened.

The storage electrode 200 is opened through the opening 125.
Are in contact with the source region 16 and extend above the adjacent gate electrode 24 and word line 28 on the second insulating layer 190 to define a region of the storage capacitor. The storage electrode 200 has many micro cylinders (and many micro trenches). The structures of the micro cylinder and the micro trench will be described later. The dielectric layer 40 is formed on the surface of the storage electrode 200, and the plate electrode 400 is formed thereon.

As described above, in the structure of the DRAM memory cell shown in FIGS. 12 and 13, the DASH (Diagonal Ac) in which the bit line is formed under the storage capacitor.
tiveStacked capacitor cell with a Highly-packed st
It can be seen that it is applied to the roage node) structure.
This DASH structure is described in IEDM 1988, p.
p. Details on 596-599. DRAM of DASH structure
In the memory cell, the horizontal expansion of the storage capacitor can be designed without being affected by the design rule of the bit line. Therefore, the process is easier than forming the storage capacitor under the normal bit line, and the storage capacitor can be formed easily. The advantage is that the capacity can be increased easily. Therefore, it can be seen that the storage electrode 200 that limits the area of the storage capacitor can be expanded within a range that does not contact the storage electrode of another storage capacitor belonging to the adjacent memory cell.

Now, the manufacturing process of the memory cell shown in FIG. 13 will be described in detail with reference to FIGS. FIG. 14 shows up to the step of forming the bit line 150 after forming the pair of transfer transistors on the substrate. The process up to the formation of the bit line 150 is the same as that described with reference to FIG. First
Since the bit line 150 is formed on the insulating layer 30, the first insulating layer 3 may be formed using a reflow process such as BPSG.
The surface of 0 should be flattened. Then, in order to connect the drain region 20 of the transfer transistor and the bit line 150, a portion of the first insulating layer 30 on the drain region 20 is exposed to expose a portion of the surface of the drain region 20 by a normal photo-etching method. Until it is removed to form the opening 135. Then, an aluminum bit line 150 is formed so as to pass through the opening 135.

Next, FIG. 15 will be described. After forming the bit line 150, a second insulating layer 190 such as BPSG or PSG is applied on the substrate 10 to a thickness of about 5000Å, and then reflow is performed to planarize the surface. The second insulating layer 190 is a normal silicon oxide film, or
You may use the composite layer which consists of a silicon oxide film and a silicon nitride film. However, in either case, the surface flattening step is performed after the application of the second insulating layer. The planarization is performed by applying a silicon oxide film layer on a substrate, further applying a resist material thereon, and then performing an etching process in which the etching ratio of the resist material and the silicon oxide film layer is adjusted. Any method may be used.

Next, FIG. 16 will be described. After the formation and planarization of the second insulating layer 190 are completed, the opening 125 exposing the partial surface of the source region 16 is formed in the second insulating layer 190 and the first insulating layer 30 by using a normal photolithography method. To form through. Then, after removing the photoresist used for forming the opening 125, the thickness 25 having a large number of hemispherical protrusions on the surface is formed as described with reference to FIG.
A 00Å polycrystalline silicon layer 56 is formed on the second insulating layer 190 so as to contact a part of the surface of the source region 16 through the opening 125.

After forming the polycrystalline silicon layer 56, arsenic ion implantation is performed in the same manner as in FIG. 4 to dope the polycrystalline silicon layer 56. Then, SiO is formed on the doped polycrystalline silicon layer 56.
_{The second} mask layer 250 is applied to
Deposit to a thickness of about 500Å. This mask layer 250
As the dielectric material, a dielectric material having a high dielectric constant such as Si ₃ N ₄ or Ta ₂ O ₅ can be used. It is better to use a dielectric material with a crystalline silicon / dielectric material selection ratio. Then, after depositing the mask layer 250, patterning for limiting the area of the storage capacitor is performed by a normal photo-etching method.

Hereinafter, FIGS. 18 to 20 and 21 to 23 will be described.
A microcylinder, which is a characteristic part of the present invention,
The process of forming the micro trench will be described in detail.
The drawing is an enlarged view of a portion 500 surrounded by a dotted line in FIG. 21 to 23, when the distance between the HSGs (hemispherical protrusions) is twice or more the thickness of the mask layer 250 of silicon oxide, the distance between the HSGs is 0 in FIGS. 18 to 20. Indicate the case.

As can be seen from FIG. 18, a normal LDD
The etch back process of the silicon oxide film for forming the side wall used in the MOSFET manufacturing process is performed with the thickness of the silicon oxide film 250 of 300 to 500Å as an end point of the etching completion. this is,
It is similar to that shown in FIG. Then, as in the case of FIG. 7, since a thicker silicon oxide film layer is deposited in the valley portion 223 between the HSGs 221 of the polycrystalline silicon layer 56 when the silicon oxide film 250 is deposited, the etching back is performed as a result of the etching back. The mask layer 251 remains and HS
Only the top 222 of G221 is exposed.

Then, in FIG. 19, until the polycrystalline silicon layer 56 having a thickness of 2500Å is completely etched to expose a part of the surface of the second insulating layer 190 except the lower portion of the etching mask layer 251, the polycrystalline silicon layer 56 is exposed. An anisotropic etching is performed with a selectivity ratio of / silicon oxide of 40. Such etching is performed by the model name "Rainbow 440" of LAM.
200 "under atmospheric pressure of 350 mbar using" 0 "
HBR (Hydro-bromide): Cl ₂ = 4 with att power
It can be performed using a mixed gas of 0 SCCM: 120 SCCM. As a result, the formed microcylinder 230 has a shape like a through hole penetrating the polycrystalline silicon layer 56. Here, in the above-described etching process for forming the micro-cylinder in FIG. 8, the groove depth is 0.2 μm.
Therefore, it can be seen that this is different from the present embodiment.

After the through-hole-shaped microcylinder 230 is formed in this way, at a temperature of 600 ° C. or higher, which is a temperature condition for forming normal polycrystalline silicon,
LPH with a deposition rate of 20-25Å / min for SiH ₄ gas for decomposition
Thin polysilicon layer 24 doped by the method
0 indicates the substrate 10 including the inner and outer surfaces of the microcylinder 230
Deposited on the entire surface of. The thickness of the polycrystalline silicon layer 240 is at least the diameter (0.07 to 0.1) of the HSG 221.
If it is thinner than 1/2 of 5 μm), it does not affect the surface area of the storage capacitor, so it is preferable to set it to about 300 to 700Å. In addition, since the polycrystalline silicon layer 240 is formed on the entire surface of the substrate 10, a patterning process for limiting the area of the storage capacitor can be performed using a normal photo-etching method, thereby completing the pattern of the storage electrode 200. It As a result, it can be seen that the storage electrode 200 is composed of the polycrystalline silicon layer 56 and the thin polycrystalline silicon layer 240, and has a structure having a large number of microcylinders 230.

Next, referring to FIG. 20, the storage electrode 200 is shown.
Is completed, a Si ₃ N ₄ layer having a thickness of about 70Å is formed on the surface of the polycrystalline silicon layer 240 (or the surface of the storage electrode 200) by a normal CVD method, and this Si ₃ N ₄ layer is formed. A dielectric layer 40 of a NO layer (which becomes an ONO layer when the naturally oxidized SiO ₂ layer is added) is formed by thermal oxidation to form a thin SiO ₂ layer of about 20 Å. Then, a doped polycrystalline silicon plate electrode 400 is formed on the dielectric layer 40 to complete the storage capacitor shown in FIG.

On the other hand, in the case of FIGS. 21 to 23, the mask layer 2
When 50 is etched back, an etching mask layer 251 as shown in FIG. 21 is formed on the sidewall 225 of each HSG 221, and only a portion 226 of the surface of the polycrystalline silicon layer 56 between the HSGs 221 and the top 222 of the HSG 221 are exposed. Thereafter, similarly to the above-described FIG. 19, etching is performed until the polycrystalline silicon layer 56 is penetrated and a part of the surface of the second insulator layer 190 is exposed, so that the thin polycrystalline silicon layer 240 is formed on the entire surface of the substrate 10. After the deposition, the storage electrode 200 is patterned to form the storage electrode 200 having the micro-cylinder and the micro-trench having the structure shown in FIG. 22, and the dielectric layer 40 and the plate electrode 400 are formed. It

At this time, it will be easily understood by those having ordinary knowledge in this field that the storage capacitor can be formed by the same method as described above even when the HSG intervals are not constant.

In this embodiment, the etching mask layer 2 is formed by increasing the selection ratio of polycrystalline silicon / silicon oxide.
Since the polycrystalline silicon layer 56 not covered by 51 is completely removed, the polycrystalline silicon layer 240 for connecting the microcylinder and the microtrench and forming the storage electrode 200 is formed. There is no need to adjust the etching depth for forming the trench.

The above description relates to the case where the storage electrode contains the silicon oxide used as the etching mask layer. However, since this etching mask layer (251) does not play an effective role as the dielectric layer of the capacitor and does not contribute to the increase of the surface area of the capacitor, the buffer HF (B
uffered HF) solution.

In this embodiment, the DASH structure memory cell in which the bit line extends below the storage capacitor has been described, but it should be understood that the present invention is not limited to this. . That is, this embodiment can be applied to the structure shown in FIG. However, in such a case, it is necessary to flatten the surface of the first insulating layer thereunder before depositing the polycrystalline silicon layer (56) to be the storage electrode.

Embodiment 2 (FIGS. 24 to 36): As a manufacturing process for forming the structure of FIG. 13, the description has been given with reference to FIGS. 14 to 23 as an example, but it can be formed by other methods. This will be described with reference to FIGS. 24 to 27 and 28 to 36.

First, in FIG. 24, a polycrystalline silicon layer 56 having a thickness of 2500 .ANG.
25 is formed on the second insulating layer 190 so as to be in contact with a part of the surface of the source region 16 via the arsenic, and arsenic is ion-implanted. Then, as shown in FIG. Layer 330 is deposited on polycrystalline silicon layer 56 by a conventional LPCVD method, and SiN layer 330 is deposited.
SOG (Spin On Glass) 340 with a thickness of about 2000Å on top
Is applied. The SOG layer 340 is larger than the height of HSG and needs to be formed so that the surface of the polycrystalline silicon layer 56 in which HSG is formed is completely flat.

FIG. 28 shows an enlarged view of a portion surrounded by a dotted line in FIG. Then, in FIG. 29, after the SOG 340 is applied and planarized, the SOG 340 is etched back (dry etched) to form the SiN formed on the top of the HSG 221.
A portion 331 of layer 330 is exposed. This SiN layer 3
The degree of exposure of 30 can be appropriately adjusted by the etching amount, etching time, and the like. Next, in FIG. 30, exposed SiN
A portion 331 of the layer is etched away. This is L
Dry etching using AM Inc. model name of the "Rainbow 4400", or can be by wet etching using phosphoric acid (H ₃ PO _4). After that, SOG
The remaining part SOG342 of 340 is BOE (Buffered-
Oxide Etchant) solution is completely removed as shown in FIG. 31 by soaking the substrate for about 1 minute.

In FIG. 32, after removing the remaining SOG 342, the HSG 22 of the exposed polycrystalline silicon layer 56 is removed.
The top of No. 1 is oxidized to form an oxide layer 231 having a thickness of about 100 to 1000 Å. This oxidation process uses dry O ₂ or at a temperature of 60-80 ° C. and HCL:
It can be carried out by immersing the substrate in a mixed solution of H ₂ O ₂ : H ₂ O = 1: 1: 6. At this time, a slight oxide layer 232 is formed on the SiN layer 330.
It can be removed by immersing the substrate in the E solution for a short time (about 10 seconds). The oxide layer 231 is used as an etching mask for forming the micro trench. After such oxidation, as shown in FIG. 33, the SiN layer 330 remaining between the HSGs 221 is removed by the H ₃ PO ₄ solution.

Here, as shown in FIG. 26, after the oxide layer (etching mask layer) 231 is formed, the polycrystalline silicon layer 56 is patterned by a normal photo-etching method for patterning the storage electrode. . In this patterning, since the polycrystalline silicon layer 56 is formed on the bit line 150, it can be seen that the area expansion in the horizontal direction is not affected by the bit line design rule.

Thereafter, anisotropic etching with a selection ratio of polycrystalline silicon / silicon oxide of 40 is performed to a depth of about 0.2 μm using the etching mask layer 231 formed in the steps up to FIG. 33 as a mask. For such etching, a model name "Rainbow 4400" manufactured by LAM is used, and a power of 200 watt is obtained under an atmospheric pressure of 350 mbar.
HRR (Hydro bromide): Cl ₂ = 40 SCC at t
It can be carried out in a mixed gas atmosphere of M: 120 SCCM. As a result, as shown in FIG. 34, micro-trench 224 having a round inclined surface portion corresponding to the surface shape of polycrystalline silicon layer 56 before etching is formed on the bottom surface.
As can be seen from the figure, the boundary portion between the bottom surface and the side surface of the micro trench 224 has a gentle slope due to the presence of HSG before etching. With such a structure, the step coverage of the dielectric material applied in the process described below can be improved as compared with the conventional case.

After forming the micro trench,
The shape of the storage electrode 201 is completed by removing the etching mask layer 231 that does not substantially contribute to the surface area of the capacitor as shown in FIG. As can be seen from the figure, the surface of the storage electrode 201 after the etching mask layer 231 is removed has no sharp portion,
The whole is rounded. This again provides a good dielectric coating and prevents the storage capacitor's breakdown voltage from being unnecessarily low.

[0072] Thereafter, the thickness of Si ₃ N ₄ layer about 70Å was formed by a conventional CVD method on the surface of the storage electrode 201, about the surface of the Si ₃ N ₄ layer by thermally oxidizing 20
N composed by forming thin Å SiO ₂
A dielectric layer 40 of an O layer (which becomes an ONO layer when a naturally oxidized SiO ₂ layer is added) is applied. And in FIG.
Then, a doped polycrystalline silicon plate electrode 400 is formed on the dielectric layer 40 to complete a storage capacitor. After that, HPSG (boro-phosphosiligat
e glass) or PSG is applied to the entire surface of the substrate 10, and a reflow process for flattening is performed. as a result,
The structure of the DRAM cell as shown in FIG. 27 is completed.

In the manufacturing method shown in FIGS. 24 to 36, the thickness of the polycrystalline silicon layer 220 serving as the storage electrode is 2500 Å and the depth of the trench is 2000 Å. It is not limited. For example, the surface area of the storage electrode 201 can be further increased by making the polycrystalline silicon layer 56 thicker and etching the trench deeper by the selection ratio of polycrystalline silicon / silicon oxide.

On the other hand, although not shown, it can be easily understood by those having ordinary knowledge in this field that the embodiments of FIGS. 24 to 36 can be applied even when the distance between HSGs is 0. Ah

Embodiment 3 (FIGS. 37 to 51): As a method of manufacturing a storage capacitor according to the present invention, another embodiment different from the above will be described with reference to FIGS. 37 to 51. First, in FIG. 37, the gate electrode 24 and the word line 28 are formed on the first conductivity type semiconductor substrate 10 in the same manner as in FIG. 3, and then the first interlayer insulating film 60 is formed on the entire surface of the substrate 10.
0, for example, a BPSG or oxide type film is deposited and planarized, and a first insulating film 610 is formed on the first interlayer insulating film 600, for example, a nitride film having a thickness of about 500 to 1000Å, and a second insulating film. Insulating film 620, for example 1000-2
An oxide film with a thickness of about 000Å is sequentially deposited. The nitride film, which is the first insulating film 610, is used as an etch stop film in a subsequent process.

FIG. 38 shows the first contact hole CH1,
And a step of forming the first conductor layer (polycrystalline silicon layer) 56 is illustrated. First, a photoresist is applied on the second insulating film 620, and a desired photoresist pattern is obtained through steps such as mask exposure and development. Then, the second insulating film 620, the first insulating film 610, and the first interlayer insulating film 600 are etched using this photoresist pattern to form a storage electrode used as the first electrode of the capacitor. A first contact hole CH1 for connecting to the source region 16 of the transistor is formed. Then, after removing the photoresist pattern for forming the first contact hole CH1, a polycrystalline silicon layer 56 having HSG doped with impurities and having a thickness of about 2000 to 6000Å is deposited on the entire surface of the substrate 10. To do. Here, as shown in FIG. 38, the surface of the polycrystalline silicon layer 56 shows a state where the protrusions are in contact with each other, that is, the above-described distance S is 0. Similar to the case of the example, it is applicable even when the protrusions are separated from each other by a predetermined distance.

FIG. 39 shows a step of forming the pattern of the polycrystalline silicon layer 56 and the third insulating film 630. First, a photoresist is applied on the polycrystalline silicon layer 56,
A desired photoresist pattern is formed through processes such as mask exposure and development, and the polycrystalline silicon layer 56 is etched using this photoresist pattern to form a polycrystalline silicon layer pattern 56 'as illustrated. To do. Then, the photoresist pattern is removed, and a third insulating film 630, for example, an HTO (High Temperature Oxide) film having a thickness of about 300 to 1000 Å is deposited on the entire surface of the substrate 10.

FIG. 40 illustrates an etching process of the third insulating film 630. After the process of FIG. 39, the substrate 10 is exposed until the top portion of the protrusion of the polycrystalline silicon layer pattern 56 'is exposed.
By etching back the entire surface, the third insulating film is left between the protrusions of the polycrystalline silicon layer pattern 56 '(630'). At this time, the third insulating film on the side wall of the polycrystalline silicon layer pattern 56 'also remains (63).
0 ').

FIG. 41 illustrates a process of forming a storage electrode. The remaining third insulating film 630 'is used as an etching mask to form a polycrystalline silicon layer pattern 5 as shown in FIG.
The storage electrode 202 is formed by etching 6 '. That is, the polycrystalline silicon layer is not etched in the portion where the third insulating film 630 'used as the etching mask remains, and
A microcylinder (or a microtrench) is formed on the exposed portion of the polycrystalline silicon layer without the insulating film 630 ', and the storage electrode 202 is completed. Also,
The third insulating layer 630 'remaining on the sidewalls of the polycrystalline silicon layer pattern 56' causes the polycrystalline silicon layer pattern 56 'to be removed during an etching process for forming a storage electrode.
The part of the side wall of the is slope-etched with some slope. At this time, etching process of the polysilicon layer pattern 56 ', the third insulating film which is used as an etching mask (for example, oxide film) etch selectivity is greater bromo hydrogen with (HBr) and chlorine (Cl ₂₎ It is carried out using a mixed gas of.

FIG. 42 shows a process of forming a storage capacitor. After the process of FIG. 41, first, the third insulating film 630 'used as an etching mask is subjected to BOE (Buffe).
redOxide Etchant) solution or diluted hydrogen fluoride (H
F) The dielectric is removed by wet etching using a solution and then covered with the entire surface of the exposed storage electrode 202, for example, an ONO structure or NO structure dielectric having an oxide film-nitride film-oxide film structure. Deposit layer 40. And a second conductor layer so as to cover the dielectric layer 40,
For example, the plate electrode 400 is formed by depositing polycrystalline silicon doped with impurities and then patterning it. In this way, the storage electrode 20
2. A capacitor including the dielectric layer 40 and the plate electrode 400 is completed. Then, the drain region 20 is exposed to form a bit line (not shown). The bit line may be formed before forming the conductor layer (polycrystalline silicon layer) for forming the storage electrode.

43 to 50 show an application example of the steps shown in FIGS. 37 to 42. The process of FIG. 43 is the same as the process of FIG. Then, in FIG. 44, the first contact hole CH1 is formed similarly to FIG. 38, and then the polycrystalline silicon layer 56 and the third insulating film 640 are sequentially formed. Then, in FIG. 45, a photoresist is applied on the third insulating film 640, and a desired photoresist pattern 700 is formed through processes such as mask exposure and development. Then, the third insulating film 640 and the polycrystalline silicon layer 56 are sequentially etched using the photoresist pattern 700, so that the polycrystalline silicon layer pattern 56a as illustrated is formed.
To form At this time, the third insulating film 640 is etched along the polycrystalline silicon layer pattern 56a by wet etching using BOE or diluted hydrogen fluoride,
Third insulating film pattern 640a in which the portion indicated by arrow A is etched
To form The degree of etching for forming the third insulating film pattern 640a is about 500 to 1000Å.

Here, the portion indicated by the arrow A is shown in FIG.
As can be seen from the plan view of FIG. 3, the polycrystalline silicon layer pattern 56a has the same size as the photoresist pattern 700, while the third insulating film pattern 640 has the same size.
a has a constant width from the peripheral edge of the polycrystalline silicon layer pattern 56a.

In FIG. 46, after removing the photoresist pattern 700 of FIG. 45, the third insulating film pattern 6 is removed.
Polysilicon layer pattern 56a using 40a as a mask
Is etched about 500Å to form a stepped surface (arrow B) along the upper peripheral edge of the polycrystalline silicon layer pattern 56a as shown in the figure.

Then, in FIG. 47, the third insulating film pattern 640a is removed, and 500 to 1 are formed on the entire surface of the substrate 10.
Fourth insulating film 650 which is an HTO film having a thickness of about 000Å
Is deposited. The step of removing the third insulating film pattern 640a before depositing the fourth insulating film 650 may be omitted.

Then, in FIG. 48, a fourth insulating film 65 is formed.
The polycrystalline silicon layer pattern 5 is formed by performing an etching process on the entire surface of the substrate 10 on which 0 is formed.
The fourth insulating film pattern 650a remains only between the protrusions of 6a and the side wall of the polycrystalline silicon layer pattern 56a. At this time, the fourth insulating film 650 is formed also on the step surface portion of the upper peripheral edge of the polycrystalline silicon layer pattern 56a formed in the process of FIG.
It is to be noted that the remaining space is left, and this serves as the spacer 651. This spacer 651 is used to form a cylinder along the side wall of the storage electrode that will be formed in a subsequent step.

Thereafter, referring to FIG. 49, the fourth insulating film pattern 6 is formed.
A micro cylinder (and a micro trench) is formed by etching the polycrystalline silicon layer pattern 56a by about 4000 Å using 50a and the spacer 651 as an etching mask.
To complete the shape of the storage electrode 204 having.

Thereafter, referring to FIG. 50, the fourth insulating film pattern 6 is formed.
After removing the spacer 50a and the spacer 651, the dielectric layer 4
The storage capacitor is completed by applying 0 and depositing impurity-doped polycrystalline silicon to form the plate electrode 400.

Although the embodiments of the structure of the storage capacitor and the manufacturing method thereof according to the present invention have been described above, it is common knowledge in the technical field of the present invention that the above embodiments can be applied in various combinations. Then it will be easy to understand. For example, the present invention can be applied to a case where a groove is formed in a semiconductor substrate and a stack capacitor is formed in this groove. When a capacitor having a high capacitance is required in a limited area on the insulating substrate, a storage electrode having a large number of micro cylinders and micro trenches is formed on the insulating substrate according to the present invention, and a dielectric material is formed on the storage electrode. An application example in which a necessary capacitor is manufactured by forming a layer and then forming a plate electrode to be the second electrode on the layer is also considered.

[0089]

As described above, according to the present invention, it is possible to provide a storage electrode having a further increased surface area within a restricted region, so that it is possible to obtain a capacitor having a higher capacity, and the uniformity is good. High reliability can be obtained because various micro cylinders and micro trenches can be formed. Moreover, such an excellent capacitor can be provided by a simpler manufacturing process. As a result, it can greatly contribute to high integration and large capacity of future semiconductor memory devices.

[Brief description of the drawings]

FIG. 1 is a partial plan view of a DRAM memory cell according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line 2-2 in FIG. 1;

3 is a cross-sectional view corresponding to FIG. 2 illustrating an embodiment of a manufacturing process of a capacitor having a storage electrode having the structure shown in FIG.

FIG. 4 is a cross-sectional view corresponding to FIG. 2 illustrating a step following FIG. 3;

FIG. 5 is a cross-sectional view corresponding to FIG. 2 illustrating a step following FIG. 3;

FIG. 6 is a partially enlarged cross-sectional view illustrating details of a process for forming a microcylinder (microtrench) of the storage electrode having the structure shown in FIG.

7 is a cross-sectional view corresponding to FIG. 6 illustrating a step following FIG. 6;

8 is a cross-sectional view corresponding to FIG. 6 illustrating a step following FIG.

9 is a partially enlarged sectional view illustrating details of a process for forming a microcylinder (microtrench) of the storage electrode having the structure shown in FIG.

10 is a cross-sectional view corresponding to FIG. 9 illustrating a step following FIG. 9;

11 is a cross-sectional view corresponding to FIG. 9 illustrating a step following FIG.

FIG. 12 is a partial plan view of a DRAM memory cell according to another embodiment of the present invention.

13 is a sectional view taken along line 3-3 of FIG.

14 is a cross-sectional view corresponding to FIG. 13, illustrating an embodiment of a manufacturing process of a capacitor having a storage electrode having the structure shown in FIG.

FIG. 15 is a cross-sectional view corresponding to FIG. 13 illustrating a step following FIG. 14;

FIG. 16 is a cross-sectional view corresponding to FIG. 13 illustrating a step following the step of FIG. 15;

FIG. 17 is a cross-sectional view corresponding to FIG. 13 illustrating a step following FIG. 16;

FIG. 18 is a partially enlarged cross-sectional view illustrating the details of the process for forming the micro cylinder (micro trench) of the storage electrode having the structure shown in FIG.

FIG. 19 is a cross-sectional view corresponding to FIG. 18, illustrating a step following FIG. 18;

20 is a cross-sectional view corresponding to FIG. 18, illustrating a step following FIG. 19;

FIG. 21 is a partially enlarged cross-sectional view illustrating details of a process for forming a microcylinder (microtrench) of the storage electrode having the structure shown in FIG.

22 is a cross-sectional view corresponding to FIG. 21 illustrating a step following FIG. 21.

23 is a cross-sectional view corresponding to FIG. 21, illustrating a step following FIG. 22.

24 is a cross-sectional view corresponding to FIG. 13 for explaining another embodiment of the manufacturing process of the capacitor having the storage electrode having the structure shown in FIG.

25 is a cross-sectional view corresponding to FIG. 13 illustrating a step following FIG. 24.

FIG. 26 is a cross-sectional view corresponding to FIG. 13 illustrating a step following FIG. 25.

27 is a cross-sectional view corresponding to FIG. 13 illustrating the step following FIG. 26.

28 is a partially enlarged cross-sectional view illustrating details of a process for forming a microtrench of the storage electrode having the structure shown in FIG.

29 is a cross-sectional view corresponding to FIG. 28 illustrating a step following FIG. 28.

30 is a cross-sectional view corresponding to FIG. 28 illustrating a step following FIG. 29.

31 is a cross-sectional view corresponding to FIG. 28 illustrating the step following FIG. 30.

32 is a cross-sectional view corresponding to FIG. 28 illustrating a step following FIG. 31.

FIG. 33 is a cross-sectional view corresponding to FIG. 28 illustrating a step following the step of FIG. 32.

34 is a cross-sectional view corresponding to FIG. 28 illustrating a step following the step of FIG. 33.

FIG. 35 is a cross-sectional view corresponding to FIG. 28, illustrating a step following FIG. 34.

FIG. 36 is a cross-sectional view corresponding to FIG. 28 illustrating a step following FIG. 35.

FIG. 37 is a partial cross-sectional view of a DRAM memory cell illustrating a manufacturing process of a capacitor according to still another embodiment of the present invention.

38 is a cross-sectional view corresponding to FIG. 37 illustrating a step following FIG. 37.

39 is a cross-sectional view corresponding to FIG. 37 illustrating a step following FIG. 38.

FIG. 40 is a cross-sectional view corresponding to FIG. 37 illustrating a step following FIG. 39.

41 is a cross-sectional view corresponding to FIG. 37 illustrating a step following FIG. 40.

42 is a cross-sectional view corresponding to FIG. 37 illustrating a step following FIG. 41.

FIG. 43 is a partial cross-sectional view of a DRAM memory cell illustrating a manufacturing process of a capacitor according to still another embodiment of the present invention.

44 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 43.

45 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 44.

FIG. 46 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 45.

FIG. 47 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 46.

48 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 47.

FIG. 49 is a cross-sectional view corresponding to FIG. 43, illustrating a step following FIG. 48.

50 is a cross-sectional view corresponding to FIG. 43 illustrating a step following FIG. 49.

51 is a plan view illustrating a pattern formation state in FIG. 45. FIG.

[Explanation of symbols]

 16 Source Region 20 Drain Region 24 Gate Electrode 36 Storage Electrode (First Electrode) 40 Dielectric Layer 42 Plate Electrode (Second Electrode)

Claims (21)

(57) [Claims] 1. A memory cell of a semiconductor memory device comprising a transistor transistor and a storage capacitor, wherein the transfer transistor comprises a source region and a drain of a second conductivity type formed on a semiconductor substrate of a first conductivity type. A region and adjacent to the source region and the drain region,
It is composed of a first conductor layer insulated from the channel region between the source region and the drain region via a gate insulating film, and a first insulating layer insulating the first conductor layer, and adjacent to the source region. A field oxide film is formed on the semiconductor substrate, and the storage capacitor is formed to contact the source region and overlap at least a portion of the first conductor layer and at least a portion of the field oxide film. A first electrode of the storage capacitor, a dielectric layer covering the first electrode, and a second electrode covering the dielectric layer. A memory cell, wherein a large number of microcylinders each having a hemispherical convex portion are formed in the memory cell. 2. The memory cell according to claim 1, wherein a large number of micro trenches are formed in a portion other than the micro cylinder in the first electrode of the storage capacitor. 3. A first electrode of a conductor layer extending on an insulating layer, a dielectric layer formed on the first electrode, and a dielectric layer formed on the dielectric layer in a restricted area on the substrate. A capacitor having a second electrode, wherein the first electrode is formed with a large number of microcylinders having a cylindrical shape and a hemispherical convex portion on the bottom surface. 4. The capacitor according to claim 3, wherein a large number of micro trenches are formed in a portion of the first electrode other than the micro cylinder. 5. A memory cell of a semiconductor memory device comprising a transfer transistor and a storage capacitor, wherein the transfer transistor comprises a source region and a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type. A first conductor layer adjacent to the source region and the drain region and insulated from the channel region between the source region and the drain region via a gate insulating film, and a first insulating layer for insulating the first conductor layer A second conductive layer formed on the semiconductor substrate, the field oxide film being formed on the semiconductor substrate so as to be adjacent to the source region, and extending on the first insulating layer. A second insulating layer for insulating the second conductor layer is formed, and the storage capacitor contacts the source region and
A first electrode of a conductor layer formed so as to overlap at least a part of the first conductor layer and at least a part of a field oxide film, a dielectric layer covering the first electrode, and a dielectric layer covering the dielectric layer. A memory cell comprising a second electrode and a plurality of microcylinders having a cylindrical shape and a hemispherical convex portion on a bottom surface thereof are formed on the first electrode of the storage capacitor. 6. The memory cell according to claim 5, wherein a large number of micro trenches are formed in a portion other than the micro cylinder in the first electrode of the storage capacitor. 7. The memory cell according to claim 5, wherein the first conductor layer is a word line and the second conductor layer is a bit line. 8. The memory cell according to claim 5, wherein the surface of the second insulating layer is flattened. 9. A method of forming a storage electrode of a capacitor having a shape having a large number of microcylinders, the method comprising forming a conductor layer having a hemispherical protrusion on the surface as the storage electrode, the hemispherical protrusion A step of forming an etching mask layer on each side surface of the hemispherical projection so as to expose the top part of the film, anisotropic etching is performed using the etching mask layer as a mask, and a bottom part having a shape corresponding to the top shape is formed. A method of forming a storage electrode, comprising the step of forming a microcylinder. 10. The method of forming a storage electrode according to claim 9, further comprising the step of removing sharp corners of the conductor layer after anisotropic etching. 11. A method of forming a storage electrode of a capacitor having a shape having a large number of microcylinders, the method comprising: flattening a surface of an insulating layer formed under the storage electrode; Forming a conductor layer having a protrusion on the insulating layer; exposing the top of the protrusion of the conductor layer to form an etching mask layer on each side surface of the protrusion; and using the etching mask layer as a mask, Performing anisotropic etching until a part of the insulating layer surface is exposed through the conductive layer, and forming a thin second conductive layer that covers the conductive layer surface and the exposed insulating layer surface A method of forming a storage electrode, comprising the steps of: 12. A method of manufacturing a storage capacitor of a semiconductor memory device using a polycrystalline silicon layer having a large number of hemispherical protrusions, comprising the steps of: forming an etching mask layer on the top surface of the hemispherical protrusions; A storage electrode is formed by a process including a step of patterning the crystalline silicon layer, a step of anisotropically etching the polycrystalline silicon layer using the etching mask layer as a mask, and a step of removing the etching mask layer. A method of manufacturing a storage capacitor, comprising: 13. The method of manufacturing a storage capacitor according to claim 12, wherein the etching mask layer is formed by oxidizing the top surface of the hemispherical protrusion. 14. The method of manufacturing a storage capacitor according to claim 12, wherein after the etching mask layer is removed, a dielectric layer is formed on the surface of the storage electrode, and a plate electrode is formed on the surface of the dielectric layer. 15. A semiconductor memory device comprising a transfer transistor and a storage capacitor, the transfer transistor comprising a source region and a drain region of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and the source. A first conductor layer adjacent to the region and the drain region and insulated from the channel region between the source region and the drain region via a gate oxide film; and a first insulating layer for insulating the first conductor layer. And a second insulating layer which is in contact with the drain region and extends on the first insulating layer, and a second insulating layer which insulates the second conductive layer, and which is adjacent to the source region. A field oxide film is formed on the semiconductor substrate, the storage capacitor contacts the source region, and at least the first conductor layer is formed. A first electrode of a conductor layer formed so as to overlap a portion and at least a portion of the field oxide film, a dielectric layer that covers the first electrode, and a second electrode that covers the dielectric layer. In the method of manufacturing a semiconductor memory device, a first step of forming a polycrystalline silicon layer having a plurality of hemispherical protrusions, the polycrystalline silicon layer being in contact with the source region and extending above the second insulating layer; A second step of forming an etching mask layer on the top surface of the protrusion, a third step of patterning the polycrystalline silicon layer, and a fourth step of anisotropically etching the polycrystalline silicon layer using the etching mask layer as a mask. A semiconductor memory characterized in that a first electrode of a storage capacitor is formed by sequentially advancing a step and a fifth step of removing the etching mask layer. A method of manufacturing a device. 16. The etching mask layer is formed by oxidizing the top surface of the hemispherical protrusion.
5. The method for manufacturing a semiconductor memory device according to item 5. 17. A method of manufacturing a storage electrode of a storage capacitor on a flattened insulating layer formed on a semiconductor substrate having an active region, comprising: a plurality of hemispherical protrusions contacting the active region and having a predetermined spacing. Forming a polycrystalline silicon layer having the above on the insulating layer, forming a SiN layer on the polycrystalline silicon layer,
SOG is applied on the SiN layer to planarize the SOG layer.
Is etched until a part of the SiN layer formed on the top of the hemispherical protrusion is exposed, and the SiN layer exposed by this etching is removed to expose the top surface of the hemispherical protrusion. The method comprises the steps of oxidizing the surface to form an etching mask layer, anisotropically etching the polycrystalline silicon layer using the etching mask layer as a mask, and removing the etching mask layer after the etching. A method of manufacturing a storage electrode, comprising: 18. A method of manufacturing a storage electrode of a storage capacitor on an insulating layer formed on a semiconductor substrate having an active region, comprising: a first interlayer insulating film planarized on the semiconductor substrate having an active region; A first step of sequentially forming an insulating film and a second insulating film, and a first step of forming a first contact hole in the first interlayer insulating film, the first insulating film, and the second insulating film to expose the active region. 2 steps, contacting the active area through the first contact hole,
A third step of forming a polycrystalline silicon layer having a large number of hemispherical protrusions on the second insulating film, a fourth step of etching the polycrystalline silicon layer to form a predetermined pattern, and the entire surface of the semiconductor substrate. Then, an insulating film covering the polycrystalline silicon layer is formed, the insulating film is etched back, and an etching mask pattern is formed between the hemispherical projections of the polycrystalline silicon layer and on the pattern side surface by the remaining insulating film. A fifth step of exposing the top of the hemispherical protrusion, and a sixth step of etching the polycrystalline silicon layer using the etching mask pattern as a mask to form a microcylinder having a bottom having a shape corresponding to the top shape. A method of manufacturing a storage electrode, comprising: 19. The method of manufacturing a storage electrode according to claim 18, wherein a nitride is used for the first insulating film. 20. A method of manufacturing a storage electrode of a storage capacitor on an insulating layer formed on a semiconductor substrate having an active region, comprising: a first interlayer insulating film planarized on the semiconductor substrate having an active region; A first step of sequentially forming an insulating film and a second insulating film, and a first step of forming a first contact hole in the first interlayer insulating film, the first insulating film, and the second insulating film to expose the active region. 2 steps, contacting the active area through the first contact hole,
Third step of forming a polycrystalline silicon layer having a large number of hemispherical protrusions on the second insulating film, fourth step of forming a third insulating film on the polycrystalline silicon layer, and these polycrystalline silicon layers And a fifth step of forming a pattern by etching the third insulating film, and a third insulating film left by etching a part of the patterned third insulating film. A sixth step of forming a first etching mask pattern having a small planar area, a seventh step of etching the polycrystalline silicon layer to a predetermined thickness using the first etching mask pattern as a mask, and a fourth step of forming a fourth surface on the entire surface of the semiconductor substrate. An eighth step of depositing an insulating film and a second etching mask for exposing the top of the hemispherical projection of the polycrystalline silicon layer by the remaining fourth insulating film by etching back the entire surface of the fourth insulating film Shape pattern Ninth step and method for producing a storage electrode, characterized in that it comprises a tenth step of etching the polycrystalline silicon layer the second etching mask pattern as a mask, the for. 21. The second etching mask pattern is formed between the hemispherical projections of the polycrystalline silicon layer, the side surface of the polycrystalline silicon layer patterned in the fifth step, and the polycrystalline pattern patterned in the seventh step. The method of manufacturing a storage electrode according to claim 20, wherein the storage electrode is formed on the side surface of the silicon layer.