DD299990A5 - One-transistor memory cell arrangement and method for its production - Google Patents

Abstract

The invention relates to a one-transistor memory cell array and a method for the production thereof, in particular for highly integrated dynamic semiconductor memory. The memory cell arrangement according to the invention is essentially characterized in that the storage electrode consists of conducting fins perpendicular to the substrate surface, arranged on a common conductive bottom plate, such that a storage dielectric covers the storage electrode with the exception of the underside of the bottom plate, that a cell plate encloses the storage electrode in a toothed manner the adjacent lamellae are completely filled and the regions of the bottom plate and the memory cell which are adjacent to the outermost lamella are likewise covered with the cell plate, and the contact points in the cell plate breakthrough are arranged according to design requirements. {Semiconductor memory, highly integrated, dynamic; Storage electrode; Base plate; slats; storage dielectric; Cell plate; Memory cell array; Production method}

Description

For this 4 pages drawings

Field of application of the invention

The invention relates to a single-transistor memory cell assembly and a method for the production thereof, in particular for highly integrated dynamic semiconductor memory.

C harakteristik the known prior art

The basic structure for dynamic one-transistor cell semiconductor memories consists of a MOS selection transistor and a storage capacitor with a storage capacity of 30 to 50fF, which contains the logical information as stored charge. The selection transistor can be controlled via a word line. Its drain region is connected to an electrode of the storage capacitor, while its source region is connected to the outside via a bit line with bit line direction source regions of further memory cells. In dRAM memories up to 1 Mbit become the storage capacitors. usually formed by a highly doped substrate surface portion, an overlying memory dielectric (usually silicon dioxide) and a PolysiliziumzellplaUo as a planar array. In order to increase the integration density, cell concepts are realized with a three-dimensional storage capacitor as a trench capacitor or stacked capacitor (STC) or in mixed variants. Compared to the trench cell concept, the STC cell concept is advantageously characterized by a substantial electrical decoupling of the storage capacity from the active silicon. As a result, the active silicon remains generally undisturbed until the drain contact of a lower storage electrode. As a result, the typical for the Trench cell concepts substrate defects or the removal of these defects usually necessary technological measures and the lateral interaction of adjacent storage capacities on the silicon substrate are avoided in principle, and ensures a natural, without separate measures available, high ALPHA immunity.

In the conventional STC memory cell, the storage capacitor consists of two stacked doped polysilicon layers with a storage dielectric therebetween. The lower polysilicon layer acts as a storage electrode and is connected to the drain region of the Auswahltramistors. The upper polysilicon layer acts as a common cell plate of a memory matrix. The electrode stack overlaps the gate of the selection transistor (see Koyanagi, IEDM Tech Dig 1978, p.348-351).

From EP-PS 0191612 an improved STC variant is known in which the cell plate overlaps the edge of the storage electrode, whereby its side edge is obtained as area contribution for a higher storage capacity. The simultaneous filling of the bit line contact windows with the production of the storage electrode also solves the problem of Bitleitun jsabrisses on the edges of the Bitleitungskontaktfensters.

These advantages can be known (EP-PS 0263941) be increased by increasing the thickness of the storage electrode. Furthermore, a method (EP-PS 0223616) is known in which by deepening of the drain contact fonsters in the silicon substrate into a trench is generated by means of an RIE process, which also contributes to its enlargement of the capacitive surface by its topology after deposition of the storage electrode layer.

An even greater storage capacity can be achieved by combining the relief contributions of a thick storage electrode and a trench in the drain contact window (IEDM Tech Dig 1988, pp. 600-603).

The listed dimensional STC variants produce a topological relief that makes string-free bit line contacting difficult if the bit line passes over the storage capacitor.

To remedy this disadvantage is from IEDM ^ ch. Dig. 1988, pp. 596-599 discloses a solution in which the bit line is under the storage capacity. is carried out. In this DASH-STC concept, bit line fabrication occurs after completion of the select transistor such that the bit line is passed laterally past the later drain contact conductor for the memory electrode. This opens up the possibility in principle of increasing the size of the STC complex vertically without problems in terms of bit line construction and contacting.

Furthermore, EP-PS 0295709 discloses an STC cell concept ("fin type") in which the storage electrode consists of an interconnected multiple polysilicon stack which overlaps the selection transistor. Erna et al., In IEDM Tech. Dig., 1988, pp. 592-595 describe both possibilities of bit line routing below and above a storage capacity of the "fin type".

For memories greater than or equal to 16 MdRAM, the bitline must be located below the STC complex. Such complexly structured storage electrodes are difficult to control in terms of production technology (see IEDM Tech. Dig. 1989, pp. 31-34). Outdome describe Inoue u. a. Thus, with a SSC line concept for 64MdRAM and 256MdRAM, respectively, a solution in which the bit line is located below the STC complex and "fin type" memory electrodes mutually overlap each other into adjacent cell geoie'o.

A disadvantage of the latter two solutions, irrespective of whether the polysilicon fins forming the storage electrode stack overlap only the own cell area or the adjacent cell areas, is that a processing phase occurs during production in which the polysilicon fins arranged one above the other are exposed to a plurality of process steps. These process steps, such as wet etching and cleaning steps, oxidation, insulator and polysilicon CVD depositions, represent significant mechanical, chemical and thermal stresses for these sensitive, self-supporting, storage electrode configurations.

Due to the manufacturing process for producing the Polysiliziumfinnen and the requirement to achieve a large memory-effective structure surface, the fins are preferably very thin (less than 100nm) at the same time large length-to-thickness ratio and only linear with the other fins of the same storage or ., the monocrystalline silicon substrate fused. As a result, the stability of such cantilevered storage electrodes is low and, as a result, the yield in the production of the memory cell is adversely affected.

Another disadvantage is that the lying between the polysilicon fins, long and narrow spaces are parallel to the silicon substrate surface and can be achieved, for example by Naßätz- and cleaning processes only perpendicular thereto, shaft-shaped channels. This results in particular in the surface treatment of the self-supporting Polysiliziumfinnen by Naßätz- and Reinigungsprozessa, but also for the following CVD tleschichtungsprozesse for the memory insulator and the polysilicon cell plate unfavorable transport, removal and exchange conditions for liquid and gaseous media in the micro-areas of the storage electrode configuration , However, these processes must reproducibly ensure the necessary high output quality of the storage electrode surface or the high quality of the usually very thin (less than 10nm silicon dioxide equivalent), dielectric (greater than or equal to 6MV / cm) storage dielectric and the cell plate with high yield.

A further disadvantage is that the arrangement of the storage electrode complex over the bit line, which is at least equal to 64 MdRAM, is achieved by laterally bypassing the bit line at the drain contact window for subsequent connection of the lower storage electrode, an additional r between the bit line and the drain contact window adjustment-related safety distance is to be observed. This results in a not to be exceeded width B min of the memory cell (B min = bit line width + drain contact window width + twice the adjustment-related safety distance) at this point.

Object of the invention

The object of the invention is a one-transistor memory cell arrangement for dynamic semiconductor memories and a method for their production, which substantially improve the quality and stability of the storage electrodes of the STC complex with high reproducibility, increase the yield of the manufacturing process and ensure an increase in the packing density.

Explanation of the essence of the invention

The invention has for its object to provide a one-transistor memory cell array for dynamic semiconductor memory and a method for their preparation, which for liquid and gaseous media in the implementation of Naßätz- and cleaning processes and coating methods, in particular in the formation of the STC complex , to ensure favorable conditions and avoid a adjustment-related safety distance when arranging the STC complex above the bit line.

According to the invention, the object is achieved by a one-transistor memory cell for highly integrated dynamic semiconductor memory, consisting of field isolation regions and active surface regions of a monocrystalline substrate, in which a MOS field effect transistor is integrated with a wordline insulated on all sides and a source and a drain region, and a via the stack disposed stacked capacitor (STC) complex covering the memory cell and having its storage electrode connected to the drain region and having its upper electrode formed as a cell plate of all memory cells of a memory matrix block and a bit line contacted to the source region is thereby solved in that the storage electrode consists of conductive lamellae arranged perpendicular to the substrate surface on a common, conductive bottom plate, each of which is arranged in the memory cell layout

Returning and closed ribbon, the width of which corresponds to the wall thickness of the lamellae, represents that each of the lamellae, beginning with an outermost lamella, is arranged within the storage cell, enclosing a smaller one each, along the Lämellenumfanges the wall-to-wall distance adjacent lamellae is constant and corresponds approximately to the lamella wall thickness, that the inner wall surfaces of the innermost, arranged in the center of the Stapelkondansatorkomplexes lamella touch over the entire surface, that a storage dielectric the storage electrode except the bottom plate underside covered, that a cell plate, the storage electrode is interlocked, the distances between are completely filled in the adjacent l.ame'len and which at the outermost lamella bordering with memory dielectric covered areas of the bottom plate and the spine cell are also covered with the cell plate, and that sufformsbf dmgt necessary en contact points in the customs plate breakthroughs are arranged. In one embodiment of the invention, the bottom plate in the memory cell layout corresponds exactly to the area enclosed by the circumference of the outermost lamella, in a further embodiment the memory cell arrangement is such that the bottom plate consists of several conductive layers, the layer thickness of a bottom conductive bottom plate layer being smaller is equal to the wall thickness of the slats and the bottom plate surface corresponds at least to the area enclosed by the periphery of the outermost slat, that a second conductive layer is arranged on the lowermost conductive bottom plate layer whose layer thickness corresponds to the wall thickness of the outermost slat and deron area of the periphery The surface enclosed by the outermost lamella corresponds exactly to the fact that a third conductive layer is arranged on the second conductive layer, whose layer thickness corresponds to the wall thickness of the next inner lamella and whose area corresponds to that of Perimeter of the next inner lamella enclosed area corresponds exactly and that further conductive layers are arranged analogously to the aforementioned layers.

In one embodiment of the invention, the memory cell array, characterized in that the lamellae regardless of the relief of the bottom plate, with which they are contacted, and regardless of the relief of the arranged below the bottom plate memory cell elements at a uniform height above the level of the substrate surface ondon.

A further embodiment of the memory cell arrangement is characterized in that a bit line is arranged on the isolated stacked capacitor complex, the part of the bit line located in the source contact patch being stamped and planarized with respect to the top side of the stacked capacitor complex, and the drain contacting of the storage electrode being effected by direct contact of the storage electrode bottom plate with the drain biot in a drain contact window of a lower insulator layer, which is arranged on the isolated word lines and over the remaining memory cell areas except for the contact windows of the source and drain areas.

In a further embodiment of the invention, the memory cell arrangement is characterized in that the bit line covered with an upper insulation layer is arranged below the stacked capacitor complex, wherein the bit line is arranged on the lower insulation layer above the word line isolate and the lower insulation layer covers all areas of the memory cell except the one The source and drain contact region covers the bit line in the source contact window contacting the source region and an insulated conductive die contacting the drain region in the drain contact window piercing the lower insulation layer, the bit line and the upper insulation layer and contacting the underside of the bottom plate.

In one embodiment of this arrangement according to the invention, the veitikale surface of the punch is covered by a self-aligning insulating jacket with a constant thickness.

Furthermore, this memory cell arrangement is in an embodiment, characterized in that the bit line is supplemented at a Stempe'durchmesser of approximately the Bitleitungsbreite at the piercing point by a conductive ring which surrounds the isolated stamp with constant thickness self-aligning, wherein the conductive ring in its height at least equal to the thickness of the bit line and is electrically isolated from the drain region, the word line and the bottom plate. According to the invention, the object is further achieved by a method for producing a one-transistor memory cell arrangement, dsm in a monocrystalline substrate η-conducting and p-type regions, Felaisolationsgebiete and subsequently MOS field effect transistors with all sides isolated word lines and source and drain areas, a lowest conductive layer of a storage electrode, which generates the contact of a Stjpelkondensators to the underlying drain region of the memory cell, formed in a memory matrix stacked capacitor complex and contacted with the source region of the memory cell bit line and finally etched at contact points breakthroughs in the cell plate of the stacked capacitor complex, achieved in that after depositing a lowermost conductive layer of the bottom plate, a thick auxiliary insulating layer is deposited in a planarized manner, followed by a steep-edged through-hole in the thick auxiliary insulating layer h is formed down to the lowermost conductive layer, that subsequently, starting and ending with a deposition of a conductive laminar layer in alternating sequence, a conductive laminar layer and then a thin Hilfsisolatiünsschicht are deposited, the double sum of all conductive fin and auxiliary insulation layer thicknesses the shortest distance from each other Wall surfaces of the Stolflankigen breakthrough in the thick auxiliary insulating layer corresponds, and at least after each deposition of a thin auxiliary insulating an anisotropic RIE process is performed, wherein a jf the surface of the thick auxiliary insulating layer and on the bottom surface in the breakthrough at least the last deposited layer is etched while the last deposited and all previously deposited layers remain on the vertical walls of the opening and form a lamellar structure that after the deposition of the last conductive lamellae Not by means of an RIE process, the surface of the thick insulating layer from the last Lomellenschicht and remaining lamellar layers is etched, whereby the upper ends of the etched lamellae are separated from each other, then subsequently by means of an isotropic, with respect to the fins and the bottom plate selective etching process the thin auxiliary insulating layers lying between the lamellae and at the same time the remainders of the thick auxiliary insulating layer in the entire memory cell region are subsequently structured so as to pattern the bottom plate of the memory cell, whereby the storage electrode consisting of the bottom plate and the lamellae is electrically separated from adjacent storage electrodes of adjacent memory cells, that subsequently by an etching and cleaning process, the fin surfaces and the bottom plate surface are smoothed and cleaned, that subsequently a storage dielectric usgebil dot which completely covers the storage electrode surface, thereafter depositing a conductive layer which completely fills the interstices of adjacent fins, interleaves the fins and forms a cell plate, and then forms a cover insulating layer planarizing the cell plate.

In one embodiment of the invention, the ancestor is characterized in that, within the alternating sequence of the deposition of the conductive lamellae layers and the auxiliary thin insulating layers, the thickness of the lamellae layers is at least the same as the lowermost layer of the baseplate, and after the deposition of each thin auxiliary dielectricization layer an anisotropic RIE Etching process is performed, which selectively ablates on the surface of the thick auxiliary insulating layer and on the bottom surface in dom breakthrough only the thin Hilfsisolstionsschicht, the underlying conductive lamellae schichi stops the etching process, that after deposition of the last conductive lamellar layer, which completely closes the breakthrough of the thick auxiliary insulation layer , an RIE process is performed which removes the layer stack of conductive Lameileri layers lying on the surface of the thick auxiliary insulation layer, whereby the upper ends of the vertically perpendicular z For the substrate surface standing slats are separated from each other, and that after the isotropic removal of the thin auxiliary insulation layers'. Wipe the fins and the remains of the thick auxiliary insulation layer, the bottom plate of the memory cell by means of an anisotropic RIE etching process is self-masking maskless structured. A further embodiment of the method according to the invention is characterized in that after production of the wordline insulated on all sides and the source and drain regions, a lower insulating layer is deposited, that subsequently drain contact windows are patterned in the lower insulating layer, that subsequently the stacked capacitor complex begins with the deposition of the lower conductive layer of the bottom plate, which contacts the drain region is formed, d & ß after deposition of the planarizing cover insulating layer of the stacked capacitor complex, the Bitleitungskontakifensiar is etched into this layer by means of an anisotropic Rlt process, the cell plate stops the process that subsequently by means of an RIE process the Bitleitungskontaktfenster is introduced into the cell plate, wherein the storage dielectric stops the process that subsequently by means of a selective isotropic etching process, the cell plate slants in the K Ontaktfenster are removed behind the Bitleitungskontaktfensterflankrn the cover insulation layer, that then a thin insulating layer is deposited isotropically, then subsequently removed by an anisotropic RIE ProzelJ the thin insulating layer on the surface of the cover insulation layer and on the Billeitungskontaktfenstercberfläche again and the Bitleitungskontaktfenster fully open except for the substrate surface with the bit line contact window flanks covered by the thin insulating layer, subsequently depositing conductive material isotropically deposited, which completely fills the bit line contact window, then subsequently, by an RIE process, etch the deposited conductive material down to the level of the planar surface of the cover insulation layer is, so that it forms a planarized conductive stamp in the bit line contact window, that subsequently formed the bit line wherein the bit line in the memory matrix region contacts the planarized conductive die, and finally an upper insulating layer is deposited on the bit line. In this case, it is possible to oxidize the cell plates before the isotropic deposition of the thin insulation layer.

The inventive method is characterized in a further embodiment, characterized in that after the production of all sides insulated word lines and the source and drain areas a lower insulating layer is formed, that after the source contact window is structured, that subsequently the bit line is formed, at the same time the source contact is made in that thereafter an obove insulating layer covering the bit line is formed, thereafter etching a drain contact window through the upper insulating layer and the bit line in the lower insulating layer by an anisotropic etching process via a resist mask, stopping the etching process before reaching the drain surface of the substrate and the TeMe of the field and word isolation insulation adjacent to the drain contact window are not damaged, and subsequently a further insulation layer is deposited isotropically, the thickness of this layer being distinctly k Longer than half the drain contact window width is that subsequently, by means of an anisotropic RIE process, the drain contact window is recessed down to the drain surface of the substrate, thereby providing all around insulating self-aligned coverage of the drain contact window flanks and the broken bit line along the piercing line of the drain contact window in the form of an insulating jacket Finally, the stack capacitor complex is formed starting with the formation of the bottom conductive layer of the bottom plate, wherein the thickness of the bottom bottom plate layer is greater than the reduced by the insulating jacket width of the drain contact window.

The method is ausgestaltend characterized in that in the anistropic RIE process for etching the drain-contact window, the lower insulating layer is first etched only partially, that after a conductive layer is deposited isotropically, that subsequently an anisotropic RIE process is carried out removes the conductive layer on the upper insulating layer and on the bottom of the drain contact window but leaves on the sidewalls of the drain contact window a conductive ring contacting the outer edge of the drain lines formed on the drain contact window flanks during drain contact window patterning, followed by a thin insulating layer having a thickness , which is significantly smaller than the half-width of the drain contact window reduced by the conductive ring, isotropically deposited, followed by the thin insulation layer with a maskless anisotropic RIE process on all horizontal Surface is etched while remaining on the inner vertical wall surface of the conductive ring, that thereafter the conductive ring is selectively isotropically etched away to the surrounding insulation to a level above the bit line surface, wherein the thin insulating layer which surrounds the inner wall surface of the ring as Component of the insulating jacket is completely retained, that then a further insulating layer is deposited isotropically with a layer thickness greater than half the wall thickness of the ring, that subsequently the drain contact window is structured maskjnlos and anisotropically with an RIE process to the substrate surface, whereby at the same time Isolation jacket is completed, and that after the STC complex is formed beginning with the deposition of the bottom layer of the bottom plate, wherein the thickness of the bottom bottom plate layer is greater than the remaining after formation of the insulation sheath half Br side of the drain contact window. The ring is biw on its exposed surfaces by oxidation. Nitriding covered with a stable insulating layer

 The cell construction can be carried out according to the concept of the open or folded bitline.

Ausfuhrungsbalsplel

The invention will be explained in more detail with reference to an embodiment. In the accompanying drawing show

FIG. 1 a: cell construction diagram of a memory cell arrangement "bitune on STC" (drawn without cell plate) FIG. 1 b: cell layout of a memory cell arrangement "bitline on SfC" (drawn without bit line) FIG. 1 c: cross section oinor memory cell array "bitmap on S FC"

2 a: a cell construct of a memory cell arrangement with "STC on bitline" (drawn without cell plate, STC complex lifted off)

2 b: line layout of a memory cell arrangement "STC on bitline" (drawn without bit line) FIG. 2 c: cross section of a memory cell arrangement "STC on bitline"

FIG. 3 a: lamellar structure of the storage electrode in the plan view of the memory cell layout FIG. 3 b: STC complex in front of RIE of the thick auxiliary insulating layer FIG. 3 c: STC complex before RIE of the first thin auxiliary insulating layer FIG. 3d: STC complex according to FIG RIE of the first thin auxiliary insulating layer Fig. 3 e: STC complex after deposition of the last filling lamellar layer Fig. 3 f: STC complex after RIE of the planar lamella layer stack Fig. 3 g: STC complex after isotropic removal of the auxiliary insulating layers Fig. 3 h: STC complex after mask-free RIE structuring of the bottom plate Fig. 3 i: STC complex final state

4 a: memory cell arrangement "STC on bitline" before RIE of the drain contact window FIG. 4 b: memory cell arrangement "STC on bitline" before RIE structuring of the conductive ring FIG. 4 c: memory cell arrangement "STC on bitline" after RIE strickturation of a thin one Insulation layer on the inner surface

of the conductive ring Fig. 4d: memory cell arrangement "STC on bitline" after deposition of a further insulation layer for the insulation jacket

4 e: memory cell arrangement "STC on bitline" before RIE of the thick auxiliary dispersion layer FIG. 4 f: memory cell arrangement "STC on bitline" after deposition of the insulation insulating layer on the complete STC complex.

The realization of the inventive one-transistor memory cell arrangement for dynamic semiconductor memories is, on the one hand, as shown in FIG. 1, wherein FIG. 1 a shows the cell construction, FIG. 1 b (see cell layout and FIG. 1 c shows the cross-section as a memory cell 2 on the basis of the cell design, FIG. 2b shows the cell layout and FIG. 2c shows the cross section as a memory cell arrangement with bitline on STC: ii.

The invention will be explained in more detail below with reference to the production of an STC on bitline memory cell arrangement.

After the fabrication of n- and p-type CMOS wells, field isolation regions and active regions are formed in a p-doped m-LOCOS silicon substrate followed by LDD-MOS transistors consisting of isolated polysilicon wordlines 12 with silicon dioxide capping , lateral isolation spacers and source 7 and drain regions 9.

Subsequently, a 400 .mu.m thick, rounded lower insulation layer 11 is applied and patterned, whereby source contact windows 8 are opened in the memory matrix. Subsequently, the bite line is generated and connected by deposition, doping and structuring of a polycide layer. Thereafter, a 650nm thick, rounded by RTA, upper insulating layer 13 is applied (Figure 4a) and with an RIE process via a resist mask in the drain areas 9 of the n-LDD-MOS transistors of the memory matrix stoilMankig drain contact window 10 with a minimum account window width of 1 , 0 pm introduced into the upper insulating layer 13, wherein the etching process is stopped by its selectivity against the bit line material on the bit line surface.

With a further RIE process, the bit line 6 exposed in the drain contact window 10 is severed, the lower insulation layer 11 being etched to a remaining residual thickness of 200 nm.

After removing the resist mask and performing a cleaning process, a 20 nm-thick, phosphorous-doped, polysilicon layer is deposited. Thereafter, a 200nm thick tungsten CVD layer conforming to the steep flank of the drain contact window 10 is deposited (Fig. 4b) and removed from all horizontal surfaces by a subsequent anisotropic RIE process. However, the double layer consisting of tungsten and polysilicon remains in the form of a conductive ring 16 on the steep flanks of the drain contact window 10. The conductive ring 16 contacts the bit line 6 which has been broken by the drain contact window etch process and closes it again except for the drain contact window 10 remaining in the center of the conductive ring.

In this RIE etching process, a large-area Abtrao the upper insulating layer 13 and in the region of the remaining drain contact window 10 at the same time the lower insulating layer 11 of about 50nm.

Following this etching process, a thin insulating layer 20 in the form of a 50nm thick silicon nitride layer is deposited by an LPCVD process and removed from the horizontal surfaces by an anisotropic RIE etching process, leaving the silicon nitride layer 20 on the inner horizontal wall surface of the conductive ring 16 'with unattenuated thickness obtained (Figure 4c).

Subsequently, the exposed top surface of the conductive ring 16 isotropic and selective to a level of about

Etched 200nm above the bit line surface, with the silicon nitride layer 20 remaining intact on the inner vertical wall surface of the conductive ring 16.

Thereafter, a 140 nm thick silicon nitride layer is deposited by means of an LPCVD process (FIG. 4d) and then removed again on all horizontal surfaces by an anisotropic RIE process. By continuing the RIE process will

Subsequently, the drainage contact window 10 remaining in the center of the conductive ring 16 is opened up to the surface of the substrate. Dor conductive ring 16 is thus at its upper top surface and its inner vertical wall surface by an insulating jacket 15, which is formed from two mask-free structured silicon nitride layers, covered. After cleaning the remaining exposed drain contact window surface 10, a 100 nm thick η-conductive polysilicon layer as the bottom bottom plate layer 2a, which contacts the drain region 9 and completely fills the remaining in the center of the conductive ring 16 and its insulating jacket 15 drain contact window 10 in the form of a conductive die 14 , isolated.

Subsequently, a 1 pm thick planarized auxiliary insulator layer 17 is applied (Figure 4 e; Figure 3b) and a resist mask with an anisotropic selective RIE process, which is stopped on the bottom bottom plate layer 2 A, a steep flankigor breakthrough with a width of 1.6μπι introduced into the auxiliary insulator layer 17. After removing the resist mask and performing a cleaning process, an n-type polysilicon layer having a thickness of 175 nm is deposited as a first conductive fin layer, followed by a first thin auxiliary insulation layer 18 having a thickness of 180 nm (Figure 3c) and then by an anisotropic RIE. Process on all horizontal surfaces again removed, wherein the anisotropic etching process is stopped on the first fin layer (Figure 3d). After a cleaning process again an n-type polysilicon layer is deposited, another thin auxiliary insulation layer 18 is applied with a thickness of 180 nm and removed with an anisotropic RIE process, so that the steep, vertical side walls of the opening of a layer sequence of polysilicon layer and thinner Auxiliary insulator layer 18 are covered twice and remains in the center of the opening a residual opening of 180 nm minimum width. This residual opening is completely filled by depositing a 120 nm thick n-type polysilicon layer as the last lamella layer (FIG. 3e). Subsequently, the layer stack of all the lamination layers lying on the surface of the thick auxiliary insulation layer 17 is removed by a RIE process, exposing the surfaces of the thick auxiliary insulation layer 17 and the thin auxiliary insulation layers 18 remaining in the steep flank breakthrough and arranging the upper ends of them perpendicularly in the breakdown Polysilicon fins 3 are separated from each other (Fig. 3f). After the subsequent selective wet-chemical removal of the thin 18 and the thick auxiliary insulating layers 17 (Figure 3g) in the region of the previous steep-flanking opening vertically free-standing polysilicon 3 are removed by an anisotropic RIE ancestor vertically by the thickness of the bottom bottom plate layer 2 A, wherein the RIE process on the upper insulating layer 13 is stopped. By this RIE method, the complete self-aligned etching of the bottom bottom plate layer 2 A in the area outside the previous steep-flanking breakthrough, and thus the separation of the storage electrodes 1 adjacent memory cells, wherein the conductive fins horizontally connecting conductive bottom plate?, Which from the bottom bottom plate layer 2 A and the horizontal portions of these polysilicon lamellae layers are cleaved to the thickness of the bottommost bottom plate layer but not severed (Figure 3h). Subsequent to this etching process, a 3nm thick polysilicon oxide layer, a 10nm thick LPCVD silicon nitride layer, and a reoxidation of the silicon nitride layer are formed into an ONO memory dielectric 4 having a silicon dioxide equivalent thickness of 8nm.

After this, an n-doped polysilicon layer is deposited and patterned as a cell plate 5 with a thickness of 150 nm, which completely fills the spaces between the polysilicon fins 3

 Finally, a planarizing cover insulation layer 19 is deposited and patterned (FIG.

Claims (14)

1. One-transistor memory cell for dynamic semiconductor spi. >. Ser consisting of field isolation regions and active surface region; The single-crystalline substrate in which a MOS field-effect transistor is integrated with a word line insulated a'nseitin and a source and a drain region, as well as arranged over the word lineurturtd the area of the memory cell largely covering stack capacitor complex, which with its storage electrode the drain region is connected and its upper electrode is formed as a cell plate of all memory cells of a memory matrix block, and a bit line contacted to the source region, characterized in that the storage electrode (1) is arranged on a common, conductive bottom plate (2) perpendicular to the substrate surface Slats (3), each of which in the memory cell layout a retreating and closed band whose width corresponds to the wall thickness of the slats (3), that each of the slats (3) starting with an outermost slat (3 A), the within the storage cell e is arranged, each enclosing a smaller, along the lamellar circumference of the wall-to-wall distance of adjacent lamellae (3) is constant and corresponds approximately to the lamella wall thickness, that the inner wall surfaces of the innermost, arranged in the center of the stack capacitor complex lamella (3B) over the entire surface contacting a storage dielectric (4) covering the storage electrode (1) with the exception of the underside of the bottom plate, that a cell plate (5) surrounds the storage electrode (1) in a toothed manner, the spaces between the adjacent lamellae (3) being completely filled and those against the outermost lamella (3A) bordering, with memory dielectric (4) covered areas of the bottom plate (2) and the memory cell are also covered with the cell plate (5), and that due to design necessary contact points in the cell plate (5) breakthroughs are arranged. 2. Memory cell arrangement according to claim 1, characterized in that the bottom plate (2) in the memory cell layout exactly corresponds to the area which is enclosed by the circumference of the outermost lamella (3 A). 3. Memory cell arrangement according to claim 1, characterized in that the bottom plate (2) consists of a plurality of conductive layers, wherein the layer thickness of a lowermost conductive bottom plate layer (2A) is less than or equal to the wall thickness of the lamellae (3) and the bottom plate surface corresponds at least to the surface, which is enclosed by the beginning of the outermost lamella (3A), that on the lowest conductive bottom plate layer (2 A), a second conductive layer is arranged, whose layer thickness corresponds to the wall thickness of the outermost lamella (3 A) and whose surface that of the circumference of the outermost lamella (3A) corresponds exactly to the enclosed surface, that a third conductive layer is arranged on the second conductive layer whose layer thickness corresponds to the wall thickness of the next inner lamella and whose surface exactly corresponds to the area enclosed by the circumference of the next inner lamella, and that further conductive layers are analogous to those in FIG previously mentioned nten layers are arranged. 4. Memory cell arrangement according to uinem of the preceding claims, characterized in that the lamellae (3) regardless of the relief of the bottom plate (2), with which they are contacted, and regardless of the relief of the under the bottom plate (2) arranged Speillierzellenelemente in a uniform height the level of the substrate surface. 5. Memory cell arrangement according to one of the preceding claims, characterized in that a bit line (6) is arranged on the isolated stacked capacitor complex, wherein formed in the source contact window (8) lying part of the bit line (6) stamped and planarized with respect to the top of the stack capacitor complex and that the drain contact of the storage electrode (1) by direct contact of the bottom plate (2) with the drain region (9) in a drain contact window (10) of a lower insulating layer (11) on the isolated word lines (12) and over the remaining Memory cell areas except for the contact window of the source (7) and drain pads (9) is arranged takes place. 6. memory cell arrangement according to one of claims 1 to 4, characterized in that the with an upper insulating layer (13) covered bit line (6) below the stack capacitor complex is arranged, wherein the bit line (6) on the lower insulating layer (11) above the word line isolation is arranged urd the lower insulating layer (11) covers all areas of the spoke cell except the source and Drainkontaktf ansterbereich that the bit line (6) in the source contact window (8) the Source region (7) contacted and that an insulated conductive punch (14) which contacts the drain region (9) in the drain contact window (10) pierces the lower insulating layer (13) and the bottom of the bottom plate (2) contacted. 7. memory cell arrangement according to claims 1-4 and 6, characterized in that the vertical surface of the punch (14) by an insulating jacket (15) is covered with a constant thickness self-adjusting. 8. memory cell arrangement according to claims 1-4 and 6 or 7, characterized in that the bit line (6) at a punch diameter of approximately the Bitleitungsbreite at the piercing point by a conductive ring (16), the isolated punch (14) with a constant Thickness self-aligning encloses, is supplemented, wherein the conductive ring (16) in height equal to at least the thickness of the bit line (6) and against dam drained area (9), the word line (12) and the bottom plate (2) is electrically isolated. 9. A method for producing an If.in-transistor memory cell array, wherein in a single-crystalline substrate η-type and p-type regions, field isolation regions and subsequently MOS field effect transistors with all sides insulated word lines and source and drain areas, a lowermost leitendo layer of a Storage electrode, which generates the contact of a stacked capacitor to the underlying drain region of the memory cell, formed in a memory matrix stacked capacitor complex and contacted with the source region of the memory cell bit line and finally etched at contact points breakthroughs in the cell plate of the stacked capacitor complex, characterized in that after deposition of a a thick auxiliary insulation layer (17) is planarized deposited, that in the connection in the thick auxiliary insulation layer (17) a steep-flared opening down to the lowest conductive Bottom plate layer (2 A) is formed so that a conductive lamellar layer and then a thin Hilfsisoiationschicht (18) are deposited, starting and ending with a deposition of a conductive lamellae in an alternating sequence, the double sum of all conductive lamellae and Hilfsi¬ olationsschichtdicken the shortest Distance of opposite wall surfaces of the steillankigen breakthrough in the thick auxiliary insulating layer (17) corresponds, and at least after each Abbeheidung a thin auxiliary insulating layer (18) an anisotropic R! E process is performed, wherein on the surface of the thick auxiliary insulating layer (17) and on the Floor surface in the aperture at least the last deposited layer is etched, while the last deposited and all previously deposited layers remain on the vertical walls of the opening and form a lamellar structure, that after the deposition of the last conductive lamella nschicht is etched by means of a RIE process, the surface of the thick auxiliary insulation layer (17) of the last lamellar layer and underlying lamellar layers, whereby the upper ends of the etched lamellae (3) are separated from each other, then by means of an isotropic, with respect to the lamellae (3 ) and the bottom plate (2) selective etching process between the lamellae (3) thin auxiliary insulating layers (18) and at the same time the remains of the thick auxiliary insulating layer (17) are removed in the entire Spöicherzellengebiet that subsequently structured the bottom plate (2) of the memory cell becomes, whereby the l. , Floor plate (2) and the lamellae (3) existing storage electrode (1) of adjacent storage electrodes (1) adjacent memory cells is electrically separated, that are subsequently smoothed and cleaned by an etching and cleaning process, the fin surfaces and the bottom plate surface and then a memory dielectric ( 4) is formed, which completely covers the storage electrode surface, that thereafter a conductive layer is deposited, which completely fills the interstices of adjacent lamellae (3), the lamellae (3) interlocked encloses and forms a cell plate (5), and then one of the Cell plate planarizing cover insulation layer (19) is formed. 10. The method according to claim 9, characterized in that within the alternating sequence of deposits of denleitynden lamellar layers and the thin auxiliary insulation layers (18) the thickness of the lamellar layers at least the thickness of the bottom layer (2 A) of the bottom plate (2) and after deposition performing an anisotropic RIE etching process on each thin auxiliary insulating layer (18), selectively ablating only the thin auxiliary insulating layer (18) on the surface of the thick auxiliary insulating layer (17) and on the bottom surface in the breakdown, the underlying conductive fin layer stopping the etching process after deposition of the last conductive lamellar layer containing the Breakthrough of the thick auxiliary insulating layer (17) closes completely, a RIE process is carried out, which removes the lying on the surface of the thick auxiliary insulating layer (17) layer stack of all conductive fin layers, whereby the upper ends of the perpendicular to the substrate surface slats (3) separated from each other be, and that after the isotropic removal of the thin auxiliary insulation layers (18) between the lamellae (3) and the remains of the thick auxiliary insulation layer (17), the bottom plate (2) of the memory cell by means of an anisotropic RIE etching process is self-masking maskless structured. 11. The method according to claim 9 or 10, characterized in that after the production of the all-sides insulated word line (12) and the source (7) and drain areas (9) a lower insulating layer (11) is deposited, that subsequently in the lower insulating layer (11) drain contact windows (1 C) are patterned, then the stacked capacitor complex is formed starting with the deposition of the lower conductive layer (2a) of the bottom plate (2) contacting the drainage region (9) such that after deposition of the planarizing overcoat insulating layer (19) of the stack capacitor complex, the bit line contact window (8) is etched in this layer by means of an anisotropic RIE process, wherein the cell plate (5) stops the process, then subsequently, by means of an RIE process, the bit line contact window (8) into the cell plate (5). is introduced, wherein the storage dielectric (4) stops the process that subsequently by means of a selective isotropic tzprozesses the cell plate flanks in the contact window (8) behind the Bitleitungskontaktfensterflanken the Deckisolationsschichl (19) are removed, that then a thin insulating layer (20) isotropically deposited, then by an anisotropic RIE process, the thin insulating layer (20) on the surface of the cover insulating layer (19) and on the bit line contact window surface is removed again and the bit line contact window (8) is fully opened except for the substrate surface, wherein the Bitleitungskontaktfonsterflanken remain covered by the thin insulating layer (20), that subsequently conductive material is deposited isotropically, the Bitleitungskontaktfenster (8 ) completely filled, that then by an RIE process, the deposited conductive material is etched back to the level of the planar surface of the cover insulating layer (19) so that it in the Bitleitungskonstaktfenster (8) planarisie conductive pad (21) forms, that the bit line (6) is formed thereafter, wherein the bit line (6) in the memory matrix region contacted the planarized conductive punch (21), and that finally on the bit line (6) has an upper insulating layer ( 13) is deposited. 12. The method according to claim 9 or 10, characterized in that after the production of all sides of isolated word lines (12) and the source (7) and drain areas (9), a lower insulating layer (11) is formed, that thereafter the source contact window (8) is structured, that then the bit line (6) is formed, wherein at the same time the source contact is made, that following the bit line (6) covering the upper insulating layer (13) is formed, that thereafter by an anisotropic etching process via a resist mask, a drain contact window (10) through the upper insulating layer (13), the bit line (6) and the lower insulating layer (11) is etched, wherein the etching process is stopped before reaching the drain surface of the substrate and the drain contact window (10) adjacent parts of the field and Wortleitungsisolation be damaged, that then a further insulation layer is deposited isotropically, wherein the thickness this layer is significantly smaller than half the drain contact window width, then, by means of an anisotropic RIE process, the drain contact window (10) is recessed down to the drain surface of the substrate, thereby providing a completely insulating self-aligned coverage of the drain contact window flanks and the broken bit line (6 ) is formed along the puncture line of the drain contact window (10) in the form of an insulating jacket (15), and finally the stacked capacitor complex is formed beginning with the formation of the lowermost conductive layer (2A) of the bottom plate (2), the thickness of the bottommost bottom plate layer (FIG. 2 A) is greater than the reduced by the insulating jacket (15) half the width of the drain contact window (10). 13. The method according to claim 12, characterized in that in the anisotropic RIE process for etching the drain contact window (10), the lower insulating layer (11) is first etched only partially, that thereafter a conductive layer is deposited isotropically, wherein the thickness of this layer is significantly smaller than half the drain contact window width, that is followed by an anisotropic RIE process is performed, which removes the conductive layer on the upper insulating layer (13) and on the bottom of the drain contact window (10), on the flanks of the drain contact window (10), however, leaves a conductive ring (16) contacting the drain line contact edges formed on the drain contact window flanks with its outer circumference, followed by a thin insulation layer (20) having a thickness significantly smaller than that through the conductive half (16) of the drain contact window (10) is deposited isotropically, then the thin insulating layer (20) is etched off with a maskless anisotropic RIE process on all horizontal surfaces while adhering to the inner vertical wall surface of the conductive ring (16), thereafter leaving the conductive ring (16) selectively isotropically etched to a level above the bit line surface, the thin insulating layer (20) covering the inner wall surface of the ring (16) forming part of Insulation jacket (15) is completely preserved, that subsequently a further insulating layer with a layer thickness greater than half the wall thickness of the ring (16) is deposited isotropically, that subsequently the drain contact window (10) structured maskenlos and anisotropically with an RIE process to the substrate surface, whereby at the same time the insulating jacket (15) is completed, and that thereafter the stack capacitor complex is formed starting with the deposition of the lowermost layer (2A) of the bottom plate (2), the thickness of the bottom bottom plate layer (2A) being greater than that after formation of the isolation jacket (15). remaining half width of the drain contact window (10). 14. The method according to claim 13, characterized in that the ring (16) is covered on its exposed surfaces by oxidation or nitration with a stable insulating layer.