FR2603129A1 - Circuit de redondance de colonne pour memoire a acces aleatoire dynamique en technologie cmos - Google Patents
Circuit de redondance de colonne pour memoire a acces aleatoire dynamique en technologie cmosInfo
- Publication number
- FR2603129A1 FR2603129A1 FR8711801A FR8711801A FR2603129A1 FR 2603129 A1 FR2603129 A1 FR 2603129A1 FR 8711801 A FR8711801 A FR 8711801A FR 8711801 A FR8711801 A FR 8711801A FR 2603129 A1 FR2603129 A1 FR 2603129A1
- Authority
- FR
- France
- Prior art keywords
- column
- normal
- random access
- spare
- dynamic random
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Dram (AREA)
Abstract
MEMOIRE A ACCES ALEATOIRE DYNAMIQUE POUR SUBSTITUER A UNE LIGNE DE COLONNE NORMALE 70 COUPLEE A DES CELLULES DE MEMOIRES NORMALES DEFECTUEUSES UNE LIGNE DE COLONNE DE RECHANGE 60 COUPLEE A DES CELLULES DE MEMOIRES SANS DEFAUT AVEC UN MOYEN DE VERROUILLAGE AYANT UN FUSIBLE PILOTE ET UNE HORLOGE DE RESTAURATION DESSERVANT UNE BORNE D'ENTREE. UN MOYEN 200 DE DECODAGE DES COLONNES DE RECHANGE VALIDE OU INVALIDE LA LIGNE DE COLONNES DE RECHANGE AVEC LA SORTIE DES MOYENS DE VERROUILLAGE ET L'ENTREE SELECTIVE SOIT DE SIGNAUX VRAIS D'ADRESSES DE COLONNE SOIT DE SIGNAUX COMPLEMENTAIRES D'ADRESSE DE COLONNE ET UNE PLURALITE DE MOYENS DE DECODAGE DE COLONNE NORMALE 47 VALIDE OU INVALIDE LES LIGNES DE COLONNE NORMALE AVEC LES SIGNAUX D'ADRESSE DE COLONNE DIRIGEANT UNE LIGNE DE COLONNE NORMALE SPECIFIEE SOUS LA COMMANDE DE LA SORTIE DU MOYEN DE DECODAGE DE LA COLONNE DE RECHANGE.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019860006932A KR890003691B1 (ko) | 1986-08-22 | 1986-08-22 | 블럭 열 리던던씨 회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2603129A1 true FR2603129A1 (fr) | 1988-02-26 |
FR2603129B1 FR2603129B1 (fr) | 1990-08-17 |
Family
ID=19251841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR878711801A Expired - Lifetime FR2603129B1 (fr) | 1986-08-22 | 1987-08-21 | Circuit de redondance de colonne pour memoire a acces aleatoire dynamique en technologie cmos |
Country Status (8)
Country | Link |
---|---|
US (1) | US4829480A (fr) |
JP (1) | JPS6353794A (fr) |
KR (1) | KR890003691B1 (fr) |
DE (1) | DE3724509A1 (fr) |
FR (1) | FR2603129B1 (fr) |
GB (1) | GB2195480B (fr) |
HK (1) | HK18393A (fr) |
SG (1) | SG58292G (fr) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2647583A1 (fr) * | 1989-05-24 | 1990-11-30 | Samsung Electronics Co Ltd | Dispositif de memoire a semiconducteurs avec bloc redondant |
FR2680590A1 (fr) * | 1991-08-21 | 1993-02-26 | Samsung Electronics Co Ltd | Agencement d'un reseau de cellules redondant pour un dispositif de memoire a semiconducteurs. |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5426607A (en) * | 1988-04-27 | 1995-06-20 | Sharp Kabushiki Kaisha | Redundant circuit for memory having redundant block operatively connected to special one of normal blocks |
KR910003594B1 (ko) * | 1988-05-13 | 1991-06-07 | 삼성전자 주식회사 | 스페어컬럼(column)선택방법 및 회로 |
US5687109A (en) * | 1988-05-31 | 1997-11-11 | Micron Technology, Inc. | Integrated circuit module having on-chip surge capacitors |
US5327380B1 (en) * | 1988-10-31 | 1999-09-07 | Texas Instruments Inc | Method and apparatus for inhibiting a predecoder when selecting a redundant row line |
NL8900026A (nl) * | 1989-01-06 | 1990-08-01 | Philips Nv | Matrixgeheugen, bevattende standaardblokken, standaardsubblokken, een redundant blok, en redundante subblokken, alsmede geintegreerde schakeling bevattende meerdere van zulke matrixgeheugens. |
KR920010347B1 (ko) * | 1989-12-30 | 1992-11-27 | 삼성전자주식회사 | 분할된 워드라인을 가지는 메모리장치의 리던던시 구조 |
KR920009059B1 (ko) * | 1989-12-29 | 1992-10-13 | 삼성전자 주식회사 | 반도체 메모리 장치의 병렬 테스트 방법 |
KR930000821B1 (ko) * | 1990-02-24 | 1993-02-05 | 현대전자산업 주식회사 | 메모리 소자의 저소비 전력 리던던시(Redundancy)회로 |
JP2575919B2 (ja) * | 1990-03-22 | 1997-01-29 | 株式会社東芝 | 半導体記憶装置の冗長回路 |
US5293564A (en) * | 1991-04-30 | 1994-03-08 | Texas Instruments Incorporated | Address match scheme for DRAM redundancy scheme |
EP0514664A3 (en) * | 1991-05-20 | 1993-05-26 | International Business Machines Corporation | Dynamic random access memory with a redundancy decoder |
KR940006079B1 (ko) * | 1991-06-14 | 1994-07-06 | 삼성전자 주식회사 | 반도체 메모리 장치 |
US6026505A (en) * | 1991-10-16 | 2000-02-15 | International Business Machines Corporation | Method and apparatus for real time two dimensional redundancy allocation |
US5471426A (en) * | 1992-01-31 | 1995-11-28 | Sgs-Thomson Microelectronics, Inc. | Redundancy decoder |
US5295102A (en) * | 1992-01-31 | 1994-03-15 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with improved redundant sense amplifier control |
US5278793A (en) * | 1992-02-25 | 1994-01-11 | Yeh Tsuei Chi | Memory defect masking device |
KR950000275B1 (ko) * | 1992-05-06 | 1995-01-12 | 삼성전자 주식회사 | 반도체 메모리 장치의 컬럼 리던던시 |
US5301153A (en) * | 1992-06-03 | 1994-04-05 | Mips Computer Systems, Inc. | Redundant element substitution apparatus |
JP2870320B2 (ja) * | 1992-09-29 | 1999-03-17 | 日本電気株式会社 | 半導体メモリ回路 |
US5392245A (en) * | 1993-08-13 | 1995-02-21 | Micron Technology, Inc. | Redundancy elements using thin film transistors (TFTs) |
JP3530574B2 (ja) * | 1994-05-20 | 2004-05-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
KR0130030B1 (ko) * | 1994-08-25 | 1998-10-01 | 김광호 | 반도체 메모리 장치의 컬럼 리던던시 회로 및 그 방법 |
KR970001564U (ko) * | 1995-06-21 | 1997-01-21 | 자동차용 후부차체의 보강구조 | |
KR0167678B1 (ko) * | 1995-08-22 | 1999-02-01 | 김광호 | 컬럼 리던던시 회로를 가지는 반도체 메모리 장치 |
US5771195A (en) * | 1995-12-29 | 1998-06-23 | Sgs-Thomson Microelectronics, Inc. | Circuit and method for replacing a defective memory cell with a redundant memory cell |
US5612918A (en) * | 1995-12-29 | 1997-03-18 | Sgs-Thomson Microelectronics, Inc. | Redundancy architecture |
US6037799A (en) * | 1995-12-29 | 2000-03-14 | Stmicroelectronics, Inc. | Circuit and method for selecting a signal |
US5841709A (en) * | 1995-12-29 | 1998-11-24 | Stmicroelectronics, Inc. | Memory having and method for testing redundant memory cells |
US5790462A (en) * | 1995-12-29 | 1998-08-04 | Sgs-Thomson Microelectronics, Inc. | Redundancy control |
KR0179550B1 (ko) * | 1995-12-29 | 1999-04-15 | 김주용 | 반도체 메모리 장치의 리던던시 회로 |
KR100224774B1 (ko) * | 1996-06-29 | 1999-10-15 | 김영환 | 반도체 메모리 장치의 컬럼 리던던시 회로 |
KR100228533B1 (ko) * | 1997-06-23 | 1999-11-01 | 윤종용 | 반도체 집적회로의 용단가능한 퓨즈 및 그 제조방법 |
US5999463A (en) * | 1997-07-21 | 1999-12-07 | Samsung Electronics Co., Ltd. | Redundancy fuse box and semiconductor device including column redundancy fuse box shared by a plurality of memory blocks |
KR100542696B1 (ko) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 장치의 리페어 퓨즈 박스 |
EP2351652B1 (fr) | 2008-10-10 | 2014-12-24 | Kotobuki & Co., Ltd. | Structure de montage d'attache pour outil d'écriture |
US10134486B2 (en) * | 2016-09-13 | 2018-11-20 | Samsung Electronics Co., Ltd. | Memory device including a redundancy column and a redundancy peripheral logic circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0034070A2 (fr) * | 1980-02-12 | 1981-08-19 | Mostek Corporation | Système de mémoire tolérant des fautes |
EP0115128A2 (fr) * | 1982-12-04 | 1984-08-08 | Fujitsu Limited | Dispositif de mémoire semi-conductrice divisée en blocs |
EP0115170A2 (fr) * | 1982-12-28 | 1984-08-08 | Kabushiki Kaisha Toshiba | Appareil de programmation pour circuit redondant dans un système de circuit redondant |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS555698B2 (fr) * | 1972-06-14 | 1980-02-08 | ||
US4228528B2 (en) * | 1979-02-09 | 1992-10-06 | Memory with redundant rows and columns | |
JPS5677997A (en) * | 1979-11-28 | 1981-06-26 | Fujitsu Ltd | Semiconductor memory device |
US4346459A (en) * | 1980-06-30 | 1982-08-24 | Inmos Corporation | Redundancy scheme for an MOS memory |
US4389715A (en) * | 1980-10-06 | 1983-06-21 | Inmos Corporation | Redundancy scheme for a dynamic RAM |
JPS59119743A (ja) * | 1982-12-25 | 1984-07-11 | Nippon Telegr & Teleph Corp <Ntt> | 集積回路の冗長構成方式 |
US4556975A (en) * | 1983-02-07 | 1985-12-03 | Westinghouse Electric Corp. | Programmable redundancy circuit |
US4601019B1 (en) * | 1983-08-31 | 1997-09-30 | Texas Instruments Inc | Memory with redundancy |
JPS61217993A (ja) * | 1985-03-22 | 1986-09-27 | Mitsubishi Electric Corp | 半導体メモリ |
JPS632351A (ja) * | 1986-06-20 | 1988-01-07 | Sharp Corp | 半導体装置 |
-
1986
- 1986-08-22 KR KR1019860006932A patent/KR890003691B1/ko not_active IP Right Cessation
-
1987
- 1987-07-23 JP JP62182412A patent/JPS6353794A/ja active Granted
- 1987-07-24 DE DE19873724509 patent/DE3724509A1/de active Granted
- 1987-08-21 US US07/088,151 patent/US4829480A/en not_active Expired - Lifetime
- 1987-08-21 FR FR878711801A patent/FR2603129B1/fr not_active Expired - Lifetime
- 1987-08-24 GB GB8719936A patent/GB2195480B/en not_active Expired - Lifetime
-
1992
- 1992-06-03 SG SG582/92A patent/SG58292G/en unknown
-
1993
- 1993-03-04 HK HK183/93A patent/HK18393A/xx not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0034070A2 (fr) * | 1980-02-12 | 1981-08-19 | Mostek Corporation | Système de mémoire tolérant des fautes |
EP0115128A2 (fr) * | 1982-12-04 | 1984-08-08 | Fujitsu Limited | Dispositif de mémoire semi-conductrice divisée en blocs |
EP0115170A2 (fr) * | 1982-12-28 | 1984-08-08 | Kabushiki Kaisha Toshiba | Appareil de programmation pour circuit redondant dans un système de circuit redondant |
Non-Patent Citations (2)
Title |
---|
IEEE ELECTRO, vol. 7, mai 1982, pages 26/3-1-6, New York, US; J.P. ALTNETHER et al.: "Testing redundant memories" * |
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-20, no. 5, octobre 1985, pages 941-950, IEEE, New York, US; L.C. SOOD et al.: "A fast 8Kx8 CMOS SRAM with internal power down design techniques" * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2647583A1 (fr) * | 1989-05-24 | 1990-11-30 | Samsung Electronics Co Ltd | Dispositif de memoire a semiconducteurs avec bloc redondant |
NL9000227A (nl) * | 1989-05-24 | 1990-12-17 | Samsung Electronics Co Ltd | Halfgeleider-geheugeninrichting met redundant blok. |
FR2680590A1 (fr) * | 1991-08-21 | 1993-02-26 | Samsung Electronics Co Ltd | Agencement d'un reseau de cellules redondant pour un dispositif de memoire a semiconducteurs. |
Also Published As
Publication number | Publication date |
---|---|
JPS6353794A (ja) | 1988-03-08 |
SG58292G (en) | 1992-07-24 |
US4829480A (en) | 1989-05-09 |
KR880003329A (ko) | 1988-05-16 |
GB2195480A (en) | 1988-04-07 |
GB8719936D0 (en) | 1987-09-30 |
HK18393A (en) | 1993-03-12 |
KR890003691B1 (ko) | 1989-09-30 |
FR2603129B1 (fr) | 1990-08-17 |
JPH0535520B2 (fr) | 1993-05-26 |
DE3724509A1 (de) | 1988-02-25 |
GB2195480B (en) | 1990-12-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property |