FR2590425B1 - Appareillage pour regler les phases de signaux de donnees appliques a un circuit d'utilisation de donnees - Google Patents

Appareillage pour regler les phases de signaux de donnees appliques a un circuit d'utilisation de donnees

Info

Publication number
FR2590425B1
FR2590425B1 FR868601923A FR8601923A FR2590425B1 FR 2590425 B1 FR2590425 B1 FR 2590425B1 FR 868601923 A FR868601923 A FR 868601923A FR 8601923 A FR8601923 A FR 8601923A FR 2590425 B1 FR2590425 B1 FR 2590425B1
Authority
FR
France
Prior art keywords
phases
data
adjusting
signals applied
use circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR868601923A
Other languages
English (en)
Other versions
FR2590425A1 (fr
Inventor
Randall D Rettberg
Lance A Glasser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bolt Beranek and Newman Inc
Original Assignee
Bolt Beranek and Newman Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bolt Beranek and Newman Inc filed Critical Bolt Beranek and Newman Inc
Publication of FR2590425A1 publication Critical patent/FR2590425A1/fr
Application granted granted Critical
Publication of FR2590425B1 publication Critical patent/FR2590425B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
FR868601923A 1985-02-13 1986-02-12 Appareillage pour regler les phases de signaux de donnees appliques a un circuit d'utilisation de donnees Expired - Fee Related FR2590425B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/701,116 US4700347A (en) 1985-02-13 1985-02-13 Digital phase adjustment

Publications (2)

Publication Number Publication Date
FR2590425A1 FR2590425A1 (fr) 1987-05-22
FR2590425B1 true FR2590425B1 (fr) 1992-09-11

Family

ID=24816137

Family Applications (1)

Application Number Title Priority Date Filing Date
FR868601923A Expired - Fee Related FR2590425B1 (fr) 1985-02-13 1986-02-12 Appareillage pour regler les phases de signaux de donnees appliques a un circuit d'utilisation de donnees

Country Status (7)

Country Link
US (1) US4700347A (fr)
JP (1) JPS6223647A (fr)
AU (1) AU586664B2 (fr)
CA (1) CA1256168A (fr)
DE (1) DE3604277C2 (fr)
FR (1) FR2590425B1 (fr)
GB (1) GB2171577B (fr)

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CA2078310A1 (fr) * 1991-09-20 1993-03-21 Mark A. Kaufman Processeur numerique a memoire repartie
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US5313501A (en) * 1992-06-15 1994-05-17 Digital Equipment Corporation Method and apparatus for deskewing digital data
US5436908A (en) * 1992-06-17 1995-07-25 National Semiconductor Corporation Common edge output skew detection circuit
CA2099348A1 (fr) * 1992-07-01 1994-01-02 John V. Camlet Dispositif de synchronisation de signaux de donnees dans un systeme optique commute
US5634041A (en) * 1992-08-12 1997-05-27 Massachusetts Institute Of Technology Rationally clocked communication interface
US5359630A (en) * 1992-08-13 1994-10-25 Digital Equipment Corporation Method and apparatus for realignment of synchronous data
US5414832A (en) * 1992-12-17 1995-05-09 International Business Machines Corporation Tunable synchronous electronic communication apparatus
FR2704376B1 (fr) * 1993-04-22 1995-06-30 Rainard Jean Luc Procédé de récupération d'horloge et de synchronisation pour la réception d'informations transmises par un réseau ATM et dispositif de mise en Óoeuvre du procédé.
US5509037A (en) * 1993-12-01 1996-04-16 Dsc Communications Corporation Data phase alignment circuitry
US5532632A (en) * 1994-02-01 1996-07-02 Hughes Aircraft Company Method and circuit for synchronizing an input data stream with a sample clock
JP3386221B2 (ja) * 1994-03-17 2003-03-17 富士通株式会社 非同期データのクロック乗換回路
US5579352A (en) * 1994-04-06 1996-11-26 National Semiconductor Corporation Simplified window de-skewing in a serial data receiver
US5537068A (en) * 1994-09-06 1996-07-16 Intel Corporation Differential delay line clock generator
US5828250A (en) * 1994-09-06 1998-10-27 Intel Corporation Differential delay line clock generator with feedback phase control
US5768283A (en) * 1994-11-08 1998-06-16 Washington University Digital phase adjustment circuit for asynchronous transfer mode and like data formats
SE504426C2 (sv) * 1996-01-26 1997-02-10 Ericsson Telefon Ab L M Förfarande och anordning för skewminimering
US5727021A (en) * 1996-04-03 1998-03-10 Teradyne, Inc. Apparatus and method for providing a programmable delay with low fixed delay
IT1284718B1 (it) * 1996-07-31 1998-05-21 Cselt Centro Studi Lab Telecom Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.
DE19713660A1 (de) * 1997-04-02 1998-10-08 Siemens Nixdorf Inf Syst Phasenjustierung schneller paralleler Signale
JP2993463B2 (ja) * 1997-05-08 1999-12-20 日本電気株式会社 同期回路制御装置
JP2002505533A (ja) * 1997-09-19 2002-02-19 フジツウ ネットワーク コミュニケーションズ，インコーポレイテッド 一定位相クロスバ交換機
US6304125B1 (en) 1998-09-04 2001-10-16 Sun Microsystems, Inc. Method for generating and distribution of polyphase clock signals
US6188262B1 (en) * 1998-09-04 2001-02-13 Sun Microsystems, Inc. Synchronous polyphase clock distribution system
US6466589B1 (en) 1998-10-19 2002-10-15 Chin-Shen Chou Apparatus for verifying data integrity and synchronizing ATM cell data format for processing
JP2000174736A (ja) * 1998-12-08 2000-06-23 Sharp Corp ビット同期回路
JP3789247B2 (ja) 1999-02-26 2006-06-21 Ｎｅｃエレクトロニクス株式会社 クロック周期検知回路
US6453431B1 (en) * 1999-07-01 2002-09-17 International Business Machines Corporation System technique for detecting soft errors in statically coupled CMOS logic
US6272193B1 (en) * 1999-09-27 2001-08-07 Genesis Microchip Corp. Receiver to recover data encoded in a serial communication channel
US6704882B2 (en) 2001-01-22 2004-03-09 Mayo Foundation For Medical Education And Research Data bit-to-clock alignment circuit with first bit capture capability
EP1355443A1 (fr) * 2002-08-02 2003-10-22 Agilent Technologies Inc. a Delaware Corporation Récupération d'un flux de données par sur-échantillonage
US7324421B1 (en) * 2002-08-13 2008-01-29 Adaptec, Inc. Method and apparatus for data bit align
WO2006030343A1 (fr) * 2004-09-14 2006-03-23 Koninklijke Philips Electronics N.V. Circuit de commande de retard et procede associe
EP1772795A1 (fr) * 2005-10-10 2007-04-11 STMicroelectronics (Research & Development) Limited Pointeur de mémoire tampon rapide via l'horloge
US7865088B2 (en) 2006-05-12 2011-01-04 Alcatel Lucent Burst mode optical receiver
US7929866B2 (en) * 2005-11-28 2011-04-19 Alcatel Lucent Passive optical network media access controller assisted clock recovery
US7764886B2 (en) 2005-11-28 2010-07-27 Alcatel Lucent Burst mode optical receiver
WO2010031417A1 (fr) 2008-09-19 2010-03-25 Verigy (Singapore) Pte. Ltd. Unité de traitement de données et procédé de traitement de données
KR101421909B1 (ko) 2010-08-12 2014-07-22 어드밴테스트 (싱가포르) 피티이. 엘티디. 기준 스캔 체인 테스트 데이터를 생성하는 테스트 장치 및 테스트 시스템
JP6241156B2 (ja) * 2013-09-11 2017-12-06 株式会社ソシオネクスト 並列データを受信するために使用するクロックの位相を決定する方法、受信回路及び電子装置

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Also Published As

Publication number Publication date
FR2590425A1 (fr) 1987-05-22
GB2171577A (en) 1986-08-28
JPS6223647A (ja) 1987-01-31
GB2171577B (en) 1989-06-07
DE3604277C2 (de) 1996-06-05
AU586664B2 (en) 1989-07-20
DE3604277A1 (de) 1986-08-28
CA1256168A (fr) 1989-06-20
GB8603471D0 (en) 1986-03-19
AU5271186A (en) 1986-08-21
US4700347A (en) 1987-10-13

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Legal Events

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ST Notification of lapse