FR2636448B1 - Dispositif d'acquisition de donnees pour processeur - Google Patents

Dispositif d'acquisition de donnees pour processeur

Info

Publication number
FR2636448B1
FR2636448B1 FR8812037A FR8812037A FR2636448B1 FR 2636448 B1 FR2636448 B1 FR 2636448B1 FR 8812037 A FR8812037 A FR 8812037A FR 8812037 A FR8812037 A FR 8812037A FR 2636448 B1 FR2636448 B1 FR 2636448B1
Authority
FR
France
Prior art keywords
processor
data acquisition
acquisition device
data
acquisition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8812037A
Other languages
English (en)
Other versions
FR2636448A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR8812037A priority Critical patent/FR2636448B1/fr
Publication of FR2636448A1 publication Critical patent/FR2636448A1/fr
Application granted granted Critical
Publication of FR2636448B1 publication Critical patent/FR2636448B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
FR8812037A 1988-09-15 1988-09-15 Dispositif d'acquisition de donnees pour processeur Expired - Fee Related FR2636448B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8812037A FR2636448B1 (fr) 1988-09-15 1988-09-15 Dispositif d'acquisition de donnees pour processeur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8812037A FR2636448B1 (fr) 1988-09-15 1988-09-15 Dispositif d'acquisition de donnees pour processeur

Publications (2)

Publication Number Publication Date
FR2636448A1 FR2636448A1 (fr) 1990-03-16
FR2636448B1 true FR2636448B1 (fr) 1994-07-22

Family

ID=9370015

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8812037A Expired - Fee Related FR2636448B1 (fr) 1988-09-15 1988-09-15 Dispositif d'acquisition de donnees pour processeur

Country Status (1)

Country Link
FR (1) FR2636448B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2694426B1 (fr) * 1992-07-29 1994-09-30 Sgs Thomson Microelectronics Circuit d'interface, associé à un processeur pour échanger des données numériques en série avec un dispositif périphérique.
DE69300523T2 (de) * 1993-11-26 1996-03-14 Sgs Thomson Microelectronics Prozessorschnittstellenschaltung zum Austausch von seriellen digitalen Daten mit einem Peripheriegerät.
JPH10283088A (ja) * 1997-04-02 1998-10-23 Oki Electric Ind Co Ltd シリアル通信回路
US6779055B2 (en) * 2001-06-20 2004-08-17 Freescale Semiconductor, Inc. First-in, first-out memory system having both simultaneous and alternating data access and method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2517565C3 (de) * 1975-04-21 1978-10-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für ein Datenverarbeitungssystem
US4298954A (en) * 1979-04-30 1981-11-03 International Business Machines Corporation Alternating data buffers when one buffer is empty and another buffer is variably full of data
JPS5712470A (en) * 1980-06-25 1982-01-22 Nec Corp Information processor having buffer memory
US4847812A (en) * 1986-09-18 1989-07-11 Advanced Micro Devices FIFO memory device including circuit for generating flag signals

Also Published As

Publication number Publication date
FR2636448A1 (fr) 1990-03-16

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Legal Events

Date Code Title Description
TP Transmission of property
TP Transmission of property
ST Notification of lapse