FR2426977A1 - Circuit integre a forte densite d'integration et son procede de realisation - Google Patents

Circuit integre a forte densite d'integration et son procede de realisation

Info

Publication number
FR2426977A1
FR2426977A1 FR7913400A FR7913400A FR2426977A1 FR 2426977 A1 FR2426977 A1 FR 2426977A1 FR 7913400 A FR7913400 A FR 7913400A FR 7913400 A FR7913400 A FR 7913400A FR 2426977 A1 FR2426977 A1 FR 2426977A1
Authority
FR
France
Prior art keywords
integrated circuit
high integration
integration density
substrate
obtaining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7913400A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of FR2426977A1 publication Critical patent/FR2426977A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32105Oxidation of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41775Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783Raised source or drain electrodes self aligned with the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B20/00Read-only memory [ROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/141Self-alignment coat gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Circuit intégré à forte densité d'intégration et son obtention. Le procédé d'obtention applique des techniques de réalisation de grilles et de contacts auto-alignés de transistors à effet de champ et de lignes conductrices en Si polycristallin diffusées dans le substrat et aussi formées sur de l'oxyde de champ isolant formé sur le substrat. Les tolérances d'alignement des masques sont augmentées et rendues moins rigoureuses. L'utilisation dans les couches successives de matières à caractéristiques différentes de décapage permet, sans masquage, l'oxydation sélective des seules parties voulues et l'enlèvement discontinu d'une matière choisie. Application : réalisation de circuits intégrés de densité et de fiabilité accrues, contenant par exemple des transistors destinés à des mémoires vives ou mortes
FR7913400A 1978-05-26 1979-05-25 Circuit integre a forte densite d'integration et son procede de realisation Withdrawn FR2426977A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/909,886 US4277881A (en) 1978-05-26 1978-05-26 Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines

Publications (1)

Publication Number Publication Date
FR2426977A1 true FR2426977A1 (fr) 1979-12-21

Family

ID=25427983

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7913400A Withdrawn FR2426977A1 (fr) 1978-05-26 1979-05-25 Circuit integre a forte densite d'integration et son procede de realisation

Country Status (7)

Country Link
US (1) US4277881A (fr)
JP (1) JPS54155782A (fr)
DE (1) DE2921010A1 (fr)
FR (1) FR2426977A1 (fr)
GB (3) GB2106713B (fr)
IT (1) IT1117188B (fr)
NL (1) NL7904120A (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4587711A (en) * 1978-05-26 1986-05-13 Rockwell International Corporation Process for high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
DE3176909D1 (en) * 1980-03-06 1988-11-17 Toshiba Kk Semiconductor device using component insulation and method of manufacturing the same
US4317276A (en) * 1980-06-12 1982-03-02 Teletype Corporation Method of manufacturing an insulated gate field-effect transistor therefore in a silicon wafer
US4335502A (en) * 1980-10-01 1982-06-22 Standard Microsystems Corporation Method for manufacturing metal-oxide silicon devices
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
JPS58175846A (ja) * 1982-04-08 1983-10-15 Toshiba Corp 半導体装置の製造方法
CA1198226A (fr) * 1982-06-01 1985-12-17 Eliezer Kinsbron Methode de fabrication d'un dispositif semiconducteur
FR2548453B1 (fr) * 1983-06-30 1986-11-14 Thomson Csf Procede de fabrication d'un transistor a effet de champ a jonction vertical haute frequence
JPS6091673A (ja) * 1983-10-25 1985-05-23 Toshiba Corp 半導体装置の製造方法
US4584761A (en) * 1984-05-15 1986-04-29 Digital Equipment Corporation Integrated circuit chip processing techniques and integrated chip produced thereby
US4658496A (en) * 1984-11-29 1987-04-21 Siemens Aktiengesellschaft Method for manufacturing VLSI MOS-transistor circuits
JPS61150369A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
CA1258320A (fr) * 1985-04-01 1989-08-08 Madhukar B. Vora Petite cellule de memoire vive sans contacts
US5739569A (en) * 1991-05-15 1998-04-14 Texas Instruments Incorporated Non-volatile memory cell with oxide and nitride tunneling layers
US5384278A (en) * 1992-11-16 1995-01-24 United Technologies Corporation Tight control of resistor valves in a SRAM process
JP3653107B2 (ja) * 1994-03-14 2005-05-25 株式会社ルネサステクノロジ 半導体装置およびその製造方法
AU2050900A (en) 1998-12-28 2000-07-31 Fairchild Semiconductor Corporation Metal gate double diffusion mosfet with improved switching speed and reduced gate tunnel leakage
US7078296B2 (en) 2002-01-16 2006-07-18 Fairchild Semiconductor Corporation Self-aligned trench MOSFETs and methods for making the same
DE102006051490B4 (de) * 2006-10-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Technik zur Herstellung einer Passivierungsschicht ohne ein Abschlussmetall
TWI364798B (en) * 2008-03-21 2012-05-21 Vanguard Int Semiconduct Corp Semiconductor device and fabrication method thereof
US11276641B1 (en) * 2020-01-06 2022-03-15 Rockwell Collins, Inc. Conformal multi-plane material deposition

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3837935A (en) * 1971-05-28 1974-09-24 Fujitsu Ltd Semiconductor devices and method of manufacturing the same
JPS4859781A (fr) * 1971-11-25 1973-08-22
JPS50148084A (fr) * 1974-05-20 1975-11-27
US3899373A (en) * 1974-05-20 1975-08-12 Ibm Method for forming a field effect device
US3943542A (en) * 1974-11-06 1976-03-09 International Business Machines, Corporation High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same
US4021789A (en) * 1975-09-29 1977-05-03 International Business Machines Corporation Self-aligned integrated circuits
JPS605065B2 (ja) * 1976-01-30 1985-02-08 株式会社日立製作所 Mis形半導体装置の製造方法
US4151537A (en) * 1976-03-10 1979-04-24 Gte Laboratories Incorporated Gate electrode for MNOS semiconductor memory device
NL7604986A (nl) * 1976-05-11 1977-11-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting, en inrichting vervaardigd door toe- passing van de werkwijze.
JPS6041470B2 (ja) * 1976-06-15 1985-09-17 松下電器産業株式会社 半導体装置の製造方法
US4057820A (en) * 1976-06-29 1977-11-08 Westinghouse Electric Corporation Dual gate MNOS transistor

Also Published As

Publication number Publication date
GB2100926B (en) 1983-05-25
GB2021860A (en) 1979-12-05
NL7904120A (nl) 1979-11-28
GB2021860B (en) 1983-04-27
IT1117188B (it) 1986-02-17
GB2100926A (en) 1983-01-06
JPS54155782A (en) 1979-12-08
IT7949184A0 (it) 1979-05-25
GB2106713A (en) 1983-04-13
US4277881A (en) 1981-07-14
DE2921010A1 (de) 1979-11-29
GB2106713B (en) 1983-08-10

Similar Documents

Publication Publication Date Title
FR2426977A1 (fr) Circuit integre a forte densite d'integration et son procede de realisation
JPS55123157A (en) High-stability ion-injected resistor
CA2052970A1 (fr) Dispositif a supraconducteur comportant un canal d'oxyde supraconducteur extremement mince et methode de fabrication de ce dispositif
KR900001394B1 (en) Super high frequency intergrated circuit device
FR2387514A1 (fr) Dispositif semi-conducteur et son procede de fabrication
KR850000786A (ko) 반도체 장치 및 그 제조방법
JPS567462A (en) Semiconductor device and its manufacture
CA2054644A1 (fr) Dispositif a canal extremement court fait d'une couche d'oxyde supraconducteur extremement mince et sa methode de fabrication
DE3586047D1 (en) Duennfilmtransistor.
JPS57130473A (en) Mos type semiconductor memory storage
JPS57176757A (en) Semiconductor device
JPS57128957A (en) Semiconductor integrated circuit device and manufacture thereof
JPS5515230A (en) Semiconductor device and its manufacturing method
JPS5766671A (en) Semiconductor device
JPS57133667A (en) Manufacture of semiconductor device
KR910001889A (ko) 반도체장치
AU5330190A (en) Fermi threshold field effect transistor
JPS5693370A (en) Manufacture of mos-type semiconductor device
KR910005304A (ko) 싱글풀리 및 싱글메탈의 이피롬쎌 및 그 제조방법
JPS56105666A (en) Semiconductor memory device
JPS6463213A (en) High temperature superconductive material
JPS5577174A (en) Insulating gate-type electric field-effective semiconductor device
JPS57207373A (en) Manufacture of semiconductor device
SU1176774A1 (ru) Способ формирования диффузионных областей и контактов к ним
JPS5629361A (en) Manufacture of semiconductor integrated circuit

Legal Events

Date Code Title Description
ST Notification of lapse