JPS5577174A - Insulating gate-type electric field-effective semiconductor device - Google Patents
Insulating gate-type electric field-effective semiconductor deviceInfo
- Publication number
- JPS5577174A JPS5577174A JP15076478A JP15076478A JPS5577174A JP S5577174 A JPS5577174 A JP S5577174A JP 15076478 A JP15076478 A JP 15076478A JP 15076478 A JP15076478 A JP 15076478A JP S5577174 A JPS5577174 A JP S5577174A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- sio
- ion
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Volatile Memory (AREA)
Abstract
PURPOSE: To make high-speed operation possible and to improve integration performance, by forming FET's channel in substrate and also by burying source layer just under gate insulating film.
CONSTITUTION: An SiO2 film 36 is prepared by laminating an n-epitaxial-layer 32 on an n+-type Si 31, boring hole on an SiO2 film 33 with an Si3N4 film as a mask, injecting ion to form a p-layer 35 and oxidizing it. Holes are selectively opened on the films 34 and 33 to form a p-layer 38. The films 34 and 33 are removed to provide a gate oxide film 39, ion is injected to form a p-layer 40 and its concentration is made larger than that of the n-layer 32 and its depth-wise distribution is made to be almost equal to that of the layer 38. Ion is injected to form a n-layer 41, a p-layer 42 is laminated and activated by being heat-treated. When a poly Si 44 is laminated and a hole is bored in position of a prescribed distance L together with the film 39 and an n+-layer 43 is provided with a depth 1, a distance L-l becomes an effective channel length. It is then covered with an SiO2 film 45 to form electrodes 46, 47 and 48. As it is possible, in this mechanism, for carrier to travel in the substrate at high speed, it is possible to operate at high speed and to form an FET of high integration.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15076478A JPS5577174A (en) | 1978-12-05 | 1978-12-05 | Insulating gate-type electric field-effective semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15076478A JPS5577174A (en) | 1978-12-05 | 1978-12-05 | Insulating gate-type electric field-effective semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5577174A true JPS5577174A (en) | 1980-06-10 |
Family
ID=15503896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15076478A Pending JPS5577174A (en) | 1978-12-05 | 1978-12-05 | Insulating gate-type electric field-effective semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5577174A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100472A (en) * | 1980-01-16 | 1981-08-12 | Ricoh Co Ltd | Semiconductor device |
| US5231474A (en) * | 1986-03-21 | 1993-07-27 | Advanced Power Technology, Inc. | Semiconductor device with doped electrical breakdown control region |
-
1978
- 1978-12-05 JP JP15076478A patent/JPS5577174A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56100472A (en) * | 1980-01-16 | 1981-08-12 | Ricoh Co Ltd | Semiconductor device |
| US5231474A (en) * | 1986-03-21 | 1993-07-27 | Advanced Power Technology, Inc. | Semiconductor device with doped electrical breakdown control region |
| US5434095A (en) * | 1986-03-21 | 1995-07-18 | Sundstrand Corporation | Method for controlling electrical breakdown in semiconductor power devices |
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