JPS57113250A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57113250A
JPS57113250A JP18797280A JP18797280A JPS57113250A JP S57113250 A JPS57113250 A JP S57113250A JP 18797280 A JP18797280 A JP 18797280A JP 18797280 A JP18797280 A JP 18797280A JP S57113250 A JPS57113250 A JP S57113250A
Authority
JP
Japan
Prior art keywords
thermal oxide
oxide film
polysilicon
onto
oxygen barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18797280A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18797280A priority Critical patent/JPS57113250A/en
Publication of JPS57113250A publication Critical patent/JPS57113250A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To conduct complete insulation within groove width by disposing the first thermal oxide film into a groove, arranging an oxygen barrier film onto the thermal oxide film and disposing the second thermal oxide film onto the oxygen barrier film. CONSTITUTION:An N type epitaxial growth layer 2 is formed onto a P type silicon substrate 1. The grooves 4 are shaped using a photo-resist, etc. as amsks. Ions are implanted 9 into the grooves 4 for channel stopper, and the thermal oxide film 10 in SiO2, etc. is formed onto the surface containing the insides of the grooves 4. The oxygen barrier film 11 in Si3N4 is shaped onto the thermal oxide film 10. Polysilicon 12 is molded onto the oxygen barrier film 11. When the polysilicon 12 is oxidized, recesses 4a left in the grooves 4 are filled completely because the polysilicon is formed in the thickness approximately double the thickness of the polysilicon 12 on the oxygen barrier film 11. The polysilicon 12 is changed into the SiO2 13 of the thermal oxide film.
JP18797280A 1980-12-29 1980-12-29 Semiconductor device Pending JPS57113250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18797280A JPS57113250A (en) 1980-12-29 1980-12-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18797280A JPS57113250A (en) 1980-12-29 1980-12-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57113250A true JPS57113250A (en) 1982-07-14

Family

ID=16215362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18797280A Pending JPS57113250A (en) 1980-12-29 1980-12-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57113250A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500140A (en) * 1983-10-11 1986-01-23 アメリカン テレフオン アンド テレグラフ カムパニ− Semiconductor circuits including complementary metal-oxide-semiconductor devices
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate
JPH0685413B2 (en) * 1984-11-01 1994-10-26 エヌ・シー・アール・インターナショナル・インコーポレイテッド Method for forming insulating region on semiconductor substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61500140A (en) * 1983-10-11 1986-01-23 アメリカン テレフオン アンド テレグラフ カムパニ− Semiconductor circuits including complementary metal-oxide-semiconductor devices
JPH0685413B2 (en) * 1984-11-01 1994-10-26 エヌ・シー・アール・インターナショナル・インコーポレイテッド Method for forming insulating region on semiconductor substrate
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate

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