JPS5788772A - Vertical mis semiconductor device - Google Patents

Vertical mis semiconductor device

Info

Publication number
JPS5788772A
JPS5788772A JP55163273A JP16327380A JPS5788772A JP S5788772 A JPS5788772 A JP S5788772A JP 55163273 A JP55163273 A JP 55163273A JP 16327380 A JP16327380 A JP 16327380A JP S5788772 A JPS5788772 A JP S5788772A
Authority
JP
Japan
Prior art keywords
type
layer
designated
mask
type layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55163273A
Other languages
Japanese (ja)
Inventor
Hideshi Ito
Mitsuo Ito
Shigeo Otaka
Kazutoshi Ashikawa
Tetsuo Iijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55163273A priority Critical patent/JPS5788772A/en
Publication of JPS5788772A publication Critical patent/JPS5788772A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To equalize voltage current characteristic (grade resistance) in the forward and reverse directions of a vertical MISFET by a methd wherein when the depth directional resistance value of an n<-> type epitaxial layer in the directly under region A of a p type layer is designated as R1, and is designated as R2 in the part surrounded with the p type layer, the values thereof are selected as to satisfy the relation R1>=R2. CONSTITUTION:The p<+> type layer 3a is formed surrounding the n<-> type epitaxial layer 2 having thickness L2 on an n<3> type Si substrate 1. A polycrystalline Si mask 7 is provided on a gate oxide film 6, and B ions are implanted and heat treatment is performed to form p type channels 3b. A resist mask 11 is applied thereon, p ions are made to be diffused to form n<+> type layers 4, and the mask 11 is removed. An SiO2 film 12, an interlayer insulating film 13 are accumulated on the surface of the polycrystalline Si mask 7, an electrode 5 to short-circuit the n<+> type source 4 and the p<+> type layer 3a is formed, and an electrode 14 is fixed on the n<+> type substrate. The area on the surface of the n<-> type drain surrounded with the p type layer 3 is designated as S2, thickness of the n<-> type layer at the bottom part of the layer 3 is designated as I2, and when specific resistance in the zones A, B is uniform, by constituting the diffusion layer as to satisfy the relation L1/S1>=L2/S2, the vertical MISFET having the equal output characteristic in the forward and reverse directions can be obtained.
JP55163273A 1980-11-21 1980-11-21 Vertical mis semiconductor device Pending JPS5788772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163273A JPS5788772A (en) 1980-11-21 1980-11-21 Vertical mis semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163273A JPS5788772A (en) 1980-11-21 1980-11-21 Vertical mis semiconductor device

Publications (1)

Publication Number Publication Date
JPS5788772A true JPS5788772A (en) 1982-06-02

Family

ID=15770669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163273A Pending JPS5788772A (en) 1980-11-21 1980-11-21 Vertical mis semiconductor device

Country Status (1)

Country Link
JP (1) JPS5788772A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686551A (en) * 1982-11-27 1987-08-11 Nissan Motor Co., Ltd. MOS transistor
JPS62188374A (en) * 1986-02-14 1987-08-17 Fuji Electric Co Ltd Manufacture of insulated-gate field-effect transistor
US4803532A (en) * 1982-11-27 1989-02-07 Nissan Motor Co., Ltd. Vertical MOSFET having a proof structure against puncture due to breakdown
US4883767A (en) * 1986-12-05 1989-11-28 General Electric Company Method of fabricating self aligned semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686551A (en) * 1982-11-27 1987-08-11 Nissan Motor Co., Ltd. MOS transistor
US4803532A (en) * 1982-11-27 1989-02-07 Nissan Motor Co., Ltd. Vertical MOSFET having a proof structure against puncture due to breakdown
JPS62188374A (en) * 1986-02-14 1987-08-17 Fuji Electric Co Ltd Manufacture of insulated-gate field-effect transistor
US4883767A (en) * 1986-12-05 1989-11-28 General Electric Company Method of fabricating self aligned semiconductor devices

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