ES8702010A1 - Un sistema para el control de desvio durante el funcionamiento de un ordenador en una modalidad de canalizacion. - Google Patents

Un sistema para el control de desvio durante el funcionamiento de un ordenador en una modalidad de canalizacion.

Info

Publication number
ES8702010A1
ES8702010A1 ES540629A ES540629A ES8702010A1 ES 8702010 A1 ES8702010 A1 ES 8702010A1 ES 540629 A ES540629 A ES 540629A ES 540629 A ES540629 A ES 540629A ES 8702010 A1 ES8702010 A1 ES 8702010A1
Authority
ES
Spain
Prior art keywords
source data
computer
pipeline operation
instruction
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES540629A
Other languages
English (en)
Other versions
ES540629A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59034056A external-priority patent/JPS60178539A/ja
Priority claimed from JP3405784A external-priority patent/JPS60178540A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES540629A0 publication Critical patent/ES540629A0/es
Publication of ES8702010A1 publication Critical patent/ES8702010A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

SISTEMA PARA EL CONTROL DE DESVIO EN UN ORDENADOR. COMPRENDE: UN REGISTRO (1) DE INSTRUCCIOPNES; UN ARCHIVO (2) DE REGISTROS; UN CIRCUITO (3) DE COINCIDENCIAS; UNA PORCION DE DESCODIFICACION (41); UN REGISTRO (42) DE IDENTIFICADORES VALIDOS DE DESVIO; REGISTROS (51, 52, 53, 54, 55) DE RETENCION DE DIRECCIONES DE INSCRIPCION DE REGISTRO; UNA PORCION DE OPERACION DE INSCRIBIR (56); REGISTROS DE BASE (BR) (61), DE RETENCION DE DIRECION DE OPERANDO (WAR 1, 2) (62, 64), DE INDICE (XR) (63) Y DE DESPLAZAMIENTO (65); SELECTORES (66, 67); UN SUMADOR/RESTADOR (68) Y TRES PORCIONES DE INSTRUCCIONES (71, 72, 73) PARA TOMA DE DATOS DE INSTRUCCIONES DE UNA MEMORIA. TIENE APLICACIONES EN INDUSTRIAS DEDICADAS A LA FABRICACION DE ORDENADORES.
ES540629A 1984-02-24 1985-02-22 Un sistema para el control de desvio durante el funcionamiento de un ordenador en una modalidad de canalizacion. Expired ES8702010A1 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59034056A JPS60178539A (ja) 1984-02-24 1984-02-24 情報処理装置におけるバイパス制御方式
JP3405784A JPS60178540A (ja) 1984-02-24 1984-02-24 情報処理装置におけるバイパス制御方式

Publications (2)

Publication Number Publication Date
ES540629A0 ES540629A0 (es) 1986-12-01
ES8702010A1 true ES8702010A1 (es) 1986-12-01

Family

ID=26372848

Family Applications (1)

Application Number Title Priority Date Filing Date
ES540629A Expired ES8702010A1 (es) 1984-02-24 1985-02-22 Un sistema para el control de desvio durante el funcionamiento de un ordenador en una modalidad de canalizacion.

Country Status (7)

Country Link
US (1) US5043868A (es)
EP (1) EP0155211B1 (es)
AU (1) AU553416B2 (es)
BR (1) BR8500788A (es)
CA (1) CA1223371A (es)
DE (1) DE3587277T2 (es)
ES (1) ES8702010A1 (es)

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US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
JP2845578B2 (ja) * 1990-06-19 1999-01-13 甲府日本電気 株式会社 命令制御方式
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US5966514A (en) * 1995-05-31 1999-10-12 Matsushita Electric Industrial Co., Ltd. Microprocessor for supporting reduction of program codes in size
US5802346A (en) * 1995-06-02 1998-09-01 International Business Machines Corporation Method and system for minimizing the delay in executing branch-on-register instructions
US6092184A (en) * 1995-12-28 2000-07-18 Intel Corporation Parallel processing of pipelined instructions having register dependencies
US5778248A (en) * 1996-06-17 1998-07-07 Sun Microsystems, Inc. Fast microprocessor stage bypass logic enable
US5996065A (en) * 1997-03-31 1999-11-30 Intel Corporation Apparatus for bypassing intermediate results from a pipelined floating point unit to multiple successive instructions
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US7107302B1 (en) 1999-05-12 2006-09-12 Analog Devices, Inc. Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
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JP3445535B2 (ja) * 1999-09-24 2003-09-08 株式会社東芝 バイパス制御回路
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ATE529802T1 (de) * 2000-02-09 2011-11-15 Texas Instruments Inc Datenverarbeitungsvorrichtung
US6851044B1 (en) * 2000-02-16 2005-02-01 Koninklijke Philips Electronics N.V. System and method for eliminating write backs with buffer for exception processing
US6862677B1 (en) * 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
US6629234B1 (en) * 2000-03-30 2003-09-30 Ip. First, L.L.C. Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction
US6675287B1 (en) * 2000-04-07 2004-01-06 Ip-First, Llc Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
US20030154363A1 (en) * 2002-02-11 2003-08-14 Soltis Donald C. Stacked register aliasing in data hazard detection to reduce circuit
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US7100024B2 (en) * 2003-02-04 2006-08-29 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for generating early status flags
US7107438B2 (en) * 2003-02-04 2006-09-12 Via Technologies, Inc. Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions
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US8966230B2 (en) * 2009-09-30 2015-02-24 Intel Corporation Dynamic selection of execution stage
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Also Published As

Publication number Publication date
ES540629A0 (es) 1986-12-01
CA1223371A (en) 1987-06-23
AU553416B2 (en) 1986-07-17
DE3587277T2 (de) 1993-07-29
AU3867785A (en) 1985-09-05
BR8500788A (pt) 1985-10-08
EP0155211B1 (en) 1993-04-21
EP0155211A2 (en) 1985-09-18
EP0155211A3 (en) 1988-04-27
DE3587277D1 (de) 1993-05-27
US5043868A (en) 1991-08-27

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