SG97920A1 - Address wrap function for addressable memory devices - Google Patents

Address wrap function for addressable memory devices

Info

Publication number
SG97920A1
SG97920A1 SG200004493A SG200004493A SG97920A1 SG 97920 A1 SG97920 A1 SG 97920A1 SG 200004493 A SG200004493 A SG 200004493A SG 200004493 A SG200004493 A SG 200004493A SG 97920 A1 SG97920 A1 SG 97920A1
Authority
SG
Singapore
Prior art keywords
memory devices
addressable memory
wrap function
address wrap
address
Prior art date
Application number
SG200004493A
Inventor
Paul William Coteus
Brian Li Ji
Toshiaki Kirihata
John Michael Ross
William Wu Shen
Paul William Hovis
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG97920A1 publication Critical patent/SG97920A1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
SG200004493A 1999-10-18 2000-08-14 Address wrap function for addressable memory devices SG97920A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US41959499A 1999-10-18 1999-10-18

Publications (1)

Publication Number Publication Date
SG97920A1 true SG97920A1 (en) 2003-08-20

Family

ID=23662922

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200004493A SG97920A1 (en) 1999-10-18 2000-08-14 Address wrap function for addressable memory devices

Country Status (4)

Country Link
JP (1) JP2001176269A (en)
KR (1) KR100373419B1 (en)
CN (2) CN1163832C (en)
SG (1) SG97920A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505686B1 (en) * 2003-05-26 2005-08-03 삼성전자주식회사 System and method of testing plurality of DUTs in parallel mode
US7783917B2 (en) * 2007-02-26 2010-08-24 International Business Machines Corporation Selection of data arrays
CN108267682B (en) * 2016-12-30 2020-07-28 杭州广立微电子有限公司 High-density test chip, test system and test method thereof
CN113360430B (en) * 2021-06-22 2022-09-09 中国科学技术大学 Dynamic random access memory system communication architecture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0155211A2 (en) * 1984-02-24 1985-09-18 Fujitsu Limited System for by-pass control in pipeline operation of computer
US5307324A (en) * 1992-02-03 1994-04-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including address transition detecting circuit
US5651002A (en) * 1995-07-12 1997-07-22 3Com Corporation Internetworking device with enhanced packet header translation and memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1012268B (en) * 1984-05-18 1991-04-03 盐野义制药株式会社 Synthesis of acrylic acid derivatives
US5014327A (en) * 1987-06-15 1991-05-07 Digital Equipment Corporation Parallel associative memory having improved selection and decision mechanisms for recognizing and sorting relevant patterns
WO1995028677A1 (en) * 1994-04-13 1995-10-26 Ericsson Inc. Efficient addressing of large memories

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0155211A2 (en) * 1984-02-24 1985-09-18 Fujitsu Limited System for by-pass control in pipeline operation of computer
US5307324A (en) * 1992-02-03 1994-04-26 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including address transition detecting circuit
US5651002A (en) * 1995-07-12 1997-07-22 3Com Corporation Internetworking device with enhanced packet header translation and memory

Also Published As

Publication number Publication date
CN1536491A (en) 2004-10-13
KR100373419B1 (en) 2003-02-25
KR20010050968A (en) 2001-06-25
CN100533405C (en) 2009-08-26
JP2001176269A (en) 2001-06-29
CN1293402A (en) 2001-05-02
CN1163832C (en) 2004-08-25

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