AU7342300A - Dynamic memory caching - Google Patents

Dynamic memory caching

Info

Publication number
AU7342300A
AU7342300A AU73423/00A AU7342300A AU7342300A AU 7342300 A AU7342300 A AU 7342300A AU 73423/00 A AU73423/00 A AU 73423/00A AU 7342300 A AU7342300 A AU 7342300A AU 7342300 A AU7342300 A AU 7342300A
Authority
AU
Australia
Prior art keywords
dynamic memory
memory caching
caching
dynamic
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU73423/00A
Inventor
Walter E. Croft
Alex E. Henderson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fast Chip Inc
Original Assignee
Fast Chip Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fast Chip Inc filed Critical Fast Chip Inc
Publication of AU7342300A publication Critical patent/AU7342300A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU73423/00A 1999-09-07 2000-09-01 Dynamic memory caching Abandoned AU7342300A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15268099P 1999-09-07 1999-09-07
US60152680 1999-09-07
PCT/US2000/024078 WO2001018653A1 (en) 1999-09-07 2000-09-01 Dynamic memory caching

Publications (1)

Publication Number Publication Date
AU7342300A true AU7342300A (en) 2001-04-10

Family

ID=22543939

Family Applications (1)

Application Number Title Priority Date Filing Date
AU73423/00A Abandoned AU7342300A (en) 1999-09-07 2000-09-01 Dynamic memory caching

Country Status (3)

Country Link
EP (1) EP1222546A1 (en)
AU (1) AU7342300A (en)
WO (1) WO2001018653A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859868B2 (en) * 2002-02-07 2005-02-22 Sun Microsystems, Inc. Object addressed memory hierarchy
US11119915B2 (en) 2018-02-08 2021-09-14 Samsung Electronics Co., Ltd. Dynamic memory mapping for neural networks

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396614A (en) * 1992-06-25 1995-03-07 Sun Microsystems, Inc. Method and apparatus for a secure protocol for virtual memory managers that use memory objects
US5442766A (en) * 1992-10-09 1995-08-15 International Business Machines Corporation Method and system for distributed instruction address translation in a multiscalar data processing system
US5729710A (en) * 1994-06-22 1998-03-17 International Business Machines Corporation Method and apparatus for management of mapped and unmapped regions of memory in a microkernel data processing system

Also Published As

Publication number Publication date
WO2001018653A1 (en) 2001-03-15
WO2001018653A9 (en) 2002-09-12
EP1222546A1 (en) 2002-07-17

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase