CN100533405C - Address volume connection function for addressable storage equipment - Google Patents

Abstract

To provide a selectable function which makes the address portion of data words separable and enables the address portion to be used for a different purpose without disturbing the contents stored in a memory array. A memory assembly which has an input port 242, an output port 216, and the memory array 23 containing a plurality of addressable storing positions in one mode contains the selectable function which sends the address information portion 212 of data which appear in a data route to other processing routes 770 and 771 by by-passing the memory array 232 without disturbing the information stored at the addressable storing positions.

Description

The address reeling connection function of addressable storage equipment

Patented claim of the present invention is that application number is 00127014.1, and the applying date is on September 14th, 2000, and denomination of invention is divided an application for the application for a patent for invention of " address reeling connection function of addressable storage equipment ".

Draw is the provisional application series number of submitting on October 20th, 1,998 60/104,889 for reference herein.

Technical field

The present invention relates to the reeling connection function relevant that provide available with the addressable random access memory, this storer does not disturb the memory element content for additional the use with the address portion cigarette of data, and relate to a kind of special command or Functional Capability particularly, be used for optionally walking around the storage area of memory set component and prepare against parallel the application by address portion.

Background technology

In many data processing operations, the form of handling that information had is increment or word, and they carry adding up part and who prepares storage and are used to notify storage array where to deposit its identification division.Along with development of technology, array becomes huge, internal affairs handle and control circuit very complicated, and the information of depositing not only greatly but also valuable.These arrays have some problems always for a long time, for example speed that always increases and big or small environment and test, with regularly reach and the relation of parts between drifting about.Because memory array is made up of the addressable element that is fitted into SIC (semiconductor integrated circuit), accessibility and performance constraint seriously limit the increase of q﹠r maintenance test and other abilities.

Expect when technical development that in future the dynamic addressable array of equipment is in the validation operation of receiver address information rightly, and when input or pounce on the technology of delivering a letter that will utilize the requirement adjustment in the timing when obtaining data.Also wish or when parts drift abouts or when addressable device for a long time need not the back finds to cause timing to change owing to temperature or change in voltage, can be periodically again with the timing initialization.

Need a kind of technology of exploitation, can safeguard at the individual storage elements place of array and rebulid condition and do not distort the information that is stored in the array.

Summary of the invention

The present invention is an optional function, but the address portion of permission data word can separate from the memory contents part and this address portion can be used for various objectives and do not disturb the content of depositing in the storage array.The present invention can regard a command functions as, allow among the zone of total storage array and between development for example address, impedance calibration, regularly and the error in the project such as parts drift carry out signal analysis.

The technology that an advanced person's test addressing is arranged, one of them storage unit is the controller that can directly deliver to the data terminal of unit and send the unit back to of the information on the address bus of semiconductor integrated unit for example, so as comparison controller the information that sends on the address wire with can judge whether any fault is arranged but do not disturb the content of depositing in the storage array on address wire or data line in the information that receives on the data line.

The advanced technology part is the modification of data in response to optional array circuit, wherein the storage area of array isolated and for this generic operation for example regularly, confirmation and the drift-corrected purpose of parts reselect the address portion of data route and redefine function.

Now set forth the principle of the storage system of the Synchronous Dynamic Random Access Memory that uses the foundation of double data rate (DDR) (SDRAM-DDR) unit.

According to the present invention, a kind of addressable random access memory of demarcation of the impedance that can improve described driver element is provided, described addressable random access memory has a plurality of data array groups of arranging according to row and row, and, described addressable random access memory different command provide in the cycle read with write signal to described data array group, and described read with write signal under the control of the decoding circuit of described row by multipath conversion to common data bus, and has each driving element of described group, described addressable random access memory also comprises: a device, be used for providing one to adjust signal in the cycle at write order, can be used for forbidding from the extremely input of described array group of described common data bus, and the circuit of described write command signal and described row disconnected, a device, be used for sending the impedance Control vector signal to each described driving element, so that indicating at least, amplitude changes and existing impedance state is satisfied with one of them, and device, be used on described common data bus producing the impedance Control instruction and send described instruction to described impedance Control vector dispensing device, described Instruction Selection changes or wherein in the satisfied list value to existing impedance state from described amplitude.

According to the present invention, the method of the impedance of demarcating the driving element that is used to drive the read and write operation is provided in a kind of addressable random access memory, described addressable random access memory has a plurality of data array groups of arranging according to row and row, and, described addressable random access memory different command provide in the cycle read with write signal to described data array group, and described read with write signal under the control of described decoding circuit by multipath conversion to common data bus, and has each driving element of described group, said method comprising the steps of: provide one to adjust signal in the cycle at write order, can be used for forbidding from the extremely input of described array group of described common data bus, and the circuit of described write command signal and described row disconnected, send the impedance Control vector signal to each described driving element, so that indicating at least, amplitude changes and existing impedance state is satisfied with one of them, and generation impedance Control instruction on described common data bus, described Instruction Selection is from described amplitude variation with to wherein one in the list value of existing impedance state satisfaction, and the described instruction of transmission is to each described driving element.

According to the present invention, a kind of demarcation addressable random access memory that can improve the impedance of described driver element is provided, described addressable random access memory has a plurality of data array groups of arranging according to row and row, different command provide in the cycle read with write signal to described group and multipath conversion to common data bus and have each driving element of described group, described addressable random access memory also comprises: a device, be used for providing to each described driving element in the cycle and adjust upward and adjust downwards signal at write order, for use in provide to each described driver element clock as the impedance Control vector signal that latch with input decoding, be used to indicate at least that amplitude changes and to existing impedance state satisfied one of them.

Description of drawings

Fig. 1-9 sets forth when the address signal passes through addressable storage array, the application of the principle of the invention in the address signal globality is analyzed; Wherein: Fig. 1-6 sets forth will belong to the selected node that reference number of the present invention is given standard in the prior art addressable storage systems, wherein:

Fig. 1 sets forth the basic addressing storage cell in for example two online component of a typical components, SIC (semiconductor integrated circuit) for example, and the terminals that will be referred in elaboration of the present invention are all given reference number.

Fig. 2 A, B set forth the interconnect function unit of double data rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM-DDR) in the prior art, and wherein reference number is given and belonged to unit of the present invention.

Fig. 3 sets forth the function truth table among the prior art SDRAM-DDR described in Fig. 2 A, B.

Fig. 4 A-D sets forth the sub-portfolio part of the dual-memory group SDRAM-DDR of type shown in Fig. 1-3 or the layout on the card, wherein adds reference number and belongs to the present invention.

Fig. 5 A-E sets forth the schematic diagram of the prior art dual-memory group SDRAM-DDR of type shown in Fig. 1-4, wherein adds reference number and belongs to the present invention.

Fig. 6 sets forth shown in Fig. 1-5 layout of SDRAM-DDR type of storage card in the prior art computer system, and wherein add reference number and belong to the present invention, and wherein:

Fig. 7-the 9th is used to set forth structure, flow process and the sequential chart that bypass of the present invention is implemented, wherein:

Fig. 7 A, B set forth the interior bypass circuit ability of functional diagram of Fig. 2 A, B, are used for transfer address and FPDP information, and wherein reference number belongs to the present invention.

Fig. 8 sets forth information flow of the present invention in the computer system of Fig. 6 for example, and wherein reference number belongs to the present invention, and,

Fig. 9 uses the system performance of sequential chart elaboration when system is in the reeling connection function of the present invention or the functional mode that echoes, and wherein reference number belongs to the present invention.

Figure 10-13 sets forth the principle of the invention and is applied to that used standardized component is the impedance Control of Ocd driver in prior art dynamic RAM (DRAM) subassembly; Wherein:

Figure 10 sets forth the typical DRAM data routing that is used for write data by subassembly.

Figure 11 is illustrated as the layout of implementing the principle of the invention and being additional to the adjustment in typical as shown in Figure 10 write data path.

Figure 12 is a sequential chart that is used to set forth the additional adjustment effect of Figure 11.

Figure 13 is illustrated as the enforcement principle of the invention and is additional to another layout of the adjustment in typical data path as shown in Figure 10.

Figure 14-16 elaboration principle of the invention is applied to the appraisal of sequential in the DRAM storage sets component and the route of reselecting of control is implemented, wherein:

Figure 14 is a block diagram that is used for setting forth the typical timing controlled data routing of DRAM subassembly.

Figure 15 is set forth in the sequential calibration and implements the principle of the invention, is additional to the layout of the adjustment of the data routing of type as shown in Figure 14, and,

Figure 16 is a sequential chart that is used for setting forth the condition that the timing that is additional to the adjustment in typical data path as shown in Figure 15 produces.

Embodiment

Can be for example additional by hardware with a lot of modes, software instruction and their combination implement optional function of the present invention, but thereby so that allow the address portion of data separately be used for different purposes with this address portion from the memory contents part.These embodiment are divided into wherein some groups and some groups of wherein storage array being isolated with the storage array bypass, and again address date are selected route and be used for other purposes.Memory content is interference-free in these two kinds of groups.The present invention can see an order or reeling connection function as, is used for analyzing, confirm and proofreaies and correct for example variation of address, sequential, impedance variation and parts drift and do not disturb the actual data content of depositing in the storage sets component in the addressable storage subassembly of these data routings.The storage sets component is interweaved by storage and controlled entity and forms.An exemplary dynamic random access memory (DRAM) of setting forth in Fig. 1-6 is made up of parts, data routing and control that the prior art component standard that is combined on card or the plate is made up.Analyze the important kind of data routing thereby the present invention aims to provide ability and do not disturb the data that may be stored in the storer with providing correction in appropriate boundary, to keep mutual relationship.

Referring to figs. 1 through 6, Fig. 1 sets forth the basic addressing storage cell in for example two online component of a typical components, SIC (semiconductor integrated circuit) for example, and the terminals that will be referred in elaboration of the present invention are all given reference number.Among Fig. 1, the SIC (semiconductor integrated circuit) unit be marked with 101 and all signal ends all list.Address end A0-A12 is arranged, be marked with 102, be used for by row with by the column access memory contents.Selecting side group BA0-BA1 is arranged, be marked with 103, be used to visit 4 internal storage groups, order end RAS, CAS, WE and CS are marked with 104, and they correspond respectively to row address, column address, allow to write with chip and select.There is a differential clock CLK CLK/ right, is marked with 105, be used to make the interior operation of chip synchronous, and allow clock end CLE to be marked with 106, be used for allowing and forbidding clock work with system clock.Show 4,8 or 16 data port DQ0-DQ15 among Fig. 1, they depend on the data width of chip, and data strobe UDQS, LDQS are marked with 107, and each is used for 8 data bit.FPDP is used to send the READ information data or receives the WRITE information data.These gatings are driven by reading and receive operational data, as time clock feature, data are arranged all at the rising edge of strobe pulse with above the negative edge.Also be useful on the power end VDD and the VSS of internal circuit and be used for data and the I/O power end VDDQ and the VSSQ of gating end, and a reference voltage end Vref who is used to receive data.

Fig. 1 and Fig. 2 A, B set forth the interconnect function unit of double data rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM-DDR) in the prior art together, wherein reference number is given and is belonged to unit of the present invention, and an addressable semiconductor equipment with address and FPDP is described together, it is important data routing position when the analysis address right is spent.

The functional diagram of the critical piece of video RAM among Fig. 2 A, the B (RAM) equipment.In Fig. 2 A, B, clock is marked with (202), and it is used for the address (being marked with 206) and the memory pool address (being marked with 204) of receiver address register (being marked with 212) in this example.In timing register (being marked with 205), receive clock (202) and chip select command (being marked with 201) and ras, cas and we order (being marked with 203) together.The clock signal that is postponed by delay-locked loop (being marked with 208) is used for driving data gating generator (being marked with 214), is used for making the output data of the read operation by output buffers (being marked with 216) synchronous, so that clock and output data homophase.

Timing register (205) is used to judge that address bus (being marked with 210) is to point to row cache (being marked with 218) still to point to row buffer memory (being marked with 220).For example, it is low selecting (201) as fruit chip, and the ras of (203) memory set operation or row then will occur and select for low and cas are high; Select (201) low as fruit chip, then read or write or column selection occurring for the ras and the cas both of low and (203).

Fig. 3 set forth be used among the DRAM condition of indicating the function truth table.

Be back to Fig. 2 A, B, under the condition of selecting row row decoder (being marked with 222) with row address decoding, the delegation in the 13 bit address position specified data arrays (being marked with 232) in 8192 possible row.Show 4 possibility arrays in Fig. 2 A, the B example, will determine by memory set selector switch (being marked with 224) for one of desired startup.

A major issue relevant with the problem to be solved in the present invention is that even accuracy is scarcely arranged herein, it is effective for execution and at memory device that all address informations will comprise enough information.Therefore, if in receiver address, occur owing to for example set up the equipment (Memory Controller among Fig. 6 for example of address, to illustrate later on) and memory device between the path connect to interrupt and the error that causes, then Chuan Shu data will send or receive and are difficult to find error.

Be back to Fig. 2 A, B again, in case selected delegation, then select maybe some row of this row of desirable row, then the data in the row buffer memory are sent to column decoder (being marked with 226), the latter selects the desired data position from last sensing amplifier (234).Because this is a double-data rate memory, this means that mainly each DQ port will transmit two data bit in each clock period, must pick up two data bit in array 232 in each clock period then.As at first exporting any two positions, depend on 2 the pre-pickup unit of row (being marked with 236), it checks low level column address CAO (being marked with 238).CAO (238) also selects to route to data input-buffer (being marked with 242), and the latter receives data from DQ end (being marked with 250) in write operation, and decision should interior two of receiving of clock period be delivered to appropriate address.

Aspect adress analysis of the present invention, the effect of CAO (238) is important, and this shows that it is a position, and its positional information is used for the data division of chip.In the present invention, target is the data division that as much as possible all addresses and command information is brought to chip, so that the information that receives on address and order wire can be sent data line, thereby make Memory Controller check whether address and the order of delivering to addressable device have in fact correctly received by the check data line.The present invention can not influence the perhaps normal running of addressable device in the RAM, because the invention provides an independent bus.

Continuation, is delivered to output buffers (being marked with 216) and is exported FPDP DQ to and (250) from the data of the pre-pickup unit of 2 row (236) in read operation with reference to Fig. 2 A, B.Meanwhile, data strobe UDQS and LDQS are driven at the place, unit that is marked with (214).Receiving equipment can use to be deposited the identical mode of data with RAM and uses these gatings.When timing register control is by I/O control module (being marked with 252) driving data.Data are driven as train of impulses, and the unit that is marked with (262) determines when that train of impulses is over and done with and signals to output buffers.Periodicity between reading order and the data (stand-by period) can be programmed for the length of train of impulses, can be selected rightly to enter order cke, cs, ras, cas and the we of timing register (205) and is used a special command (mode register is write) to programme by Memory Controller or other external units; Itself is contained in order in the address field.Therefore be marked with 210 address path also directional beacon with the mode register of (272), it when initialization, will instruct decoding and in other things definite burst length and stand-by period.

The present invention utilizes a mode register and provides a special command so that address bus is guided to data bus for storer when possibility, in other words, so that finish address reeling connection function.

Also can be in other equipment provide the identical address reeling connection function and without mode register by programming.

Be back to Fig. 2 A, B, similarly, if prepare data are write RAM, then the data pilot that will be received by input-buffer (242) is to the selected row and column of array (being marked with 232).Data strobe UDQS and LDQS are used for gated data, also, deposit data and deposit second data at negative edge from receiver at the rising edge place of gating, therefore obtain double data rate (DDR).

For mentioned problem, it is effective that all addresses seem equally again.If the error that appearance causes owing to the interruption of the connection between the equipment of for example setting up the address (for example Memory Controller of being discussed among Fig. 6) and the memory device in receiver address, the data of then preparing to deposit in storer still write, but the write error address.This may rewrite original correct data, thereby causes serious consequence in many computing machines.

Might be with certain data mask or obstruction and they are write, in fact in some early stage memory device, certain data mask can not be able to be read, can not write again.In the present invention, by using shielding end UDM and LDM (being marked with 207) to realize masking operation.UDM at port DQ0-7 place shielded signal, does not allow them write array at port DQ8-15 place's shielded signal and LDM.By generating iDM signal (being marked with 282) by timing register (205) and introducing in the I/O control (252) and come complete operation.

With reference to Fig. 3, Fig. 3 sets forth the function truth table among the typical SDRAM-DDR of prior art as Fig. 2 A, B described in, described in this SDRAM-DDR such as Fig. 2 A, the B and show can be by the order for the foundation of SDRAM-DDR memory device of utility command cke, cs, ras, cas, We and dm and address.The read and write order had been discussed above, and other orders are not critical to the present invention, show just for completeness herein.

Fig. 4 A-D sets forth the sub-portfolio part of the dual-memory group SDRAM-DDR of type shown in Fig. 1-3 or the layout on the card, and wherein the additional reference numeral belongs to the present invention.The layout of Fig. 4 A-D is 8 two online memory modules (DIMM) that typical 128 megabyte (MB) 184 ends are deposited, its use 18,64MB (megabit) SDRAM-DDR equipment (being marked with 402).This 64MB equipment is very similar to standard 256MB equipment, and just capacity is 1/4, and therefore the address wire that relates to is few two.DIMM is shown as the example of the set of an addressable device with public address bus.Also have many about not relating to of the present invention here or not influencing the card structure of ability of the present invention.These abilities are to drive function (being marked with 412) again.Be presented at the data switch (being marked with 422) at the back side in addition, when a plurality of DIMM shared a common data bus, this class data switch was used for the memory device on this DIMM and other DIMM are separated.Whether the existence of these data switches is to address reeling connection order did not influence of the present invention.Some card structure has little EEPROM (being marked with 432), and it comprises the descriptive information about DIMM.Whether the existence of this EEPROM is to address reeling connection order did not influence of the present invention.

Fig. 5 A-E sets forth the front and the two set of memory device of the typical case on the back side of blocking shown in Fig. 4 A-D and how to link together.With reference to Fig. 5 A-E, SDRAM-DDR equipment is marked with (502), and address register is marked with (512), and data switch is marked with (522).The address bus of all RAM is all shared.Also have, in 9 RAM of the DIMM front of Fig. 4 A-D and 9 RAM shared data buses at the DIMM back side.

The layout of SDRAM-DDR type of storage card in the prior art typical computer system shown in the displayed map 1-5 wherein adds reference number and belongs to the present invention in Fig. 6.

With reference to Fig. 6, wherein show the storer of computer system and the high-level schematic diagram of processor part.One or more herein processors are called microprocessor and are marked with (610).This processor is connected to Memory Controller (being marked with 620).In some structure, processor may be in the identical semiconductor integrated circuit apparatus with Memory Controller.The service processor that is marked with (630) is used to provide this class function, for example system initialization and Error processing.Same service processor can exist with processor, or the service processor function can be the part of processor design.In this discussion, processor and service processor are differentiated so that explain data that enter storer in using address reeling connection function of the present invention and the data that are present in the storer.Memory Controller control addressable storage equipment (being marked with 640), it can be as the SDRAM-DDR memory device among Fig. 1 and 2, on the storage card that is marked with (650), be used typical element in the industry in the case, described their example in conjunction with Fig. 4 A-D and 5.Memory Controller (620) receives (reading) or sends (writing) data by data bus (being marked with 660).These controls are told RAM to pass through cntrl/address bus (being marked with 670) and are read or write.When may being connected to each DIMM or DRAM or they, independent data bus and cntrl/address bus can use reeling connection function of the present invention when public.

Now in industry generally with address, order and data reference clock all.This clock can be from independent chip, is used for all parts synchronously, perhaps realizes clock is sent (source Synchronization Design) with address, order and data under the situation of SDRAM-DDR or other high-speed equipments in industry.Memory Controller in Fig. 6 (620) has independent clock bus (being marked with 680).For the present invention, how regularly unimportant, importantly when address reeling connection occurring, it must follow with normal running in identical timing.

In the system of describing in Fig. 1-6 some problem is arranged, they are solved by additional command ability provided by the invention.

A problem is when all addresses of storer all include effective information but exist some fault for example to break in as the storage sets component, just all information all can't be included.Therefore be difficult to know whether an address receives rightly.When bus speed increased, this problem was more obvious.In the prior art, be used for the test storage subassembly to judge that scheme that whether receive rightly the address is to read and write certain data pattern by the diverse location place at RAM alternately, but this needs mass data to transmit to finish it, and has destroyed memory content.There are a lot of reasons not wish to destroy memory content.According to the present invention, a kind of device that is used for the test address bus is provided, it is fast, and the nondestructive storage content.

Another problem is the demand for development of the technology technology of delivering a letter, and this relates to when sending or pounce on the timing adjustment that obtains data.In system shown in Fig. 6, the speed of address and data bus may be very high, thereby all require more strict with respect to the data strobe that the detailed clock of address/command regularly reaches with respect to data.Wish and periodically these buses to be reinitialized.

For for a long time need not and high-speed DRAM or other addressable storage subassemblies reused because temperature or change in voltage regularly may change.Wishing has a kind of device, can rebulid timing relationship between addressable device and opertaing device and reference-to storage not.

According to the present invention, be called the additional modes function that address reeling connection or address echoes and address these problems by providing, as shown in Figure 6, can under the control of Memory Controller or service processor, conduct interviews.The echo purpose of ability of address reeling connection of the present invention or address provides output terminal is directly delivered in the address information bypass, and evaluates at this place and disturbance storage content not.

Below be an illustrative embodiment.A method of control function provides the mode register that addressable device is given in an order, for example element 272 shown in Fig. 2 A, the B.Synchronous dram uses a mode register, and clock double synchronous dram (SDRAM-DDR) have a mode register be a element 272 among Fig. 2 A, the B and an expansion mode register both, i.e. known (EMR) that in Fig. 2 A, B, do not show separately in the technology.Explicit address end A4 among Fig. 1.Pattern position A4 among the EMR of SDRAM-DDR is available, is the non-address pattern that echoes when assignment 0, and is the address pattern that echoes when assignment 1.With reference to Fig. 7 A, B, wherein set forth the bypass circuit ability that is used for transfer address and FPDP information in the functional diagram of Fig. 2 A, B, wherein reference number belongs to the present invention.An address serial device (being marked with 770) is obtained address information and directly it is sent to output buffers 216 on passage (being marked with 771) among Fig. 7 A, the B in address register 212, and an order serializer (being marked with 780) self-timing register 205 is obtained command information and upward it is sent to output buffers 216 at passage (being marked with 781).

With reference to Fig. 8, wherein set forth information flow of the present invention in the computer system of Fig. 6 for example, wherein information path (being marked with 880) is obtained control signal and is delivered on the card 650 among the DRAM 640 selected one from Memory Controller 620, and obtains OPADD information and deliver to unshowned appraisal position in the output buffers of selected DRAM.With reference to Fig. 9, wherein set forth the sequential chart of the system performance when system is in the reeling connection function of the present invention or the functional mode that echoes.Later several cycles on address on the address/command bus and the order video data bus.Do not have new signal.At n+2 in the cycle, as in cycle n for DRAM, all DQ on assembly the same side bring out and send out, and read the address and the control end that are positioned on assembly the same side serially.Its order is the end ascending order for the signal that is positioned at assembly one side, then is the end descending at the assembly opposite side.Series read-out should be identical with the frequency of reading of data, and follow the standard of identical transmission and retention time, uses the identical drivers impedance.Finish in (16 the possible data) series read-out afterwards of 8 cycles, and the forbidden data drive operation.Can obtain a newer command after the one-period.The method is designed to provide from the address of data line output and the value of control line, and whether mate with the address that receives (or control) address (or control) that permission opertaing device sensing sends.If there is difference, then or address wire be bad, perhaps data line is bad.Available more sophisticated functions is determined difference, for example changes the order that read the address every one-period.Certainly also have additive method and reach various objectives.For example all address wires that latch in cycle n can be exported by all data lines in the cycle at n+2.Similarly, different cycles number (1,2,3 etc.) can be arranged between the output of address latch and data.

For for simplicity, make the echo timing of function of address of the present invention regularly identical in the preferred embodiment with normally reading of memory module.This is best for controller and RAM, because it has kept natural timing for normal read-write.The address can serialization, and exports as the series flow in one or more data line.All methods all produce information needed.Also promptly, will be from the value of data line OPADD and control line, whether mate with the address that receives (or control) address (or control) that permission opertaing device sensing sends.If there is difference, then or address wire be bad, perhaps data line is bad.Available more sophisticated functions is determined difference, for example changes the order that read the address every one-period.Available low speed writes EMR so that be increased in chance of success in the high speed address wire problem incident.When some line in the line that requires to test need be write EMR, this test was incomplete.Yet the failure itself when entering the address and echoing pattern just indicates the address wire failure.

Calling an echo choosing of function of address of the present invention as SDRAM-DDR function truth table with reference to Fig. 3 for method, wherein has the position can define a newer command.For example, may require auto-precharge end A10 and train of impulses to cease and desist order one is used from and sets up a newer command.When A10 when low, train of impulses is ceased and desisted order and same work in the past, but when it when being high, this means newer command, function echoes for address reeling connection promptly of the present invention or address.When given this newer command, all addresses and order all cigarette to data.

Two these available immediately newer command The Application of Technology are arranged.

First is the test address bus.In memory tester or independent computer system, write the copy of the mode register of an alternate device, and controller or tester are programmed so that the address of the address of Qu Donging and reception relatively.If they do not meet, then there is fault.This test is very fast, and it is the disturbance storage content not, therefore can at any time finish.

Second is to adjust the timing of subassembly to allow the high-speed cruising of address and data bus.In memory tester or independent computer system, write the copy of the mode register of an alternate device, and controller or tester are programmed so that the address of the address of Qu Donging and reception relatively.If data correctly receive, then this may be that the contact of breaking or it may be because the not optimization of timing relationship between address and the clock (or data and gating).For example in SDRAM-DDR, controller must be with data strobe and the data pulse centrally aligned that in phase drives with data, so that become insensitive to variation regularly.But the position of knowing the data pulse center is very difficult.Controller can scan this gating by the time with respect to data, and notices, it is because gating too early reads failure is owing to gating is too late that data send failure.This test requiredly all just requires controller to know data pattern to be read.Therefore, echo or reeling connection function allows to send in analyzing and confirming and reads any data pattern then and disturbance storage content not in address of the present invention.

The performance of the dynamic RAM in data handling system (DRAM) proceeds to higher frequency, go into and transfer out for the reliable transmission of each independent DRAM in the DRAM subassembly that guarantee to form the storage sets component, the accurate control that data input in the storage system subassembly and data are exported just becomes key.Be included in the accurate control is the ability that is used for adjusting the impedance of the driver that the array data are moved.Driver is independent unit, is called Ocd driver (OCD) in technology.

For demarcating driving force and the impedance of OCD, can take the DC current measurement, when OCD when driving known logic state load, with the impedance adjustment until obtaining required I-V characteristic.Yet for finishing this generic operation, Memory Controller must be set up a required logic state for the OCD load, will adjust instruction notification DRAM then.Now set forth this situation in conjunction with Figure 10-15, they are set forth the principle of the invention and are used for the OCD impedance Control, and wherein Figure 10 sets forth the typical DRAM data routing that is used for write data.Figure among Figure 10 sets forth the main project in the write operation.This concrete DRAM has 4 independently data array groups, has the read/write data bus communication passage that is used to be marked with the RWD data.Data multiplex on the RWD is converted to array.During write order, the RW switch places DRAM the state that receives and store data.Data input to the (OCR﹠amp that is marked with of DRAM by the outer receiver of DQ chip; DQSYNC) position, and may be synchronous with data strobe (being marked with DQS).Under the situation of picking up type of architecture in advance, wherein latch some positions of serial data in the cycle concurrently at continuous clock, can in traffic pilot (being marked with WRITE MUX), write down these data if desired.In either case, data all are urged on the bidirectional bus (being marked with RWD), and deposit memory array at last under the control of row control and decoding circuit.

In Figure 11, set forth the write data path of DRAM, wherein comprise the path of write data shown in Figure 10 feature and and it operate in the same manner, in addition also in dotted border elaboration be used to provide the feature of the demarcation and the control of Ocd driver impedance.With reference to Figure 11, the DRAM control circuit is provided with order and generates an additional control signal (being marked with ADJUST) in response to the mode register from Memory Controller.When the ADJUST order was worked, RWD bus and data array group disconnected, thereby suppressed the write order to row.In other words, because inaccurate storage array receives and the storage data, so any data in the storage array are all interference-free.Therefore, when ADJUST order is worked, can as normal write data are written on the RWD bus, but data can not be stored in the storage array.Obviously, if storage array does not comprise and do not wish the data disturbed when finishing impedance calibration, then do not need to arrange forbidden storage.The ADJUST order also allows to receive programming instruction the additional data of control (being marked with OCDIMPEDANCE CONTROL) circuit on the RWD bus.Use the write order control signal will control regularly with the delay version of signal.OCDIMPEDANCE CONTROL element is explained this programming instruction and is generated to be used to drive the vector of OCD and they are set and draws and drop-down level to needs.Set forth the example of Management Information Base and setting thereof in the table 1.

Table 1

DQ＜2〉DQ＜1〉DQ＜0〉order

What is not done for X 00

001 increase pull-down impedance

010 reduce pull-down impedance

011 are reset to the acquiescence impedance with drop-down

Draw impedance in 101 increases

Draw impedance in 110 minimizings

111 will on draw and be reset to the acquiescence impedance

Therefore, when the ADJUST signal works, the data of an available normal write from the DQ input end the OCD impedance is programmed.

With reference to Figure 12, provide the sequential chart of the timing example that is used to show this operation.Write command signal is marked with PCAS on figure, the row order is marked with CCAS.The standard of four write data train of impulses architecture in the sequential chart supposition prior art of Figure 12.Only first from the train of impulses of the subclass of n DQ is used for programming information.Choosing generation ground, the continuous position in the train of impulses also may comprise programming information.

It below is the example protocol of describing in conjunction with Figure 11 that is used to finish the impedance adjustment.

The extended mode register collection starts the ADJUST pattern.

The ADJUST mode signal RWD MUX is placed high impedance mode and forbid to row write order.

The ADJUST mode signal has also been prepared the OCD impedance control circuit and has been adjusted instruction for use in receiving.

Single write order is pounced on and is obtained DQ and they are urged on the RWD.

DQ＜0:n〉go up train of impulses first comprise impedance adjustment order.It in the table 1 example of command list.

Another option is to utilize the RWD bus that vector impedance directly is written to each OCD circuit so that transfer data to all OCD and be in this value of storage in the latch register at each OCD.This requirement makes clock and mode signal PCAS and ADJUST be distributed to each OCD circuit.Because existing RWD bus can be used for transferring data to all OCD, therefore no longer need be from the vector bus of OCD impedance Control, thus save wiring space.

Figure 13 is illustrated as another choosing of the adjustment of implementing the principle of the invention and being additional to a DQ circuit in the typical as shown in Figure 10 write data path for layout.With reference to Figure 13, this layout does not relate to the RWD bus fully, and allows each OCD to programme independently.Relate to two programming mode signals in the layout of Figure 13, one is marked with (ADJUST_PU), is used to adjust draw on the OCD and another is marked with (ADJUST_PD), is used to adjust drop-down.Can by a mode register order be set at different time and start each.When any one pattern starts, as setting forth in conjunction with Figure 11 in the past, with the write operation that suppresses array.

During the write order to DRAM, serial data receives and is stored in abreast DQ WRITE LATCH place by the outer receiver (OCR) of chip at each DQ place.The serial pulses string length is 4.In common write order, abreast data are write storage array by the RWD bus, but ADJUST_PU or the prevention of ADJUST_PD pattern are done like this.On the contrary, data directly deposit in and are arranged near the latch register of OCD.These data comprise draws or drop-down required resistance value, and they are decoded then so that select required OCD impedance.

Therefore when ADJUST_PU or ADJUST_PD signal enabling, available normal write is with OCD impedance programming, and wherein resistance value is provided in the DQ input with the serial pulses string mode.Should be noted that each OCD receives resistance value from one only one DQ, thereby allow independently different OCD to be programmed.The use that it shall yet further be noted that the method is to 4 digit pulse string length and unrestricted.

It below is the example protocol of describing in conjunction with Figure 13 that is used to finish the impedance adjustment.

The extended mode register collection starts ADJUST_PU or PD pattern.

ADJUST_PU or PD mode signal RWD MUX is placed high impedance mode and forbid to row write order.

One 4 digit pulse string is written to writing in the latch register of each DQ, as normal write.

Between DQ and WRTCLK sync period, 4 digit pulse strings transfer to draw or pull-down impedance latch register and demoder in.

The extended mode register collection stops ADJUST_PU or PD pattern.

Memory Controller is finished impedance measurement.

Above process repeats until finishing adjustment.

When using the principle of the invention, finish valuable help to timing relationship control.Because the DRAM performance is pushed to higher frequency, be the reliability that guarantees data, just become key for the accurate control of the data of input and output storage system.The most important thing is to be adjusted at the ability of the timing skew that occurs in the system in the influential each side.

Wish system to be placed a kind of state, wherein known data stream is the output quantity from OCD so that Memory Controller can operation technique in the vernier type measurement of standard adjust regularly skew.Wish that also data stream can be flexibly to operating many different pieces of information sequences.Such situation is arranged, promptly before demarcating, mustn't write data to DRAM, therefore do not allow the option that reads simply and write data to array.

With reference to Figure 14-16, they set forth appraisal and the control that the principle of the invention is applied to timing in the DRAM storage sets component.Figure 14 sets forth typical data routing in the DRAM subassembly.This concrete DRAM has 4 data array group, on its read/write data (RWD) multipath conversion to a common data bus.During read operation, signal PCAS pulse is low, and the column address that is provided by Memory Controller simultaneously appears on the inner COLADD bus.At the column access of array in the time, prepare by the OCD output data to the DQ bus and drive the RWD bus.Pick up in advance in the architecture, these data are at first used the in addition serialization of input and output pointer at FIFO latch register place.If the COLADD bus did not guarantee before finishing read cycle, then must keep start address to be used to generate output pointer when needs.

With reference to Figure 15, it is illustrated as the enforcement principle of the invention and is additional to the layout of the adjustment of data routing as shown in Figure 14, an additional control signal that is marked with ALIGN is arranged, and it is provided with order by the DRAM control circuit in response to the mode register from Memory Controller and generates.When the ALIGN signal was worked, RWD bus and data array group disconnected and are connected to the DATA bus by three condition control.Provide data to the DATA bus by the COLADD bus.This allows to use the data-driven RWD bus from the COLADD bus during normal read operation.Because data array group and RWD bus disconnect, so column decoder does not need COLADD information.Therefore can finish any amount of continuous read operation, so that OCD exports any complex data sequence to the DQ bus.

Therefore notice that the COLADD bus may be not so good as the total live width of RWD, need a fan-out so that the data of reproducting bus on all.In addition, the FANOUT function may be decoded the DATA bus message so that produce different complicated vectors.An example is also to be used to drive the complement code of DATA bus so that contiguous OCD drives complementary data.Can use more COLADD position in addition so that allow each read operation that a plurality of vectors of only one are arranged.Choosing generation ground can only require that an OCD subclass is used for demarcating, and will not be set to known state by all RWD lines in the case.

Figure 14 and 15 is used to set forth one and has 4 synchronous drams that pick up in advance with 4 fixed pulse string length.Under the situation of picking up in advance, must use a counter, so that send data from DATA HOLD at the appropriate time less than burst length.Should be noted that, when using start address DQADD and decoding function (for example FANOUT) to come together pulse series data resequenced, can allow to reduce the DATA highway width.For example, as long as make train of impulses simply, can use six patterns 0000,0001,0011,0101,0111 and 1111 to produce ten other 4 possible bit patterns from different addresses.Choosing generation ground can force DQADD to be in a known state by the AL1GN signal, and use those COLADD positions that are used as start address that DATA is provided bus on the contrary.

With reference to Figure 16, it is a sequential chart that is used for setting forth the condition that the timing that is additional to the adjustment in typical data path as shown in Figure 15 produces.

The agreement that vernier type is aimed at is as follows:

The extended mode register collection drives the ALIGN mode signal.

The ALIGN mode signal places high impedance mode and driver A control RWD with RWD MUX.

May be thereupon with any amount of normal CAS reading order.In this pattern, COLADD＜0,1〉determine start address and COLADD＜2:5〉provide data for 4 digit pulse strings.

The extended mode register collection is forbidden the ALIGN mode signal.

There are some observations to have and help determine option.

The driver A of the had three-state among Figure 15 can be little, and visit has whole row because they are for RWD.

Use inner CAS order (PCAS) latch address information.

FANOUT is used for 4 digit pulse strings are distributed to many group four RWD groups among Figure 15.

When the ALIGN mode signal is set up DQADD＜0,1 with given value〉time, COLADD＜0:1〉can be used as the front two of four digit pulse strings.

COLADD＜0:1〉can be decoded so that select in two predefine pulse string modes one,

FANOUT can be used for generating true and complementary data so that contiguous DQ can be in the opposite direction in switching.

Multiple row address COLADD＜6:9 for example more〉can be used for producing a plurality of only one 4 digit pulse string sequences.

What described is a kind of control function that is used for the dynamic random access memory array, it can optionally walk around the storer of depositing and allow address portion with data to disperse and be used for analysis, confirmation and internal control.Can reselect route by the selectivity of additional structure and existing structure and realize this control function.

Claims (3)

1. the addressable random access memory of the demarcation of the impedance that can improve driver element, described addressable random access memory has a plurality of data array groups of arranging according to row and row, and, described addressable random access memory different command provide in the cycle read with write signal to described data array group, and described read with write signal under the control of the decoding circuit of described row by multipath conversion to common data bus, and have driver element corresponding to each described data array group, described addressable random access memory also comprises:

A device is used for providing one to adjust signal in the cycle at write order, and can be used for forbidding from the extremely input of described array group of described common data bus, and the circuit of described write command signal and described row is disconnected,

A device is used for sending the impedance Control vector signal to each described driver element, so as to indicate at least that amplitude changes and to existing impedance state satisfied one of them, and

A device, be used for producing the impedance Control instruction and send the device of described instruction to described transmission impedance Control vector signal on described common data bus, described Instruction Selection is from described amplitude variation or to having wherein in the satisfied list value of impedance state now.

2. the method for the impedance of addressable random access memory acceptance of the bid fixed driver element, described addressable random access memory has a plurality of data array groups of arranging according to row and row, and, described addressable random access memory different command provide in the cycle read with write signal to described data array group, and described read with write signal under the control of decoding circuit by multipath conversion to common data bus, and have driver element corresponding to each described data array group, said method comprising the steps of:

Provide one to adjust signal in cycle at write order, can be used for forbidding, and the circuit of described write command signal and described row is disconnected from the extremely input of described array group of described common data bus,

Send the impedance Control vector signal to each described driver element, so as to indicate at least that amplitude changes and to existing impedance state satisfied one of them, and

Produce and send the impedance Control instruction on described common data bus, described Instruction Selection is from described amplitude variation with to having wherein in the satisfied list value of impedance state now.

3. the demarcation addressable random access memory that can improve the impedance of driver element, described addressable random access memory has a plurality of data array groups of arranging according to row and row, different command provide in the cycle read with write signal to described group and multipath conversion to common data bus and have driver element corresponding to each described data array group, described addressable random access memory also comprises:

A device, be used for providing to each described driver element in the cycle and adjust upward and adjust downwards signal at write order, for use in provide to each described driver element clock as the impedance Control vector signal that latch with input decoding, be used to indicate at least that amplitude changes and to existing impedance state satisfied one of them.

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