CN113360430B

CN113360430B - Dynamic random access memory system communication architecture

Info

Publication number: CN113360430B
Application number: CN202110690605.8A
Authority: CN
Inventors: 杜海涛; 康一
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2021-06-22
Filing date: 2021-06-22
Publication date: 2022-09-09
Anticipated expiration: 2041-06-22
Also published as: CN113360430A

Abstract

The invention provides a dynamic random access memory system communication structure based on double rate synchronous dynamic random memory standard, comprising: the phase shifter comprises a dynamic random access memory chip set, a data input and output switch circuit and a memory controller, wherein the data input and output switch circuit is a switch array used for controlling the directions of a data input and output selection signal and a data input and output signal of each dynamic random access memory chip in the dynamic random access memory chip set, and the switch array is used for adjusting the phase shifter; the memory controller is used for independently controlling each dynamic random access memory chip through different chip selection signals so as to realize the movement of data from the reading operation of a source address dynamic random access memory chip to the writing operation of a target address dynamic random access memory chip; the memory controller is used for controlling the switch array of the data input and output switch circuit so as to establish data paths among different chips.

Description

Dynamic random access memory system communication architecture

Technical Field

The present invention relates to the field of communications, and more particularly, to a Dynamic Random Access Memory (DRAM) system communication architecture based on the double data rate synchronous dynamic random access memory (DDR) standard.

Background

With the advent of the big data, artificial intelligence era, the storage and movement of data is gradually becoming a bottleneck of existing computing systems. The communication between the memory and the CPU is mainly mediated by a long board-level bus, which may cause huge delay and energy overhead, and in some special scenarios, such as fork system call, mysql (relational database management system), and shell script, there are a lot of data copying and initialization zeroing operations.

At present, for the operation of data copying, moving, initializing, clearing, and the like, as shown in fig. 1, a LOAD instruction is generally executed by a CPU, a read request is sent to a memory controller mc (memory controller) to read data from a source address into a CPU register, and then the STORE instruction is executed to return the data to a memory destination address through a board-level data bus. However, in this scenario, the CPU does not process data, but is equivalent to a data handler, which wastes limited board-level bus bandwidth and energy, occupies CPU resources, and aggravates the memory and CPU "memory wall" problem.

Disclosure of Invention

In view of the above, the present invention provides a dram system communication architecture, which is based on the ddr sdram standard, does not require any modification to the existing dram chips, and can implement parallel data communication, thereby significantly improving the efficiency of inter-chip communication of the dram system with less hardware overhead and reducing energy consumption.

In order to achieve the above object, the present invention provides a dram system communication architecture, the system communication architecture is based on the ddr sdram standard, and the system communication architecture includes: the dynamic random access memory comprises a dynamic random access memory chip set, a data input and output switch circuit and a memory controller, wherein the data input and output switch circuit is a switch array used for controlling the directions of a data input and output selection signal and a data input and output signal of each dynamic random access memory chip in the dynamic random access memory chip set, and the switch array is used for adjusting a phase shifter so as to adjust the phase of the data input and output selection signal and the phase of the data input and output signal in the writing state of the dynamic random access memory; the memory controller is used for independently controlling each dynamic random access memory chip through different chip selection signals so as to realize the movement of data from the reading operation of a source address dynamic random access memory chip to the writing operation of a target address dynamic random access memory chip; the memory controller is used for controlling the switch array of the data input/output switch circuit so as to establish a data path between different dynamic random access memory chips.

According to an embodiment of the present invention, the system communication architecture further comprises: and the peripheral circuit part comprises a chip selection signal decoder which is convenient for the memory controller to control different dynamic random access memory chips.

According to an embodiment of the present invention, the data input/output switch circuit is used for establishing a data path from the memory controller to the dynamic random access memory chip and a data path of data input/output signals between the dynamic random access memory chips.

According to an embodiment of the present invention, the phase shifter is disposed inside the data input/output switch circuit and is used for connecting the data input/output selection signal ports of the two dram chips, so that the data input/output selection signal port of the read chip is shifted by 90 ° in phase and then is sent to the data input/output selection signal port of the write chip as an input signal.

According to an embodiment of the present invention, the dram chip in the dram chipset includes one of: DDR2, DDR3, DDR4, wherein DDR characterizes double rate synchronous dynamic random access memory.

According to an embodiment of the present invention, the operation mode in which the memory controller supports data movement between the dynamic random access memory chips comprises: setting a read delay RL and a write delay WL through a configuration mode register at the initialization stage of the double-rate synchronous dynamic random access memory, and enabling the RL to be equal to WL + 1; the dynamic random access memory chip C1 receives a first activation command and a row address where source data are located, which are sent by a memory controller; the dynamic random access memory chip C2 receives a second activation command sent by the memory controller and a corresponding line of a destination address; when the dynamic random access memory chip C1 meets the first preset time sequence parameter, receiving a read command and a source data target column sent by a memory controller; when the dynamic random access memory chip C2 meets the second preset time sequence parameter, receiving a write command and a corresponding column of a destination address sent by a memory controller; after the burst length BL is preset, the above steps are repeated to realize a seamless read operation of the dram chip C1 to a seamless write operation of the dram chip C2.

According to an embodiment of the present invention, the manner in which the data path is used to implement data movement includes: within the dram chipset, each dram chip implements parallel data movement without resource conflicts.

According to an embodiment of the present invention, the manner in which the data path is used to implement data movement includes: under the condition that the driving capability of the data input/output selection signal and the data input/output signal of each dynamic random access memory chip meets the preset condition, the data read by one dynamic random access memory chip is utilized to drive at least two dynamic random access memory chips, and one-to-many multiple data movement is realized.

According to an embodiment of the present invention, the manner in which the data path is used to implement data movement further includes: in the same channel between the dynamic random access memory chip sets, the data read from one dynamic random access memory chip set drives the other dynamic random access memory chip set to realize data movement.

According to an embodiment of the present invention, wherein the moving of data from a source address dynamic random access memory chip read operation to a target address dynamic random access memory chip write operation is realized comprises: reading operation from the source address dynamic random access memory chip satisfies the edge alignment of the data input/output selection signal and the data input/output signal in the source address dynamic random access memory chip; the target address dynamic random access memory chip write operation satisfies the center alignment of the data input output selection signal and the data input output signal in the target address dynamic random access memory chip.

According to the embodiment of the invention, based on the double-rate synchronous dynamic random access memory standard, the data input and output switch circuit of the communication architecture of the dynamic random access memory system is utilized to establish a data path from a memory controller to the dynamic random access memory and establish a data path of data input and output signals among chips of the dynamic random access memory, so that the hardware overhead is reduced, a large amount of data transfer is realized with higher bus utilization rate under the condition of smaller hardware overhead, and the communication architecture of the dynamic random access memory system has the advantages of high efficiency, low energy consumption, low cost and the like.

Drawings

FIG. 1 is a diagram illustrating a prior art DRAM system implementing inter-chip data migration;

FIG. 2 is a diagram of a DRAM system communication architecture according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a read operation based on the DDR SDRAM standard;

FIG. 4 is a timing diagram of a write operation based on the double-rate SDRAM standard;

fig. 5(a) is a schematic diagram illustrating a data input/output principle in a system architecture according to an embodiment of the present invention;

FIG. 5(b) is a schematic diagram of a phase shifter circuit in the system architecture according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a system architecture memory controller according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings in combination with the embodiments.

The present invention provides a Dynamic Random Access Memory (DRAM) system communication architecture based on the double data rate synchronous dynamic random access memory (DDR) standard, for example, fig. 2 is a schematic diagram of a DRAM system communication architecture according to an embodiment of the present invention.

As shown in fig. 2, the system communication architecture includes: the device comprises a dynamic random access memory chip set (DRAM Rank), a data input and output switch (DS) circuit and a Memory Controller (MC). The following describes each part of the system architecture in detail.

A dynamic random access memory Chip set (DRAM Rank) is a DRAM Chip part, namely RxCy which represents Chip y on Rank x, wherein x and y represent numerical subscripts. The DRAM chip may include, but is not limited to, one of the following: DDR2, DDR3, and DDR4 are not particularly limited as long as they are applied to the DRAM chip of the present invention.

According to an embodiment of the present invention, a Dynamic Random Access Memory (DRAM) operates by giving it 4 input ports: the chip select signal CS #, the row address strobe RAS #, the column address strobe CAS #, and the read-write signal WE # input corresponding high and low levels, thereby controlling the operations of DRAM such as activation, read/write, precharge, refresh, etc.

According to the embodiment of the invention, the communication architecture of the DRAM system provided by the invention is based on a double data rate synchronous dynamic random access memory (DDR) standard, and by taking read-write operation of DDR4 as an example, a timing diagram of a read process and a write process of the DDR standard is briefly described. It should be noted that DDR4 is taken as an example for the DRAM chip, and is not intended to limit the scope of the present invention, as long as the DRAM chip suitable for the system communication architecture of the present invention is within the scope of the present invention.

Fig. 3 is a timing diagram of a read operation based on the specification of the double rate synchronous dynamic random access memory standard.

As shown in fig. 3, when the DRAM is in an idle state, first an ACT command is sent to activate a corresponding row, and then a READ (READ) command and a corresponding column address are sent, and as can be seen from fig. 2, data starts to be output from a data input output (DQ) signal port after waiting for a READ delay (RL) of 11, when a data input output Select (DQs) signal is taken as a strobe signal for the DQs, which corresponds to a DQ valid signal. At this time, DQS and DQS satisfy edge alignment, DQ and DQS are I/O (input/output) bidirectional ports, and DQ and DQS are driven by an internal circuit of a DRAM chip in a read process, which is equivalent to an output port.

FIG. 4 is a timing diagram of a write operation based on the double-rate SDRAM standard.

As shown in fig. 4, when the DRAM is in an idle state, an ACT command is first sent to activate a corresponding row, then a WRITE (WRITE) command and a corresponding column address are sent, and after waiting for a WRITE Latency (WL) to be 9, data starts to be input into the DRAM chip from a DQ signal port, where DQs serves as a strobe signal for DQ, which corresponds to a DQ valid signal. At this time, DQS and DQ meet the center alignment, DQ and DQS are driven by an external circuit in the writing process, which is equivalent to the DRAM input port.

The data input output switch (DS) circuit is a switch array for controlling the direction of a data input output select (DQS) signal and a data input output (DQ) signal for each Dynamic Random Access Memory (DRAM) chip in a DRAM Rank of a DRAM chipset, the switch array for adjusting a phase shifter to adjust a data input output select (DQS) signal phase and a data input output (DQ) signal phase for a DRAM write state.

In accordance with an embodiment of the present invention, the DS circuit is the core of the overall system communication architecture of the present invention, which is essentially a DRAM DQ bus crossbar for establishing the data path from the Memory Controller (MC) to the Dynamic Random Access Memory (DRAM) chip and the data path for data input/output (DQ) signals between the Dynamic Random Access Memory (DRAM) chips. The function is simple, the realization is not complex, and the hardware expense brought by the method is small.

For example, fig. 5(a) is a schematic diagram of a data input/output principle in a system architecture according to an embodiment of the present invention; fig. 5(b) is a schematic diagram of a phase shifter circuit in the system architecture according to an embodiment of the present invention.

As shown in fig. 5(a), the DS circuit principle is illustrated on a 2 × 2 scale, and may include data path bidirectional switches K1, K2 and Kx, Ky. The DS circuit mainly includes two parts: its path to DQS changes and its path to DQ changes. The path change is done by the bidirectional switches K1, K2 and Kx, Ky, where the bidirectional switches K1, K2 and Kx, Ky are controlled by the memory controller MC.

As shown in fig. 5(a), in the related art, during a normal CPU access to the DRAM, the switches Kx and K1 constitute a pair of switches both turned up so that DQSx and DQS1 are connected and DQx and DQ1 are connected; accordingly, switches Ky and K2 form a pair of switches that are both turned down such that DQSy is connected to DQS2 and DQy is connected to DQ2, thereby forming a conventional DRAM system communication architecture (as shown in fig. 1).

According to the embodiment of the invention, in the operating mode of fast moving data between chips, for example, if a part of data in the DRAM chip C1 needs to be copied to the chip C2, DQ1 and DQ2 are data buses of two chips respectively, then at this time, DQ1 should be an output signal of C1 driven by an internal circuit of C1, DQ2 is an input signal of C2 driven by an external circuit, and C2 is responsible for sampling and writing memory cells therein. In this mode of operation, the DS needs to complete the connection of DQS1 to DQS2, DQ1, and DQ 2.

As shown in fig. 5(a) -5 (b), the DS completing the connection of DQS1 and DQS2, DQ1 and DQ2 includes: the switches K1 and K2 are controlled by the memory controller MC to connect DQS1 to DQS2, to connect DQ1 to DQ2, and to enable the Phase shifter between DQS.

The mode of operation of the present invention differs from the conventional mode in that the phase shifter needs to be enabled, according to an embodiment of the present invention. As can be seen from the read and write timing diagrams of DDR4 shown in fig. 2-3, in order to increase the reliability of sampled DQ signals on the receiving side in DRAM read and write operations, the DQs and DQ signals for read and write operations are aligned differently by 90 °, so that a phase shifter is needed to shift the phase of the DQs signals from C1 to C2. Fig. 5(b) is a possible phase shifting circuit.

According to an embodiment of the present invention, a phase shifter is disposed inside a data input output switch (DS) circuit for connecting data input output select (DQS) signal ports of two dynamic random access memory DRAM chips, so that the data input output select (DQS) signal port of a write chip is provided as an input signal to the data input output select (DQS) signal port of the write chip after the phase of the DQS signal is shifted by 90 °.

It should be noted that the 2 × 2 scale in fig. 5(a) is only an exemplary illustration, and the DS can be extended to support more DRAM chip interconnect structures.

A Memory Controller (MC) for independently controlling each DRAM chip by different chip select signals (CS #) to effect a movement of data from a source address DRAM chip read operation to a target address DRAM chip write operation; a switch array for controlling a data input output switch (DS) circuit to establish a data path between different DRAM chips.

According to the embodiment of the invention, a Memory Controller (MC) part is mainly an extension of the existing DRAM memory controller to support a new inter-chip data transfer DRAM architecture, and is mainly changed in a control mode of a DRAM chip selection signal CS #.

According to the embodiment of the invention, in the conventional DRAM system communication architecture, one DRAM Rank is controlled by the same CS #, for example, under the condition that the data bit width of a DDR4 DQ bus is 16, one Rank consists of 4 DRAM chips, so that the data bus bit width of one DRAM channel is 64 bits, and chip selection signals of the 4 DRAM chips are the same CS #; however, in the DRAM architecture supporting the new inter-chip data transfer according to the present invention, the read/write status of each DRAM chip needs to be controlled separately, and therefore, the chip select signal CS # of each DRAM chip needs to be separated.

The working mode of the Memory Controller (MC) for supporting the data movement between DRAM chips comprises the following steps:

setting a read delay (RL) and a write delay (WL) by a configuration Mode Register (MR) at a double-rate synchronous dynamic random access memory (DDR) initialization stage, wherein RL is equal to WL + 1;

the dynamic random access memory DRAM chip C1 receives a first activation command and a row address where source data are located, which are sent by a Memory Controller (MC);

the DRAM chip C2 receives a second activation command and a corresponding row of a destination address sent by a Memory Controller (MC);

when the dynamic random access memory DRAM chip C1 meets a first preset time sequence parameter, receiving a read command and a source data target column sent by a Memory Controller (MC);

when the dynamic random access memory DRAM chip C2 meets a second preset time sequence parameter, receiving a write command and a corresponding column of a destination address sent by a Memory Controller (MC);

after the Burst Length (BL) value is preset, the above steps are repeated to achieve a seamless read operation from the DRAM chip C1 to a seamless write operation from the DRAM chip C2.

The control flow of the memory controller MC is described in detail below with reference to an embodiment, but the embodiment is only for illustration and is not intended to limit the invention.

As shown in FIG. 6, CMD1, ADDR1, DQS1 and DQ1 in FIG. 6 represent port signals of DRAM chip C1, respectively, and CMD2, ADDR2, DQS2 and DQ2 represent port signals of DRAM chip C2, respectively. RL, Read Latency, represents the time interval from the receipt of a Read command from the DRAM to the sending of data by the DRAM to the output port driving the DQ data bus, more precisely the time interval from the memory controller MC sending a Read command to the DRAM to bring it into a Read state until the MC can Read the first data on the DQ. Accordingly, WL represents the time interval between the DRAM receiving a write command and the MC driving DQ placing the first data to be written on the bus. In the DDR standard, both RL and WL can set the corresponding mode register MR to determine when the DDR is initialized.

Referring to fig. 6, the following describes the data transfer between DRAM chips according to the present invention, assuming that the memory controller MC needs to transfer data from the 1 st column (Col 1) and the 2 nd column (Col 2) chips in the 1 st Row (Row1) of the DRAM chip C1 to the x (Col x) th column and the y (Col y) th column in the 2 nd Row (Row2) of the DRAM chip C2 with a burst length BL of 8. The control flow of the MC is as follows:

a) at edge 2, C1 receives the ACT Row1 command from the memory controller MC, activating the data source Row address.

b) At edge 4, C2 receives the ACT Row2 command sent by the MC, activating the destination address Row address.

c) At edge 8, C1 satisfies the timing parameter tRCD and receives the READ Col 1 command sent by the MC, and after a delay of RL ═ 11, the first READ data D0 will be output from DQ 1. The timing parameter tRCD represents the delay from the row address strobe to the column address strobe.

d) On the 10 th edge, C2 meets the timing parameter tRCD and receives a WRITE Colx command sent by the MC, and after a delay of WL ═ 10, the first data D0 to be written will be input from DQ 2.

e) At edge 12, the MC sends READ Col 2 to C1, which is exactly 4 edges in time since the last READ Col 1 command sent to C1, so that a seamless READ operation can be achieved.

f) At edge 14, the MC sends a WRITE Col y to C2, which is exactly 4 edges in time since the last WRITE Col x command sent to C2, so that a seamless WRITE operation can be achieved.

g) At edge 18, the 1 st data from the read operation of C1 at this time is output from DQ1, directly connecting the output of DQ1 to the input of DQ 2. By shifting the DQ1 phase back by 90 ° to the DQS2 input through the phase shifter, edge alignment of DQS1 and DQ1 from the C1 read operation translates to center alignment of DQS2 and DQ2 signals to the C2 write operation input.

According to the embodiment of the invention, through setting the delay parameters of proper RL and WL (namely, making RL be WL +1) in the initial DDR stage, seamless read-to-seamless write operation of C2 can be realized for C1, and the utilization rate of DQ data bus can be at the highest value all the time.

According to the embodiment of the present invention, in the data transfer process, the data path composed of the DS can support the following situations of bulk data transfer:

a. in the DRAM Rank interior, each DRAM chip implements parallel data movement without resource conflicts. Specifically, operations in Rank can be performed according to the above operation flow, and because the isolation action of the DS between ranks can make data movement of the operations complete inside Rank, for example, data movement operations inside Rank x and Rank y do not affect each other, which means that the data movement operations inside Rank can completely perform Rank-level parallel operations.

b. Under the condition that the driving capability of a data input/output selection (DQS) signal and a data input/output (DQ) signal of each DRAM chip meets preset conditions, data read by one DRAM chip of the DRAM drives at least two DRAM chips to realize one-to-many data movement. Specifically, under the condition that the driving capability of DQS and DQ signals of one DRAM chip is enough, the memory controller MC can control the switch array of the DS, and data read out by one DRAM chip drives a plurality of DRAM chips, so that one-to-many multi-time data copying is realized, namely, multicast operation is completed by using a DQ data bus, the efficiency of data transfer among the DRAM chips can be greatly increased, and the utilization rate of limited DQ bandwidth is improved.

c. In the same channel between the DRAM Rank of the dynamic random access memory chip sets, the data read from one DRAM Rank of the dynamic random access memory chip sets is driven to the other DRAM Rank of the dynamic random access memory chip sets, and the data movement is realized. Specifically, if data shifting occurs between different ranks in the same channel, Rank x may also be set to a read state and Rank y may be set to a write state by the above method, and a suitable DS switch direction is selected to allow read data of Rank x to directly drive Rank y, but at this time, since a shared channel DQ bus is occupied, parallel data shifting operations cannot be implemented.

According to an embodiment of the present invention, the DRAM system communication architecture further comprises a peripheral circuit portion, wherein the peripheral circuit portion comprises a chip select signal decoder CS # DEC, and the CS # DEC facilitates a Memory Controller (MC) to control different DRAM chips of the DRAM, so as to prevent the memory controller MC from generating a large number of CS signals and from walking a long board-level bus.

According to the embodiment of the invention, the initialization is needed for the condition of large amount of data, such as data zero clearing. By using the framework, the high-efficiency and quick completion can be realized, and firstly, the CPU writes initialization data 0 to the chip C1 through the MC in a normal DRAM access mode. Then the system is switched to a fast data moving mode, and a proper DS switch direction is set to establish a multicast data path. And finally, copying the data from the C1 to a plurality of DRAM chips such as DRAM C2, C3 and the like through the steps of the MC control flow, and realizing quick initialization of the data.

It should be noted that during the data transfer process, the CPU can still complete the access to the DRAM through the MC. Specifically, when the data is moved among the DRAM chips in the Rank1, due to the isolation of the DS, the DQS and DQ signals of the Rank1 are separated from the data bus of the DRAM Channel, and the memory controller MC still allows the DQ of the Rank2 to be connected to the data bus of the Channel through the DS switch array configured with the Rank 2. Thus, a data path from the MC to the Rank2 is established, and the CPU can naturally access the data of the Rank2 under the condition that the Rank1 is in inter-slice data movement. This mode of operation can be hidden in the latency incurred by moving data.

According to the embodiment of the invention, through providing a data communication architecture which is based on DDR standard and is hierarchical in DRAM system chip, MC is utilized to set one DRAM chip C1 to be in a Read state, another DRAM chip C2 is set to be in a Write state, and data ports of C1 and C2 are connected together, at the moment, the output of C1 is the input of C2, so that the data which needs to be moved is Read out from C1 and written into C2, and when the DDR standard indicates that certain time sequence requirements are met, a Read/Write command is sent to realize seamless Read/Write operation, so that the existing inter-chip interconnection bus is utilized, data movement is always carried out with extremely high data bus utilization rate during data communication, a certain degree of parallel operation is realized, and the data communication architecture has the advantages of high efficiency, low energy consumption and low cost.

The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A dynamic random access memory system communication architecture, the system communication architecture based on a double rate synchronous dynamic random access memory standard, the system communication architecture comprising: a dynamic random access memory chip set, a data input/output switch circuit, a memory controller, wherein,

the data input/output switch circuit is a switch array for controlling the direction of the data input/output selection signal and the data input/output signal of each dynamic random access memory chip in the dynamic random access memory chip set, and the switch array is used for adjusting a phase shifter so as to adjust the phase of the data input/output selection signal and the phase of the data input/output signal in the writing state of the dynamic random access memory; wherein, the first and the second end of the pipe are connected with each other,

the data input/output switch circuit is used for establishing a data path from the memory controller to the dynamic random access memory chip and a data path of the data input/output signal between the dynamic random access memory chips;

the phase shifter is arranged in the data input and output switch circuit and is used for connecting the data input and output selection signal ports of the two dynamic random access memory chips, so that the data input and output selection signal ports of the read chip are used as input signals to be sent to the data input and output selection signal ports of the write chip after the phase of the data input and output selection signal of the read chip is shifted by 90 degrees;

the memory controller is used for independently controlling each dynamic random access memory chip through different chip selection signals so as to realize the movement of data from the reading operation of a source address dynamic random access memory chip to the writing operation of a target address dynamic random access memory chip;

the memory controller is used for controlling the switch array of the data input/output switch circuit so as to establish data paths among different dynamic random access memory chips.

2. The system communication architecture of claim 1, further comprising: a peripheral circuit portion including a chip select signal decoder that facilitates control of different ones of the DRAM chips by the memory controller.

3. The system communication architecture of claim 1, wherein a dynamic random access memory chip in the dynamic random access memory chipset comprises one of: DDR2, DDR3 and DDR4, wherein DDR represents double rate synchronous dynamic random access memory.

4. The system communication architecture of claim 1, wherein the mode of operation in which the memory controller supports inter-dynamic random access memory chip data movement comprises:

setting a read delay RL and a write delay WL through a configuration mode register at the initialization stage of the double-rate synchronous dynamic random access memory, and enabling the RL to be WL + 1;

the dynamic random access memory chip C1 receives a first activation command sent by the memory controller and a row address where source data is located;

the dynamic random access memory chip C2 receives a second activation command and a corresponding line of a destination address sent by the memory controller;

when the dynamic random access memory chip C1 meets a first preset time sequence parameter, receiving a read command and a source data target column sent by the memory controller;

when the dynamic random access memory chip C2 meets a second preset time sequence parameter, receiving a write command and a corresponding column of a destination address sent by the memory controller;

after the burst length value is preset, the above steps are repeated to realize the seamless read operation of the dynamic random access memory chip C1 to the seamless write operation of the dynamic random access memory chip C2.

5. The system communication architecture of claim 1, wherein the manner in which the data path is used to effect data movement comprises: within the dram chipset, each of the dram chips implements parallel data movement without resource conflicts.

6. The system communication architecture of claim 1, wherein the manner in which the data path is used to effect data movement comprises: and under the condition that the driving capacities of the data input and output selection signals and the data input and output signals of each dynamic random access memory chip meet preset conditions, driving at least two dynamic random access memory chips by using data read by one dynamic random access memory chip to realize one-to-many multiple data movement.

7. The system communication architecture of claim 1, wherein the means for enabling data movement further comprises: and in the same channel between the dynamic random access memory chip sets, driving the data read from one dynamic random access memory chip set to the other dynamic random access memory chip set to realize data movement.

8. The system communication architecture of claim 1, wherein the enabling movement of data from a source address dynamic random access memory chip read operation to a target address dynamic random access memory chip write operation comprises:

the read operation from a source address dynamic random access memory chip satisfies edge alignment of the data input output selection signal and the data input output signal in the source address dynamic random access memory chip;

the target address dynamic random access memory chip write operation satisfies the center alignment of the data input output selection signal and the data input output signal in the target address dynamic random access memory chip.