ES2113458T3 - Intercambio de lineas de datos y de reloj en buses de datos con formato multiple. - Google Patents

Intercambio de lineas de datos y de reloj en buses de datos con formato multiple.

Info

Publication number
ES2113458T3
ES2113458T3 ES93114208T ES93114208T ES2113458T3 ES 2113458 T3 ES2113458 T3 ES 2113458T3 ES 93114208 T ES93114208 T ES 93114208T ES 93114208 T ES93114208 T ES 93114208T ES 2113458 T3 ES2113458 T3 ES 2113458T3
Authority
ES
Spain
Prior art keywords
bus
data
clock
protocol
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93114208T
Other languages
English (en)
Inventor
William John Testin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technicolor USA Inc
Original Assignee
Thomson Consumer Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Consumer Electronics Inc filed Critical Thomson Consumer Electronics Inc
Application granted granted Critical
Publication of ES2113458T3 publication Critical patent/ES2113458T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

UN SISTEMA DE PROCESAMIENTO DE SEÑALES CONTROLADAS POR BUS INCLUYE UN BUS DE DATOS EN SERIE, QUE TIENE PRIMERA Y SEGUNDA LINEAS DE BUSES (SRRBUS1, SERBUS2), PARA ACOPLAR VARIOS PROCESADORES ESCLAVOS (160, 150) A UN PROCESADOR DE CONTROL MAESTRO CONTROL(MU)C). LOS DISPOSITIVOS ESCLAVOS REQUIEREN MAS DE UN PROTOCOLO DE BUS DE DATOS. CADA DISPOSITIVO ESCLAVO TIENE UN TERMINAL DE RELOJ DE BUS (CLOCK,SCL) Y UN TERMINAL DE DATOS DE BUS (DATA,SDA). LOS DISPOSITIVOS ESCLAVOS DEDICADOS A UN PROTOCOLO TIENEN SUS TERMINALES DE RELOJ CONECTADOS A LA LINEA DEL PRIMER BUS, Y SUS TERMINALES DE DATOS CONECTADOS A LA LINEA DEL SEGUNDO BUS. LOS DISPOSITIVOS ESCLAVOS DEDICADOS AL OTRO PROTOCOLO TIENEN SUS TERMINALES DE DATOS CONECTADOS A LA LINEA DEL PRIMER BUS, Y TERMINALES DE RELOJ CONECTADOS A LA LINEA DEL SEGUNDO BUS. EL PROCESADOR DE CONTROL CAMBIA EL PROTOCOLO QUE SE ESTA USANDO PARA GENERAR TRANSMISIONES DE BUS CONFORME SE REQUIERA, Y CAMBIA LA FUNCION DE LAS LINEAS DE BUSES CUANDO SE CONMUTAN ENTRE PROTOCOLOS DE BUS PARA EVITAR QUE SE DEN CIERTAS CONDICIONES CONFLICTIVAS DE BUSES.
ES93114208T 1992-09-18 1993-09-04 Intercambio de lineas de datos y de reloj en buses de datos con formato multiple. Expired - Lifetime ES2113458T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/947,669 US5376928A (en) 1992-09-18 1992-09-18 Exchanging data and clock lines on multiple format data buses

Publications (1)

Publication Number Publication Date
ES2113458T3 true ES2113458T3 (es) 1998-05-01

Family

ID=25486539

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93114208T Expired - Lifetime ES2113458T3 (es) 1992-09-18 1993-09-04 Intercambio de lineas de datos y de reloj en buses de datos con formato multiple.

Country Status (9)

Country Link
US (1) US5376928A (es)
EP (1) EP0588191B1 (es)
JP (1) JP2805579B2 (es)
KR (1) KR100281955B1 (es)
CN (1) CN1038452C (es)
ES (1) ES2113458T3 (es)
MX (1) MX9305711A (es)
MY (1) MY109682A (es)
SG (1) SG75764A1 (es)

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JP4733877B2 (ja) * 2001-08-15 2011-07-27 富士通セミコンダクター株式会社 半導体装置
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KR100443467B1 (ko) * 2002-05-07 2004-08-09 손권웅 무염 경사를 사용하여 체크무늬를 갖는 직물의 제조방법및 그 체크 무늬 직물
KR100654796B1 (ko) * 2004-11-16 2006-12-08 삼성전자주식회사 데이터수신장치 및 그 제어방법
US20090222603A1 (en) * 2004-11-16 2009-09-03 Koninklijke Philips Electronics N.V. Bus communication system
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US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
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US20150100713A1 (en) * 2013-10-08 2015-04-09 Qualcomm Incorporated Coexistence of i2c slave devices and camera control interface extension devices on a shared control data bus
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Also Published As

Publication number Publication date
JPH06205072A (ja) 1994-07-22
EP0588191B1 (en) 1998-03-04
MX9305711A (es) 1994-05-31
MY109682A (en) 1997-04-30
JP2805579B2 (ja) 1998-09-30
EP0588191A1 (en) 1994-03-23
KR940007698A (ko) 1994-04-27
CN1084986A (zh) 1994-04-06
US5376928A (en) 1994-12-27
KR100281955B1 (ko) 2001-02-15
SG75764A1 (en) 2000-10-24
CN1038452C (zh) 1998-05-20

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